From 4be3fd3076a05cc576d98b4adb9efa67b3dbd616 Mon Sep 17 00:00:00 2001 From: zhaohe Date: Fri, 12 Jan 2024 17:43:43 +0800 Subject: [PATCH] V1 --- led_test.fdc | 2 +- led_test.pds | 138 +++++++++++++++++++++++++++--- source/src/timecode/timecode_comparator.v | 58 +++++++++++++ source/src/top.v | 46 +++++----- source/src/ttl_input.v | 22 +++-- source/src/xsync_internal_generator.v | 26 +++++- 6 files changed, 243 insertions(+), 49 deletions(-) create mode 100644 source/src/timecode/timecode_comparator.v diff --git a/led_test.fdc b/led_test.fdc index 2514fc8..ab9f013 100644 --- a/led_test.fdc +++ b/led_test.fdc @@ -570,6 +570,6 @@ define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_DRIVE} {4} define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_SLEW} {SLOW} define_attribute {p:ex_rst_n} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:ex_rst_n} {PAP_IO_LOC} {M16} +define_attribute {p:ex_rst_n} {PAP_IO_LOC} {G13} define_attribute {p:ex_rst_n} {PAP_IO_VCCIO} {3.3} define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVTTL33} diff --git a/led_test.pds b/led_test.pds index 4bbb036..f5361df 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Fri Jan 12 14:25:50 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Fri Jan 12 17:39:58 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-01-12T14:24:24") + (_timespec "2024-01-12T16:11:04") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -87,7 +87,7 @@ ) (_file "source/src/xsync_internal_generator.v" (_format verilog) - (_timespec "2024-01-11T16:04:31") + (_timespec "2024-01-12T17:30:41") ) (_file "source/src/zutils/zutils_pwm_generator_advanced.v" (_format verilog) @@ -159,12 +159,16 @@ ) (_file "source/src/ttl_input.v" (_format verilog) - (_timespec "2024-01-12T14:20:08") + (_timespec "2024-01-12T16:27:36") ) (_file "source/src/zutils/zutils_signal_filter_advance.v" (_format verilog) (_timespec "2024-01-12T14:02:02") ) + (_file "source/src/timecode/timecode_comparator.v" + (_format verilog) + (_timespec "2024-01-12T17:32:04") + ) ) ) (_widget wgt_my_ips_src @@ -184,7 +188,7 @@ (_input (_file "led_test.fdc" (_format fdc) - (_timespec "2024-01-12T10:50:30") + (_timespec "2024-01-12T17:34:33") ) ) ) @@ -235,17 +239,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-01-12T14:25:50") + (_timespec "2024-01-12T17:34:42") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-01-12T14:25:48") + (_timespec "2024-01-12T17:34:40") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-01-12T14:25:50") + (_timespec "2024-01-12T17:34:42") ) ) ) @@ -255,9 +259,29 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) + (_db_output + (_file "synthesize/Top_syn.adf" + (_format adif) + (_timespec "2024-01-12T17:35:52") + ) + ) + (_output + (_file "synthesize/Top_syn.vm" + (_format structural_verilog) + (_timespec "2024-01-12T17:35:57") + ) + (_file "synthesize/Top.snr" + (_format text) + (_timespec "2024-01-12T17:36:01") + ) + (_file "synthesize/snr.db" + (_format text) + (_timespec "2024-01-12T17:36:01") + ) + ) ) (_widget wgt_tech_view (_attribute _click_to_run (_switch ON)) @@ -272,14 +296,34 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "device_map/Top_map.adf" + (_format adif) + (_timespec "2024-01-12T17:36:05") + ) + ) + (_output + (_file "device_map/Top_dmr.prt" + (_format text) + (_timespec "2024-01-12T17:36:04") + ) + (_file "device_map/Top.dmr" + (_format text) + (_timespec "2024-01-12T17:36:05") + ) + (_file "device_map/dmr.db" + (_format text) + (_timespec "2024-01-12T17:36:05") + ) + ) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-01-11T22:37:55") + (_timespec "2024-01-12T17:36:05") ) ) ) @@ -289,7 +333,39 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "place_route/Top_pnr.adf" + (_format adif) + (_timespec "2024-01-12T17:39:11") + ) + ) + (_output + (_file "place_route/Top.prr" + (_format text) + (_timespec "2024-01-12T17:39:11") + ) + (_file "place_route/Top_prr.prt" + (_format text) + (_timespec "2024-01-12T17:39:10") + ) + (_file "place_route/clock_utilization.txt" + (_format text) + (_timespec "2024-01-12T17:39:10") + ) + (_file "place_route/Top_plc.adf" + (_format adif) + (_timespec "2024-01-12T17:37:34") + ) + (_file "place_route/Top_pnr.netlist" + (_format text) + (_timespec "2024-01-12T17:39:11") + ) + (_file "place_route/prr.db" + (_format text) + (_timespec "2024-01-12T17:39:13") + ) + ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -298,8 +374,24 @@ (_attribute _click_to_run (_switch ON)) ) (_command cmd_report_post_pnr_timing - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) (_attribute _auto_exe_lock (_switch OFF)) + (_db_output + (_file "report_timing/Top_rtp.adf" + (_format adif) + (_timespec "2024-01-12T17:39:19") + ) + ) + (_output + (_file "report_timing/Top.rtr" + (_format text) + (_timespec "2024-01-12T17:39:20") + ) + (_file "report_timing/rtr.db" + (_format text) + (_timespec "2024-01-12T17:39:20") + ) + ) ) (_widget wgt_arch_browser (_attribute _click_to_run (_switch ON)) @@ -317,7 +409,25 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_output + (_file "generate_bitstream/Top.sbit" + (_format text) + (_timespec "2024-01-12T17:39:57") + ) + (_file "generate_bitstream/Top.smsk" + (_format text) + (_timespec "2024-01-12T17:39:57") + ) + (_file "generate_bitstream/Top.bgr" + (_format text) + (_timespec "2024-01-12T17:39:57") + ) + (_file "generate_bitstream/bgr.db" + (_format text) + (_timespec "2024-01-12T17:39:58") + ) + ) ) ) ) diff --git a/source/src/timecode/timecode_comparator.v b/source/src/timecode/timecode_comparator.v new file mode 100644 index 0000000..020a0f7 --- /dev/null +++ b/source/src/timecode/timecode_comparator.v @@ -0,0 +1,58 @@ +module timecode_comparator ( + input [31:0] timecodeA0, + input [31:0] timecodeA1, + input [31:0] timecodeB0, + input [31:0] timecodeB1, + output eq +); + + wire [7:0] a_frame; + wire [7:0] a_frame10; + wire [7:0] a_sec; + wire [7:0] a_sec10; + wire [7:0] a_min; + wire [7:0] a_min10; + wire [7:0] a_hour; + wire [7:0] a_hour10; + + wire [7:0] b_frame; + wire [7:0] b_frame10; + wire [7:0] b_sec; + wire [7:0] b_sec10; + wire [7:0] b_min; + wire [7:0] b_min10; + wire [7:0] b_hour; + wire [7:0] b_hour10; + + + assign a_frame = timecodeA0[7:0] & 8'b0000_1111; + assign a_frame10 = timecodeA0[15:8] & 8'b0000_0011; + assign a_sec = timecodeA0[23:16] & 8'b0000_1111; + assign a_sec10 = timecodeA0[31:24] & 8'b0000_0111; + assign a_min = timecodeA1[7:0] & 8'b0000_1111; + assign a_min10 = timecodeA1[15:8] & 8'b0000_0111; + assign a_hour = timecodeA1[23:16] & 8'b0000_1111; + assign a_hour10 = timecodeA1[31:24] & 8'b0000_0011; + + + assign b_frame = timecodeB0[7:0] & 8'b0000_1111; + assign b_frame10 = timecodeB0[15:8] & 8'b0000_0011; + assign b_sec = timecodeB0[23:16] & 8'b0000_1111; + assign b_sec10 = timecodeB0[31:24] & 8'b0000_0111; + assign b_min = timecodeB1[7:0] & 8'b0000_1111; + assign b_min10 = timecodeB1[15:8] & 8'b0000_0111; + assign b_hour = timecodeB1[23:16] & 8'b0000_1111; + assign b_hour10 = timecodeB1[31:24] & 8'b0000_0011; + + + + assign eq = a_frame == b_frame && + a_frame10 == b_frame10 && + a_sec == b_sec && + a_sec10 == b_sec10 && + a_min == b_min && + a_min10 == b_min10 && + a_hour == b_hour && + a_hour10 == b_hour10; + +endmodule diff --git a/source/src/top.v b/source/src/top.v index a741fb9..de5fb89 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -355,28 +355,28 @@ module Top ( .wr_en(reg_reader_bus_wr_en), .rd_data(ttlin1_rd_data), - .ttlin1(sync_ttl_in1), - .ttlin2(sync_ttl_in2), - .ttlin3(sync_ttl_in3), - .ttlin4(sync_ttl_in4), - - //指示灯 - .ttlin1_state_led(sync_ttl_in1_state_led), - .ttlin2_state_led(sync_ttl_in2_state_led), - .ttlin3_state_led(sync_ttl_in3_state_led), - .ttlin4_state_led(sync_ttl_in4_state_led), - - //原始信号 - .ttlin1_ext(ISIG_ttlin1_module_ext), - .ttlin2_ext(ISIG_ttlin2_module_ext), - .ttlin3_ext(ISIG_ttlin3_module_ext), - .ttlin4_ext(ISIG_ttlin4_module_ext), - - //分频后的信号 - .ttlin1_divide(ISIG_ttlin1_module_divide), - .ttlin2_divide(ISIG_ttlin2_module_divide), - .ttlin3_divide(ISIG_ttlin3_module_divide), - .ttlin4_divide(ISIG_ttlin4_module_divide) + .ttlin1(sync_ttl_in1), + .ttlin2(sync_ttl_in2), + .ttlin3(sync_ttl_in3), + .ttlin4(!sync_ttl_in4), //in4电路上进行了反向 + + //指示灯 + .ttlin1_state_led(sync_ttl_in1_state_led), + .ttlin2_state_led(sync_ttl_in2_state_led), + .ttlin3_state_led(sync_ttl_in3_state_led), + .ttlin4_state_led(sync_ttl_in4_state_led), + + //原始信号 + .ttlin1_ext(ISIG_ttlin1_module_ext), + .ttlin2_ext(ISIG_ttlin2_module_ext), + .ttlin3_ext(ISIG_ttlin3_module_ext), + .ttlin4_ext(ISIG_ttlin4_module_ext), + + //分频后的信号 + .ttlin1_divide(ISIG_ttlin1_module_divide), + .ttlin2_divide(ISIG_ttlin2_module_divide), + .ttlin3_divide(ISIG_ttlin3_module_divide), + .ttlin4_divide(ISIG_ttlin4_module_divide) ); /******************************************************************************* @@ -391,7 +391,7 @@ module Top ( .output_signal(ISIG_internal_100hz) ); - + // =========================================================================================================== diff --git a/source/src/ttl_input.v b/source/src/ttl_input.v index 57807d6..c6bb6aa 100644 --- a/source/src/ttl_input.v +++ b/source/src/ttl_input.v @@ -70,22 +70,25 @@ module ttl_input #( .reg2(r2_ttlin2_devide_factor), .reg3(r3_ttlin3_devide_factor), .reg4(r4_ttlin4_devide_factor), - + .reg5(r5_ttlin1_filter_factor), + .reg6(r6_ttlin2_filter_factor), + .reg7(r7_ttlin3_filter_factor), + .reg8(r8_ttlin4_filter_factor), .reg_wr_sig(reg_wr_sig), - .reg_index (reg_wr_index) + .reg_index(reg_wr_index) ); always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - r0_ttlin_en <= 0; + r0_ttlin_en <= 32'hffff_ffff; r1_ttlin1_devide_factor <= 0; r2_ttlin2_devide_factor <= 0; r3_ttlin3_devide_factor <= 0; r4_ttlin4_devide_factor <= 0; - r5_ttlin1_filter_factor <= 0; - r6_ttlin2_filter_factor <= 0; - r7_ttlin3_filter_factor <= 0; - r8_ttlin4_filter_factor <= 0; + r5_ttlin1_filter_factor <= 32'd02; + r6_ttlin2_filter_factor <= 32'd02; + r7_ttlin3_filter_factor <= 32'd02; + r8_ttlin4_filter_factor <= 32'd02; end else begin if (reg_wr_sig) begin case (reg_wr_index) @@ -98,7 +101,6 @@ module ttl_input #( 6: r6_ttlin2_filter_factor <= wr_data; 7: r7_ttlin3_filter_factor <= wr_data; 8: r8_ttlin4_filter_factor <= wr_data; - default: begin end endcase @@ -158,24 +160,28 @@ module ttl_input #( ztuils_sig_devide sig_devide1 ( .clk(clk), .rst_n(rst_n), + .devide(r1_ttlin1_devide_factor), .in(ttlin1_sig_af_filter), .out(ttlin1_sig_af_devide) ); ztuils_sig_devide sig_devide2 ( .clk(clk), .rst_n(rst_n), + .devide(r1_ttlin1_devide_factor), .in(ttlin2_sig_af_filter), .out(ttlin2_sig_af_devide) ); ztuils_sig_devide sig_devide3 ( .clk(clk), .rst_n(rst_n), + .devide(r1_ttlin1_devide_factor), .in(ttlin3_sig_af_filter), .out(ttlin3_sig_af_devide) ); ztuils_sig_devide sig_devide4 ( .clk(clk), .rst_n(rst_n), + .devide(r1_ttlin1_devide_factor), .in(ttlin4_sig_af_filter), .out(ttlin4_sig_af_devide) ); diff --git a/source/src/xsync_internal_generator.v b/source/src/xsync_internal_generator.v index bedc3e0..e4f3497 100644 --- a/source/src/xsync_internal_generator.v +++ b/source/src/xsync_internal_generator.v @@ -179,6 +179,15 @@ module xsync_internal_generator #( .out(ext_ttlinx_module_raw_sig) ); + wire timecode_start_trigger_sig; + timecode_comparator timecode_comparator_inst ( + .timecodeA0(ext_timecode_data[31:0]), + .timecodeA1(ext_timecode_data[63:32]), + .timecodeB0(r6_timecode0), + .timecodeB1(r7_timecode1), + .eq(timecode_start_trigger_sig) + ); + reg start_sig; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin @@ -202,7 +211,18 @@ module xsync_internal_generator #( end 1: begin //TIMECODE触发 - + if (ext_timecode_tigger_sig && timecode_start_trigger_sig) begin + rC_work_state[0] <= 1; + rC_work_state[31:1] <= 0; + end else if (reg_wr_sig && reg_wr_index == CTRL_REG_INDEX) begin + if (wr_data[0] == 1) begin + rC_work_state[0] <= 1; + rC_work_state[31:1] <= 0; + end else begin + rC_work_state[0] <= 0; + rC_work_state[31:1] <= 0; + end + end end 2, 3, 4, 5: begin //外部电平控制 @@ -264,8 +284,8 @@ module xsync_internal_generator #( /******************************************************************************* * smpte_timecode_clk_generator * *******************************************************************************/ - assign timecode0_wen = reg_wr_sig && reg_wr_index == 6; - assign timecode1_wen = reg_wr_sig && reg_wr_index == 7; + assign timecode0_wen = reg_wr_sig && reg_wr_index == 6; + assign timecode1_wen = reg_wr_sig && reg_wr_index == 7; timecode_generator #( .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)