From 5415715ff7509e9808b50e246d7a736600ddf1ae Mon Sep 17 00:00:00 2001 From: zhaohe Date: Sat, 23 Mar 2024 19:33:04 +0800 Subject: [PATCH] =?UTF-8?q?timecode=20=E6=B7=BB=E5=8A=A0=E9=A2=91=E7=8E=87?= =?UTF-8?q?=E6=8E=A2=E6=B5=8B=E5=8A=9F=E8=83=BD?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- led_test.pds | 22 +-- source/bak/internal_timecode_generator.v | 152 ------------------- source/src/input/timecode_input.v | 163 +++++++++++++++------ .../src/zutils/zutils_timecode_serial_data_gen.v | 147 ------------------- 4 files changed, 132 insertions(+), 352 deletions(-) diff --git a/led_test.pds b/led_test.pds index 2ae5cb8..5132bab 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sat Mar 23 17:15:21 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sat Mar 23 19:29:12 2024") (_version "1.0.5") (_status "initial") (_project @@ -123,7 +123,7 @@ ) (_file "source/src/timecode/timecode_generator.v" (_format verilog) - (_timespec "2024-03-04T16:13:49") + (_timespec "2024-03-23T19:26:35") ) (_file "source/src/output/timecode_output.v" (_format verilog) @@ -131,11 +131,11 @@ ) (_file "source/src/input/timecode_input.v" (_format verilog) - (_timespec "2024-03-04T20:17:07") + (_timespec "2024-03-23T19:14:39") ) (_file "source/src/timecode/timecode_decoder.v" (_format verilog) - (_timespec "2024-02-27T20:28:55") + (_timespec "2024-03-23T18:54:04") ) (_file "source/src/timecode/timecode_sample_sig_generator.v" (_format verilog) @@ -315,17 +315,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-03-23T17:12:28") + (_timespec "2024-03-23T19:28:26") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-03-23T17:12:25") + (_timespec "2024-03-23T19:28:24") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-03-23T17:12:28") + (_timespec "2024-03-23T19:28:26") ) ) ) @@ -341,21 +341,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-03-23T17:14:59") + (_timespec "2024-03-23T19:29:07") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-03-23T17:15:11") + (_timespec "2024-03-23T19:29:10") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-03-23T17:15:20") + (_timespec "2024-03-23T19:29:12") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-03-23T17:15:21") + (_timespec "2024-03-23T19:29:12") ) ) ) diff --git a/source/bak/internal_timecode_generator.v b/source/bak/internal_timecode_generator.v index e57956e..e69de29 100644 --- a/source/bak/internal_timecode_generator.v +++ b/source/bak/internal_timecode_generator.v @@ -1,152 +0,0 @@ - -// module internal_timecode_generator #( -// parameter SYS_CLOCK_FREQ = 10000000 -// ) ( -// input clk, //clock input -// input rst_n, //asynchronous reset input, low active - -// input ctrl_sig, - -// input [31:0] timecode_format, - -// input timecode_tc_wr_en, -// input [31:0] timecode_tc_wr_data, -// output reg [31:0] out_timecode_uc_reg, - -// input timecode_uc_wr_en, -// input [31:0] timecode_uc_wr_data, -// output reg [31:0] out_timecode_tc_reg, - -// output reg out_timecode_tirgger_sig -// ); - -// localparam FPS2398Format = 0; -// localparam FPS2400Format = 1; -// localparam FPS2500Format = 2; -// localparam FPS2997Format = 3; -// localparam FPS2997DropFormat = 4; -// localparam FPS3000Format = 5; - -// /******************************************************************************* -// * smpte_timecode_clk_generator * -// *******************************************************************************/ - -// wire timecode_sig_clk_output; -// zutils_smpte_timecode_clk_generator #( -// .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) -// ) smpte_timecode_clk_generator ( -// .clk(clk), -// .rst_n(rst_n), -// .ctrl_sig(ctrl_sig), -// .fps2398format_clk(fps2398format_clk), -// .fps2400format_clk(fps2400format_clk), -// .fps2500format_clk(fps2500format_clk), -// .fps2997format_clk(fps2997format_clk), -// .fps2997dropformat_clk(fps2997dropformat_clk), -// .fps3000format_clk(fps3000format_clk) -// ); - -// zutils_multiplexer_32t1_v2 timecode_clk_output_mult ( -// .chooseindex(timecode_format), -// //in -// .in0(fps2398format_clk), -// .in1(fps2400format_clk), -// .in2(fps2500format_clk), -// .in3(fps2997format_clk), -// .in4(fps2997dropformat_clk), -// .in5(fps3000format_clk), -// //out -// .out(timecode_sig_clk_output) -// ); - -// zutils_edge_detecter timecode_sig_clk_output_edge_detecter ( -// .clk(clk), -// .rst_n(rst_n), -// .in_signal(timecode_sig_clk_output), -// .in_signal_rising_edge(timecode_sig_clk_output_rising_edge) -// ); - -// reg [7:0] frameNum; -// reg timecode_drop_frame; -// wire [31:0] timecode_next; - -// always @(*) begin -// case (timecode_format) -// FPS2398Format: begin -// frameNum <= 24; -// timecode_drop_frame <= 0; -// end -// FPS2400Format: begin -// frameNum <= 24; -// timecode_drop_frame <= 0; -// end -// FPS2500Format: begin -// frameNum <= 25; -// timecode_drop_frame <= 0; -// end -// FPS2997Format: begin -// frameNum <= 30; -// timecode_drop_frame <= 0; -// end -// FPS2997DropFormat: begin -// frameNum <= 30; -// timecode_drop_frame <= 0; -// end -// default begin -// frameNum <= 30; -// timecode_drop_frame <= 0; -// end -// endcase -// end - -// ztutils_timecode_next_code ztutils_timecode_next_code_inst ( -// .timecode(out_timecode_tc_reg), -// .frameNum(frameNum), -// .drop(timecode_drop_frame), -// .timecode_next(timecode_next) -// ); - -// reg n_first_timecode_sig; - -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n || !ctrl_sig) begin -// n_first_timecode_sig <= 0; -// end else begin -// if (!n_first_timecode_sig && timecode_sig_clk_output_rising_edge) begin -// n_first_timecode_sig <= 1; -// end -// end -// end - -// // always @(posedge clk or negedge rst_n) begin -// // if (!rst_n) begin -// // out_timecode_tc_reg <= 0; -// // out_timecode_uc_reg <= 0; -// // end else begin - -// // if (timecode_tc_wr_en) begin -// // //外都写入时间码 -// // out_timecode_tc_reg <= timecode_tc_wr_data; -// // end else if (timecode_uc_wr_en) begin -// // //外都写入时间码-用户码 -// // out_timecode_uc_reg <= timecode_uc_wr_data; -// // end else begin - -// // if (timecode_sig_clk_output_rising_edge) begin -// // //第一次触发，不改变时间码 -// // if (!n_first_timecode_sig) begin -// // out_timecode_tc_reg <= out_timecode_tc_reg; -// // end else begin -// // out_timecode_tc_reg <= timecode_next; -// // end -// // out_timecode_tirgger_sig <= 1; -// // end else begin -// // out_timecode_tirgger_sig <= 0; -// // end -// // end -// // end -// // end - - - -// endmodule diff --git a/source/src/input/timecode_input.v b/source/src/input/timecode_input.v index 3f06963..fe4014b 100644 --- a/source/src/input/timecode_input.v +++ b/source/src/input/timecode_input.v @@ -17,10 +17,10 @@ module timecode_input_parser #( /******************************************************************************* * TIMECODE输出 * *******************************************************************************/ - output timecode_tigger_sig, - output [31:0] timecode_format, - output [63:0] timecode_data, - output timecode_serial_data, + output reg timecode_tigger_sig, + output reg [31:0] timecode_format, + output reg [63:0] timecode_data, + output reg timecode_serial_data, /******************************************************************************* * 指示灯状态输出 * @@ -32,38 +32,54 @@ module timecode_input_parser #( reg [31:0] r1_timecode_sig_selt; //信号源选择 0:off,1:bnc,2:headphone - reg [31:0] r2_timecode_format; // - reg [31:0] r3_timecode0; // - reg [31:0] r4_timecode1; // + reg [31:0] r2_ch1_timecode_format; // + reg [31:0] r3_ch1_timecode0; // + reg [31:0] r4_ch1_timecode1; // + wire [31:0] r5_ch1_freq; // + reg [31:0] r6_ch2_timecode_format; // + reg [31:0] r7_ch2_timecode0; // + reg [31:0] r8_ch2_timecode1; // + wire [31:0] r9_ch2_freq; // + reg [31:0] rA_freq_bias; // + + wire [31:0] reg_wr_index; zutils_register_advanced #( .REG_START_ADD(REG_START_ADD) ) _register ( - .clk(clk), - .rst_n(rst_n), - .addr(addr), + .clk (clk), + .rst_n (rst_n), + .addr (addr), .wr_data(wr_data), - .wr_en(wr_en), + .wr_en (wr_en), .rd_data(rd_data), - .reg1(r1_timecode_sig_selt), - .reg2(r2_timecode_format), - .reg3(r3_timecode0), - .reg4(r4_timecode1), - + .reg1 (r1_timecode_sig_selt), + .reg2 (r2_ch1_timecode_format), + .reg3 (r3_ch1_timecode0), + .reg4 (r4_ch1_timecode1), + .reg5 (r5_ch1_freq), + .reg6 (r6_ch2_timecode_format), + .reg7 (r7_ch2_timecode0), + .reg8 (r8_ch2_timecode1), + .reg9 (r9_ch2_freq), + .regA (rA_freq_bias), .reg_wr_sig(reg_wr_sig), .reg_index (reg_wr_index) ); always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - r1_timecode_sig_selt <= 1; - r2_timecode_format <= 0; + r1_timecode_sig_selt <= 1; + r2_ch1_timecode_format <= 0; + r6_ch2_timecode_format <= 0; end else begin if (reg_wr_sig) begin case (reg_wr_index) 31'h1: r1_timecode_sig_selt <= wr_data; - 31'h2: r2_timecode_format <= wr_data; + 31'h2: r2_ch1_timecode_format <= wr_data; + 31'h6: r6_ch2_timecode_format <= wr_data; + 31'hA: rA_freq_bias <= wr_data; default: begin end endcase @@ -71,43 +87,106 @@ module timecode_input_parser #( end end - wire timecode_in_af_selt; - zutils_multiplexer_4t1 _signal_select ( - .chooseindex(r1_timecode_sig_selt), - .signal0(1'b0), - .signal1(timecode_bnc_in), - .signal2(timecode_headphone_in), - .signalout(timecode_in_af_selt) + + wire ch1_timecode_tigger_sig; + wire [31:0] ch1_timecode_format; + wire [63:0] ch1_timecode_data; + wire ch1_timecode_serial_data; + + wire ch2_timecode_tigger_sig; + wire [31:0] ch2_timecode_format; + wire [63:0] ch2_timecode_data; + wire ch2_timecode_serial_data; + + timecode_decoder #( + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) timecode_decoder_1 ( + .clk (clk), + .rst_n (rst_n), + .timecode_in (timecode_bnc_in), // 时码输入 + .timecode_tigger_sig (ch1_timecode_tigger_sig), // + .timecode_data (ch1_timecode_data), //[63:0] + .timecode_serial_data(ch1_timecode_serial_data) // ); + zutils_freq_detector_v2 freq_detector1 ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(rA_freq_bias), + .pluse_input (ch1_timecode_tigger_sig), + .pluse_width_cnt (r5_ch1_freq) +); + timecode_decoder #( - .SYS_CLOCK_FREQ(10000000) - ) timecode_decoder_ins ( - .clk(clk), - .rst_n(rst_n), - .timecode_in(timecode_in_af_selt), // 时码输入 - .timecode_tigger_sig(timecode_tigger_sig), // - .timecode_data(timecode_data), //[63:0] - .timecode_serial_data(timecode_serial_data) // + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) timecode_decoder_2 ( + .clk (clk), + .rst_n (rst_n), + .timecode_in (timecode_headphone_in), // 时码输入 + .timecode_tigger_sig (ch2_timecode_tigger_sig), // + .timecode_data (ch2_timecode_data), //[63:0] + .timecode_serial_data(ch2_timecode_serial_data) // ); + zutils_freq_detector_v2 freq_detector2 ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(rA_freq_bias), + .pluse_input (ch2_timecode_tigger_sig), + .pluse_width_cnt (r9_ch2_freq) + ); always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - r3_timecode0 <= 0; - r4_timecode1 <= 0; + r3_ch1_timecode0 <= 0; + r4_ch1_timecode1 <= 0; + r7_ch2_timecode0 <= 0; + r8_ch2_timecode1 <= 0; end else begin - if (timecode_tigger_sig) begin - r3_timecode0 <= timecode_data[31:0]; - r4_timecode1 <= timecode_data[63:32]; + if (ch1_timecode_tigger_sig) begin + r3_ch1_timecode0 <= ch1_timecode_data[31:0]; + r4_ch1_timecode1 <= ch1_timecode_data[63:32]; + end + + if (ch2_timecode_tigger_sig) begin + r7_ch2_timecode0 <= ch2_timecode_data[31:0]; + r8_ch2_timecode1 <= ch2_timecode_data[63:32]; end end end - assign timecode_format = r2_timecode_format; - assign timecode_headphone_in_state_led = 1; - assign timecode_bnc_in_state_led = 1; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + timecode_tigger_sig <= 0; + timecode_format <= 32'hF; + timecode_data <= 0; + timecode_serial_data <= 0; + end else begin + case (r1_timecode_sig_selt) + 1: begin + timecode_tigger_sig <= ch1_timecode_tigger_sig; + timecode_format <= r2_ch1_timecode_format; + timecode_data <= ch1_timecode_data; + timecode_serial_data <= ch1_timecode_serial_data; + end + 2: begin + timecode_tigger_sig <= ch2_timecode_tigger_sig; + timecode_format <= r6_ch2_timecode_format; + timecode_data <= ch2_timecode_data; + timecode_serial_data <= ch2_timecode_serial_data; + end + default: begin + timecode_tigger_sig <= 0; + timecode_format <= 32'hF; + timecode_data <= 0; + timecode_serial_data <= 0; + end + endcase + end + end + assign timecode_headphone_in_state_led = 1; + assign timecode_bnc_in_state_led = 1; endmodule diff --git a/source/src/zutils/zutils_timecode_serial_data_gen.v b/source/src/zutils/zutils_timecode_serial_data_gen.v index 473097f..e69de29 100644 --- a/source/src/zutils/zutils_timecode_serial_data_gen.v +++ b/source/src/zutils/zutils_timecode_serial_data_gen.v @@ -1,147 +0,0 @@ - -// module internal_timecode_generator #( -// parameter SYS_CLOCK_FREQ = 10000000 -// ) ( -// input clk, //clock input -// input rst_n, //asynchronous reset input, low active - -// input [31:0] timecode_format, - - -// input trigger_sig, -// input [31:0] timecode_tc_data, -// input [31:0] timecode_uc_data, - -// output reg out_timecode_serial_data, -// output reg out_trigger_sig, -// output reg [31:0] out_timecode_tc_data, -// output reg [31:0] out_timecode_uc_data -// ); - -// // Rate 1/2Fe 1Fe -// // 23.98 F/s 260.7 us 521.4 us -// // 24.00 F/s 260.4 us 520.8 us -// // 25.00 F/s 250.0 us 500.0 us -// // 29.97 F/s 208.5 us 417.1 us -// // 30.00 F/s 208.3 us 416.7 us - -// localparam FPS2398Format = 0; -// localparam FPS2400Format = 1; -// localparam FPS2500Format = 2; -// localparam FPS2997Format = 3; -// localparam FPS2997DropFormat = 4; -// localparam FPS3000Format = 5; - -// localparam FPS2398FormatOneHalfFe = (260.7 * 1000) / (1000000000 / SYS_CLOCK_FREQ); -// localparam FPS2400FormatOneHalfFe = (260.4 * 1000) / (1000000000 / SYS_CLOCK_FREQ); -// localparam FPS2500FormatOneHalfFe = (250.0 * 1000) / (1000000000 / SYS_CLOCK_FREQ); -// localparam FPS2997FormatOneHalfFe = (208.5 * 1000) / (1000000000 / SYS_CLOCK_FREQ); -// localparam FPS2997DropFormatOneHalfFe = (208.5 * 1000) / (1000000000 / SYS_CLOCK_FREQ); -// localparam FPS3000FormatOneHalfFe = (208.3 * 1000) / (1000000000 / SYS_CLOCK_FREQ); - -// reg [31:0] timecode_onehalf_bit_count; -// always @(*) begin -// case (freqtimecode_format) -// FPS2398Format: timecode_onehalf_bit_count = FPS2398FormatOneHalfFe; -// FPS2400Format: timecode_onehalf_bit_count = FPS2400FormatOneHalfFe; -// FPS2500Format: timecode_onehalf_bit_count = FPS2500FormatOneHalfFe; -// FPS2997Format: timecode_onehalf_bit_count = FPS2997FormatOneHalfFe; -// FPS2997DropFormat: timecode_onehalf_bit_count = FPS2997DropFormatOneHalfFe; -// FPS3000Format: timecode_onehalf_bit_count = FPS3000FormatOneHalfFe; -// default: timecode_onehalf_bit_count = FPS2398FormatOneHalfFe; -// endcase -// end - -// /******************************************************************************* -// * workflag * -// *******************************************************************************/ -// reg workflag; -// reg endsig; -// // -// // -// reg [31:0] timecode_tc_cache; -// reg [31:0] timecode_uc_cache; -// reg [64:0] timecode_bit_val; -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// workflag <= 0; -// timecode_tc_cache <= 0; -// timecode_uc_cache <= 0; -// end else begin -// if (trigger_sig) begin -// timecode_tc_cache <= timecode_tc_data; -// timecode_uc_cache <= timecode_uc_data; - - - -// workflag <= 1; -// end else if (workflag && endsig) begin -// workflag <= 0; -// end -// end -// end - -// /******************************************************************************* -// * tigger_sig * -// *******************************************************************************/ -// reg [31:0] halfbitcount; -// reg tigger_sig; -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n || !workflag) begin -// halfbitcount <= 0; -// tigger_sig <= 0; -// end else begin -// if (halfbitcount == timecode_onehalf_bit_count) begin -// halfbitcount <= 0; -// end else begin -// halfbitcount <= halfbitcount + 1; -// end - -// if (halfbitcount == 0) begin -// tigger_sig <= 1; -// end else begin -// tigger_sig <= 0; -// end -// end -// end - -// // -// // trigger : | | | | | | -// // onebitoff: 0000000001111111111000000001111111110000000001 -// // bitoff : 0000000000000000000111111111111111112222222222 -// // -// // - -// reg [ 1:0] onebitoff; -// reg [31:0] bitoff; -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n || !workflag) begin -// onebitoff <= 1; -// bitoff <= 0; -// end else begin -// if (tigger_sig) begin -// if (onebit_off == 1) begin -// bitoff <= bitoff + 1; -// onebit_off <= 0; -// end else begin -// onebit_off <= 1; -// end -// end -// end -// end - - - - -// reg change_sig; - - - - - - - - - - -// endmodule