diff --git a/README.md b/README.md
index 2b8b692..f0e95dc 100644
--- a/README.md
+++ b/README.md
@@ -2,6 +2,10 @@
 https://iflytop1.feishu.cn/docx/Fk3CdIRNZoal1XxCGgjc9q1Dn1f
 固化
 https://iflytop1.feishu.cn/wiki/DyHLwd2pLicjXxkWNEvc7vI7n2b
+
+
+cfg_gen_sfc -device_name W25Q128Q -opcode 107 -sbit_start_address 0 -sbit D:/workspace/p_lusterinc/xsync_fpge/generate_bitstream/Top.sbit
+
 ```
 
 ```
diff --git a/led_test.pds b/led_test.pds
index 3c0d257..b8e2a34 100644
--- a/led_test.pds
+++ b/led_test.pds
@@ -1,5 +1,5 @@
 (_flow fab_demo "2021.1-SP7"
-    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Thu Apr 11 09:37:35 2024")
+    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Apr 15 09:55:22 2024")
     (_version "1.0.5")
     (_status "initial")
     (_project 
@@ -123,7 +123,7 @@
                 )
                 (_file "source/src/timecode/timecode_generator.v"
                     (_format verilog)
-                    (_timespec "2024-04-11T09:27:05")
+                    (_timespec "2024-04-15T09:01:50")
                 )
                 (_file "source/src/output/timecode_output.v"
                     (_format verilog)
@@ -207,7 +207,7 @@
                 )
                 (_file "source/src/output/camera_sync_signal_output.v"
                     (_format verilog)
-                    (_timespec "2024-04-11T09:29:51")
+                    (_timespec "2024-04-15T09:44:45")
                 )
                 (_file "source/src/business/record_sig_generator.v"
                     (_format verilog)
@@ -233,6 +233,10 @@
                     (_format verilog)
                     (_timespec "2024-03-23T16:58:20")
                 )
+                (_file "source/src/zutils/zutils_timer.v"
+                    (_format verilog)
+                    (_timespec "2024-04-15T09:16:39")
+                )
             )
         )
         (_widget wgt_my_ips_src
@@ -315,17 +319,17 @@
             (_db_output
                 (_file "compile/Top_comp.adf"
                     (_format adif)
-                    (_timespec "2024-04-11T09:30:16")
+                    (_timespec "2024-04-15T09:44:53")
                 )
             )
             (_output
                 (_file "compile/Top.cmr"
                     (_format verilog)
-                    (_timespec "2024-04-11T09:30:13")
+                    (_timespec "2024-04-15T09:44:50")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2024-04-11T09:30:16")
+                    (_timespec "2024-04-15T09:44:53")
                 )
             )
         )
@@ -341,21 +345,21 @@
             (_db_output
                 (_file "synthesize/Top_syn.adf"
                     (_format adif)
-                    (_timespec "2024-04-11T09:30:51")
+                    (_timespec "2024-04-15T09:45:30")
                 )
             )
             (_output
                 (_file "synthesize/Top_syn.vm"
                     (_format structural_verilog)
-                    (_timespec "2024-04-11T09:30:53")
+                    (_timespec "2024-04-15T09:45:32")
                 )
                 (_file "synthesize/Top.snr"
                     (_format text)
-                    (_timespec "2024-04-11T09:30:54")
+                    (_timespec "2024-04-15T09:45:34")
                 )
                 (_file "synthesize/snr.db"
                     (_format text)
-                    (_timespec "2024-04-11T09:30:54")
+                    (_timespec "2024-04-15T09:45:34")
                 )
             )
         )
@@ -376,21 +380,21 @@
             (_db_output
                 (_file "device_map/Top_map.adf"
                     (_format adif)
-                    (_timespec "2024-04-11T09:31:00")
+                    (_timespec "2024-04-15T09:45:42")
                 )
             )
             (_output
                 (_file "device_map/Top_dmr.prt"
                     (_format text)
-                    (_timespec "2024-04-11T09:30:57")
+                    (_timespec "2024-04-15T09:45:39")
                 )
                 (_file "device_map/Top.dmr"
                     (_format text)
-                    (_timespec "2024-04-11T09:31:00")
+                    (_timespec "2024-04-15T09:45:42")
                 )
                 (_file "device_map/dmr.db"
                     (_format text)
-                    (_timespec "2024-04-11T09:31:00")
+                    (_timespec "2024-04-15T09:45:43")
                 )
             )
         )
@@ -399,7 +403,7 @@
             (_input
                 (_file "device_map/led_test.pcf"
                     (_format pcf)
-                    (_timespec "2024-04-11T09:31:00")
+                    (_timespec "2024-04-15T09:45:42")
                 )
             )
         )
@@ -420,33 +424,33 @@
             (_db_output
                 (_file "place_route/Top_pnr.adf"
                     (_format adif)
-                    (_timespec "2024-04-11T09:36:21")
+                    (_timespec "2024-04-15T09:54:52")
                 )
             )
             (_output
                 (_file "place_route/Top.prr"
                     (_format text)
-                    (_timespec "2024-04-11T09:36:21")
+                    (_timespec "2024-04-15T09:54:53")
                 )
                 (_file "place_route/Top_prr.prt"
                     (_format text)
-                    (_timespec "2024-04-11T09:36:19")
+                    (_timespec "2024-04-15T09:54:52")
                 )
                 (_file "place_route/clock_utilization.txt"
                     (_format text)
-                    (_timespec "2024-04-11T09:36:19")
+                    (_timespec "2024-04-15T09:54:52")
                 )
                 (_file "place_route/Top_plc.adf"
                     (_format adif)
-                    (_timespec "2024-04-11T09:31:51")
+                    (_timespec "2024-04-15T09:48:13")
                 )
                 (_file "place_route/Top_pnr.netlist"
                     (_format text)
-                    (_timespec "2024-04-11T09:36:21")
+                    (_timespec "2024-04-15T09:54:53")
                 )
                 (_file "place_route/prr.db"
                     (_format text)
-                    (_timespec "2024-04-11T09:36:23")
+                    (_timespec "2024-04-15T09:54:53")
                 )
             )
         )
@@ -462,17 +466,17 @@
             (_db_output
                 (_file "report_timing/Top_rtp.adf"
                     (_format adif)
-                    (_timespec "2024-04-11T09:36:32")
+                    (_timespec "2024-04-15T09:55:01")
                 )
             )
             (_output
                 (_file "report_timing/Top.rtr"
                     (_format text)
-                    (_timespec "2024-04-11T09:36:34")
+                    (_timespec "2024-04-15T09:55:02")
                 )
                 (_file "report_timing/rtr.db"
                     (_format text)
-                    (_timespec "2024-04-11T09:36:36")
+                    (_timespec "2024-04-15T09:55:02")
                 )
             )
         )
@@ -497,19 +501,19 @@
             (_output
                 (_file "generate_bitstream/Top.sbit"
                     (_format text)
-                    (_timespec "2024-04-11T09:37:33")
+                    (_timespec "2024-04-15T09:55:22")
                 )
                 (_file "generate_bitstream/Top.smsk"
                     (_format text)
-                    (_timespec "2024-04-11T09:37:33")
+                    (_timespec "2024-04-15T09:55:22")
                 )
                 (_file "generate_bitstream/Top.bgr"
                     (_format text)
-                    (_timespec "2024-04-11T09:37:33")
+                    (_timespec "2024-04-15T09:55:22")
                 )
                 (_file "generate_bitstream/bgr.db"
                     (_format text)
-                    (_timespec "2024-04-11T09:37:35")
+                    (_timespec "2024-04-15T09:55:22")
                 )
             )
         )
diff --git a/release/v0.0.5/Top005.sbit b/release/v0.0.5/Top005.sbit
new file mode 100644
index 0000000..40b0d4d
Binary files /dev/null and b/release/v0.0.5/Top005.sbit differ
diff --git a/release/v0.0.5/Top005.sfc b/release/v0.0.5/Top005.sfc
new file mode 100644
index 0000000..653750a
Binary files /dev/null and b/release/v0.0.5/Top005.sfc differ
diff --git a/source/src/config.v b/source/src/config.v
index 61696cc..c84bbbe 100644
--- a/source/src/config.v
+++ b/source/src/config.v
@@ -43,4 +43,4 @@
 `define TTL_OUTPUT_TRIGGER_MODE_SIG_WIDTH 32'd1000
 `define FREQ_DETECT_BIAS_DEFAULT 32'd10
 `define EXT_TIMECODE_FREQ_DETECT_BIAS_DEFAULT 32'd500
-`define VERSION 32'd4
+`define VERSION 32'd5
diff --git a/source/src/output/camera_sync_signal_output.v b/source/src/output/camera_sync_signal_output.v
index 6b4aaac..c7d494a 100644
--- a/source/src/output/camera_sync_signal_output.v
+++ b/source/src/output/camera_sync_signal_output.v
@@ -92,9 +92,20 @@ module camera_sync_signal_output #(
   reg  [31:0] reg4_sub_frame_cnt_cache;
   wire [ 1:0] trigger_sig;
 
+  reg         timecode_is_ready_sig;
+
   assign trigger_sig[0] = frame_sig_rising_edge;
   assign trigger_sig[1] = in_timecode_tigger_sig;
 
+  zutils_timer #(
+      .MAX_CNT(SYS_CLOCK_FREQ / 10)
+  ) _timecode_ready_clear_timer (
+      .clk    (clk),
+      .rst_n  (rst_n),
+      .trigger(in_timecode_tigger_sig),
+      .ready  (timecode_ready_clear_timer_ready)
+  );
+
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
       reg2_timecode_snapshot0  <= 0;
@@ -103,7 +114,16 @@ module camera_sync_signal_output #(
       timecode_data_cache0     <= 0;
       timecode_data_cache1     <= 0;
       reg4_sub_frame_cnt_cache <= 0;
+      timecode_is_ready_sig    <= 0;
     end else begin
+
+      if (in_timecode_tigger_sig) begin
+        timecode_is_ready_sig <= 1;
+      end else if (timecode_is_ready_sig & timecode_ready_clear_timer_ready) begin
+        timecode_is_ready_sig <= 0;
+      end
+
+
       case (trigger_sig)
         2'b01: begin
           //帧触发信号
@@ -147,7 +167,7 @@ module camera_sync_signal_output #(
       .output_signal(frame_sig_fa_process)
   );
 
-  assign stm32if_camera_sync_out         = frame_sig_fa_process;
+  assign stm32if_camera_sync_out         = frame_sig_fa_process & timecode_is_ready_sig;
   assign stm32if_record_state_change_sig = record_en_sig;
   assign stm32if_timecode_tigger_sig     = 0;
 
diff --git a/source/src/timecode/timecode_generator.v b/source/src/timecode/timecode_generator.v
index 7e34738..2cc39dd 100644
--- a/source/src/timecode/timecode_generator.v
+++ b/source/src/timecode/timecode_generator.v
@@ -69,9 +69,9 @@ module timecode_generator #(
         end
       end else begin
         if (frame_trigger_sig) begin
-          // if (!first_frame_sig) begin
+          if (!first_frame_sig) begin
             timecode <= timecode_next;
-          // end
+          end
           timecode_trigger_sig <= 1;
         end else begin
           timecode_trigger_sig <= 0;
diff --git a/source/src/zutils/zutils_timer.v b/source/src/zutils/zutils_timer.v
new file mode 100644
index 0000000..39229c6
--- /dev/null
+++ b/source/src/zutils/zutils_timer.v
@@ -0,0 +1,32 @@
+module zutils_timer #(
+    parameter MAX_CNT = 1000
+) (
+    input clk,   //clock input
+    input rst_n, //asynchronous reset input, low active
+
+    input      trigger,
+    output reg ready
+);
+
+  reg [31:0] time_cnt = 0;
+
+  always @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      time_cnt <= 0;
+      ready    <= 0;
+    end else begin
+      if (trigger) begin
+        time_cnt <= 0;
+        ready    <= 0;
+      end else begin
+        if (time_cnt >= MAX_CNT) begin
+          ready    <= 1;
+        end else begin
+          time_cnt <= time_cnt + 1;
+          ready    <= 0;
+        end
+      end
+    end
+  end
+
+endmodule