diff --git a/led_test.fdc b/led_test.fdc index 2a4b1d6..2514fc8 100644 --- a/led_test.fdc +++ b/led_test.fdc @@ -297,54 +297,54 @@ define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_VCCIO} {3.3} define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DRIVE} {4} define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_SLEW} {SLOW} -define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_LOC} {D13} -define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_DRIVE} {4} -define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_LOC} {D15} -define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_DRIVE} {4} -define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_LOC} {C15} -define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_DRIVE} {4} -define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_LOC} {E15} -define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_DRIVE} {4} -define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_LOC} {E16} -define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_DRIVE} {4} -define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_LOC} {A17} -define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_DRIVE} {4} -define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_LOC} {B17} -define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_DRIVE} {4} -define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_LOC} {B18} -define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_DRIVE} {4} -define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_SLEW} {SLOW} +# define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_DIRECTION} {OUTPUT} +# define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_LOC} {D13} +# define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_STANDARD} {LVCMOS33} +# define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_DRIVE} {4} +# define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_SLEW} {SLOW} +# define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_DIRECTION} {OUTPUT} +# define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_LOC} {D15} +# define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_STANDARD} {LVCMOS33} +# define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_DRIVE} {4} +# define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_SLEW} {SLOW} +# define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_DIRECTION} {OUTPUT} +# define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_LOC} {C15} +# define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_STANDARD} {LVCMOS33} +# define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_DRIVE} {4} +# define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_SLEW} {SLOW} +# define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_DIRECTION} {OUTPUT} +# define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_LOC} {E15} +# define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_STANDARD} {LVCMOS33} +# define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_DRIVE} {4} +# define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_SLEW} {SLOW} +# define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_DIRECTION} {OUTPUT} +# define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_LOC} {E16} +# define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_STANDARD} {LVCMOS33} +# define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_DRIVE} {4} +# define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_SLEW} {SLOW} +# define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_DIRECTION} {OUTPUT} +# define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_LOC} {A17} +# define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_STANDARD} {LVCMOS33} +# define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_DRIVE} {4} +# define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_SLEW} {SLOW} +# define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_DIRECTION} {OUTPUT} +# define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_LOC} {B17} +# define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_STANDARD} {LVCMOS33} +# define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_DRIVE} {4} +# define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_SLEW} {SLOW} +# define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_DIRECTION} {OUTPUT} +# define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_LOC} {B18} +# define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_VCCIO} {3.3} +# define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_STANDARD} {LVCMOS33} +# define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_DRIVE} {4} +# define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_SLEW} {SLOW} # define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT} # define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {P17} # define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3} diff --git a/led_test.pds b/led_test.pds index 661f85e..2a5c2c2 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Thu Jan 11 16:07:12 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Thu Jan 11 18:45:46 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-01-11T15:58:27") + (_timespec "2024-01-11T18:41:05") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -27,7 +27,7 @@ ) (_file "source/src/zutils/zutils_pluse_generator.v" (_format verilog) - (_timespec "2024-01-10T20:51:41") + (_timespec "2024-01-11T16:29:59") ) (_file "source/src/zutils/zutils_edge_detecter.v" (_format verilog) @@ -133,6 +133,10 @@ (_format verilog) (_timespec "2024-01-11T15:07:28") ) + (_file "source/src/timecode_output.v" + (_format verilog) + (_timespec "2024-01-11T18:42:04") + ) ) ) (_widget wgt_my_ips_src @@ -152,7 +156,7 @@ (_input (_file "led_test.fdc" (_format fdc) - (_timespec "2024-01-10T22:05:26") + (_timespec "2024-01-11T18:29:17") ) ) ) @@ -195,21 +199,21 @@ ) (_task tsk_compile (_command cmd_compile - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-01-11T15:27:50") + (_timespec "2024-01-11T18:42:10") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-01-11T15:27:48") + (_timespec "2024-01-11T18:42:08") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-01-11T15:27:50") + (_timespec "2024-01-11T18:42:10") ) ) ) @@ -219,27 +223,27 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-01-11T15:28:05") + (_timespec "2024-01-11T18:42:55") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-01-11T15:28:06") + (_timespec "2024-01-11T18:42:58") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-01-11T15:28:07") + (_timespec "2024-01-11T18:43:01") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-01-11T15:28:07") + (_timespec "2024-01-11T18:43:01") ) ) ) @@ -256,14 +260,34 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "device_map/Top_map.adf" + (_format adif) + (_timespec "2024-01-11T18:43:07") + ) + ) + (_output + (_file "device_map/Top_dmr.prt" + (_format text) + (_timespec "2024-01-11T18:43:06") + ) + (_file "device_map/Top.dmr" + (_format text) + (_timespec "2024-01-11T18:43:07") + ) + (_file "device_map/dmr.db" + (_format text) + (_timespec "2024-01-11T18:43:08") + ) + ) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-01-11T11:47:31") + (_timespec "2024-01-11T18:43:07") ) ) ) @@ -273,7 +297,39 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "place_route/Top_pnr.adf" + (_format adif) + (_timespec "2024-01-11T18:45:10") + ) + ) + (_output + (_file "place_route/Top.prr" + (_format text) + (_timespec "2024-01-11T18:45:10") + ) + (_file "place_route/Top_prr.prt" + (_format text) + (_timespec "2024-01-11T18:45:09") + ) + (_file "place_route/clock_utilization.txt" + (_format text) + (_timespec "2024-01-11T18:45:09") + ) + (_file "place_route/Top_plc.adf" + (_format adif) + (_timespec "2024-01-11T18:44:12") + ) + (_file "place_route/Top_pnr.netlist" + (_format text) + (_timespec "2024-01-11T18:45:10") + ) + (_file "place_route/prr.db" + (_format text) + (_timespec "2024-01-11T18:45:11") + ) + ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -282,8 +338,24 @@ (_attribute _click_to_run (_switch ON)) ) (_command cmd_report_post_pnr_timing - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) (_attribute _auto_exe_lock (_switch OFF)) + (_db_output + (_file "report_timing/Top_rtp.adf" + (_format adif) + (_timespec "2024-01-11T18:45:17") + ) + ) + (_output + (_file "report_timing/Top.rtr" + (_format text) + (_timespec "2024-01-11T18:45:17") + ) + (_file "report_timing/rtr.db" + (_format text) + (_timespec "2024-01-11T18:45:17") + ) + ) ) (_widget wgt_arch_browser (_attribute _click_to_run (_switch ON)) @@ -301,7 +373,25 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_output + (_file "generate_bitstream/Top.sbit" + (_format text) + (_timespec "2024-01-11T18:45:45") + ) + (_file "generate_bitstream/Top.smsk" + (_format text) + (_timespec "2024-01-11T18:45:45") + ) + (_file "generate_bitstream/Top.bgr" + (_format text) + (_timespec "2024-01-11T18:45:45") + ) + (_file "generate_bitstream/bgr.db" + (_format text) + (_timespec "2024-01-11T18:45:46") + ) + ) ) ) ) diff --git a/source/src/timecode_output.v b/source/src/timecode_output.v new file mode 100644 index 0000000..d74d9ee --- /dev/null +++ b/source/src/timecode_output.v @@ -0,0 +1,164 @@ +module timecode_output #( + parameter REG_START_ADD = 0, + parameter SYS_CLOCK_FREQ = 10000000 +) ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + + //寄存器读写接口 + input [31:0] addr, + input [31:0] wr_data, + input wr_en, + output wire [31:0] rd_data, + + /******************************************************************************* + * TIMECODE输出 * + *******************************************************************************/ + + input [31:0] ext_timecode_format, + input [63:0] ext_timecode_data, + input ext_timecode_tigger_sig, + input ext_timecode_serial_data, + + input [63:0] internal_timecode_data, + input internal_timecode_tigger_sig, + input [31:0] internal_timecode_format, + input internal_timecode_serial_data, + + /******************************************************************************* + * 输出接口 * + *******************************************************************************/ + output stm32if_timecode_tigger_sig, + + output reg timecode_out_bnc, + output reg timecode_out_bnc_select, // 电平选择 0line,1:mic + output reg timecode_out_bnc_state_led, + + output reg timecode_out_headphone, + output reg timecode_out_headphone_select, // 电平选择 0line,1:mic + output reg timecode_out_headphone_state_led + +); + // 1ms + reg [31:0] r0_timecode_select; //时码输入选择器 + reg [31:0] r1_timecode0; //时码原始码0 //注意这个数据要比ext_timecode_serial_data晚一帧 + reg [31:0] r2_timecode1; //时码原始码1 //注意这个数据要比ext_timecode_serial_data晚一帧 + reg [31:0] r3_timecode_format; // + reg [31:0] r4_bnc_outut_level_select; // 0:line, 1:mic + reg [31:0] r5_headphone_outut_level_select; // 0:line, 1:mic + + wire [31:0] reg_wr_index; + + zutils_register_advanced #( + .REG_START_ADD(REG_START_ADD) + ) _register ( + .clk(clk), + .rst_n(rst_n), + .addr(addr), + .wr_data(wr_data), + .wr_en(wr_en), + .rd_data(rd_data), + + .reg0(r0_timecode_select), + .reg1(r1_timecode0), + .reg2(r2_timecode1), + .reg3(r3_timecode_format), + .reg4(r4_bnc_outut_level_select), + .reg5(r5_headphone_outut_level_select), + + + .reg_wr_sig(reg_wr_sig), + .reg_index (reg_wr_index) + ); + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + r0_timecode_select <= 0; + r4_bnc_outut_level_select <= 0; + r5_headphone_outut_level_select <= 0; + end else begin + if (reg_wr_sig) begin + case (reg_wr_index) + 31'h0: r0_timecode_select <= wr_data; + 31'h4: r4_bnc_outut_level_select <= wr_data; + 31'h5: r5_headphone_outut_level_select <= wr_data; + default: begin + end + endcase + end + end + end + + + reg out_timecode_serial_data; + reg timecode_tigger_sig; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + r1_timecode0 <= 0; + r2_timecode1 <= 0; + r3_timecode_format <= 0; + out_timecode_serial_data <= 0; + timecode_tigger_sig <= 0; + end else begin + case (r0_timecode_select) + 0: begin + r1_timecode0 <= 0; + r2_timecode1 <= 0; + r3_timecode_format <= 0; + out_timecode_serial_data <= 0; + timecode_tigger_sig <= 0; + end + // 内部时码 + 1: begin + r1_timecode0 <= internal_timecode_data[31:0]; + r2_timecode1 <= internal_timecode_data[63:32]; + r3_timecode_format <= internal_timecode_format; + out_timecode_serial_data <= internal_timecode_serial_data; + timecode_tigger_sig <= internal_timecode_tigger_sig; + end + // 外部时码 + 2: begin + r1_timecode0 <= ext_timecode_data[31:0]; + r2_timecode1 <= ext_timecode_data[63:32]; + r3_timecode_format <= ext_timecode_format; + out_timecode_serial_data <= ext_timecode_serial_data; + timecode_tigger_sig <= ext_timecode_tigger_sig; + end + + default: begin + r1_timecode0 <= 0; + r2_timecode1 <= 0; + r3_timecode_format <= 0; + out_timecode_serial_data <= 0; + timecode_tigger_sig <= 0; + end + endcase + end + end + + + zutils_pluse_generator _pluse_generator ( + .clk(clk), + .rst_n(rst_n), + .pluse_width(1000), //1ms + .pluse_delay(32'd0), + .trigger(timecode_tigger_sig), + .output_signal(stm32if_timecode_tigger_sig) + ); + + + always @(*) begin + timecode_out_bnc <= out_timecode_serial_data; + timecode_out_bnc_select <= r4_bnc_outut_level_select[0]; + timecode_out_bnc_state_led <= 1; + + timecode_out_headphone <= out_timecode_serial_data; + timecode_out_headphone_select <= r5_headphone_outut_level_select[0]; + timecode_out_headphone_state_led <= 1; + end + + + + + +endmodule diff --git a/source/src/top.v b/source/src/top.v index 8545c8a..80242ce 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -75,11 +75,10 @@ module Top ( /******************************************************************************* * STM32_IF * *******************************************************************************/ + + output stm32if_start_signal_out, output stm32if_camera_sync_out, output stm32if_timecode_sync_out, - output stm32if_start_signal_out, - output [3:0] stm32if_timecode_add, - output [3:0] stm32if_timecode_data, //SPI 串行总线1 input wire spi1_cs_pin, @@ -109,7 +108,7 @@ module Top ( localparam REG_ADD_OFF_STM32 = 16'h0000; localparam REG_ADD_OFF_FPGA_TEST = 16'h00020; //控制中心寄存器地址 - localparam REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR = 16'h00030; // 48 + localparam REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR = 16'h00030; // 48 //输入组件 localparam REG_ADD_OFF_TTLIN1 = 16'h0100; localparam REG_ADD_OFF_TTLIN2 = 16'h0110; @@ -252,7 +251,10 @@ module Top ( wire ISIG_internal_100hz; // 100hz测试信号 wire [63:0] ISIGBUS64_timecode_data_ext; + wire [31:0] ISIGBUS32_timecode_format_ext; + wire [63:0] ISIGBUS64_timecode_data_internal; + wire [31:0] ISIGBUS32_timecode_format_internal; assign ISIG_genlock_frame_sync_ext = genlock_in_vsync; assign ISIG_logic0 = 0; @@ -273,14 +275,15 @@ module Top ( assign ttl_output_module_source_sig_af[7] = ISIG_ttlin3_module_divide; assign ttl_output_module_source_sig_af[8] = ISIG_ttlin4_module_ext; assign ttl_output_module_source_sig_af[9] = ISIG_ttlin4_module_divide; - assign ttl_output_module_source_sig_af[10] = ISIG_internal_en_flag ; - assign ttl_output_module_source_sig_af[11] = ISIG_genlock_frame_sync_ext ; - assign ttl_output_module_source_sig_af[12] = ISIG_genlock_frame_sync_internal ; - assign ttl_output_module_source_sig_af[13] = ISIG_timecode_frame_sync_ext ; - assign ttl_output_module_source_sig_af[14] = ISIG_timecode_frame_sync_internal ; - assign ttl_output_module_source_sig_af[15] = ISIG_timecode_serial_data_ext ; - assign ttl_output_module_source_sig_af[16] = ISIG_timecode_serial_data_internal ; - assign ttl_output_module_source_sig_af[31] = ISIG_internal_100hz ; + assign ttl_output_module_source_sig_af[10] = ISIG_internal_en_flag; + assign ttl_output_module_source_sig_af[11] = ISIG_genlock_frame_sync_ext; + assign ttl_output_module_source_sig_af[12] = ISIG_genlock_frame_sync_internal; + assign ttl_output_module_source_sig_af[13] = ISIG_timecode_frame_sync_ext; + assign ttl_output_module_source_sig_af[14] = ISIG_timecode_frame_sync_internal; + assign ttl_output_module_source_sig_af[15] = ISIG_timecode_serial_data_ext; + assign ttl_output_module_source_sig_af[16] = ISIG_timecode_serial_data_internal; + + assign ttl_output_module_source_sig_af[31] = ISIG_internal_100hz; @@ -307,7 +310,7 @@ module Top ( .out_timecode_sig(ISIGBUS64_timecode_data_internal), //[63:0] 输出时间 .out_timecode_serial_sig(ISIG_timecode_serial_data_internal), //TIMECODE串行数据输出 .out_genlock_sig(ISIG_genlock_frame_sync_internal), - .out_en_flag(ISIG_en_flag_internal) + .out_en_flag(ISIG_internal_en_flag) ); /******************************************************************************* @@ -323,10 +326,57 @@ module Top ( ); + // =========================================================================================================== + // 输出组件 + // =========================================================================================================== + + /******************************************************************************* - * 输出组件 * + * STM32_IF * + *******************************************************************************/ + assign stm32if_start_signal_out = ISIG_internal_en_flag; + + /******************************************************************************* + * timecode_output * *******************************************************************************/ + timecode_output #( + .REG_START_ADD (REG_ADD_OFF_TIMECODE_OUT), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) timecode_output_inst ( + + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr(reg_reader_bus_addr), + .wr_data(reg_reader_bus_wr_data), + .wr_en(reg_reader_bus_wr_en), + .rd_data(timecode_out_rd_data), + + .ext_timecode_data(ISIGBUS64_timecode_data_ext), //63:0 + .ext_timecode_format(ISIGBUS32_timecode_format_ext), //31:0 + .ext_timecode_tigger_sig(ISIG_timecode_frame_sync_ext), + .ext_timecode_serial_data(ISIG_timecode_serial_data_ext), + + .internal_timecode_data(ISIGBUS64_timecode_data_internal), //63:0 + .internal_timecode_format(ISIGBUS32_timecode_format_internal), //31:0 + .internal_timecode_tigger_sig(ISIG_timecode_frame_sync_internal), + .internal_timecode_serial_data(ISIG_timecode_serial_data_internal), + + .stm32if_timecode_tigger_sig(stm32if_timecode_sync_out), + + .timecode_out_bnc(timecode_out_bnc), + .timecode_out_bnc_select(timecode_out_bnc_select), + .timecode_out_bnc_state_led(timecode_out_bnc_state_led), + + .timecode_out_headphone(timecode_out_headphone), + .timecode_out_headphone_select(timecode_out_headphone_select), + .timecode_out_headphone_state_led(timecode_out_headphone_state_led) + ); + + /******************************************************************************* + * TTL_OUTPUT * + *******************************************************************************/ ttl_output #( .REG_START_ADD(REG_ADD_OFF_TTLOUT1), .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), @@ -449,6 +499,16 @@ module Top ( ); // assign reg_reader_bus_rd_data[31:0] = fpga_test_rd_data[31:0]; + // output reg stm32if_timecode_tigger_sig, + + // output reg timecode_out_bnc, + // output reg timecode_out_bnc_select, // 电平选择 0line,1:mic + // output reg timecode_out_bnc_state_led, + + // output reg timecode_out_headphone, + // output reg timecode_out_headphone_select, // 电平选择 0line,1:mic + // output reg timecode_out_headphone_state_led + assign debug_signal_output[0] = spi2_cs_pin; assign debug_signal_output[1] = spi2_clk_pin; assign debug_signal_output[2] = spi2_rx_pin; @@ -457,7 +517,16 @@ module Top ( assign debug_signal_output[5] = sync_ttl_out2; assign debug_signal_output[6] = sync_ttl_out3; assign debug_signal_output[7] = sync_ttl_out4; - assign core_board_debug_led = 1; + assign debug_signal_output[8] = stm32if_timecode_sync_out; + assign debug_signal_output[9] = timecode_out_bnc; + assign debug_signal_output[10] = timecode_out_headphone; + assign debug_signal_output[11] = timecode_out_bnc_select; + assign debug_signal_output[12] = timecode_out_headphone_select; + assign debug_signal_output[13] = 0; + assign debug_signal_output[14] = 0; + assign debug_signal_output[15] = 0; + + assign core_board_debug_led = 1; endmodule diff --git a/source/src/zutils/zutils_pluse_generator.v b/source/src/zutils/zutils_pluse_generator.v index dcc71d7..b30c8a9 100644 --- a/source/src/zutils/zutils_pluse_generator.v +++ b/source/src/zutils/zutils_pluse_generator.v @@ -18,10 +18,14 @@ module zutils_pluse_generator #( if (!rst_n) begin inter_clk_count <= 0; end else begin - if (inter_clk_count < INTER_CLK_COUNT_MAX) begin - inter_clk_count <= inter_clk_count + 1; - end else begin + if (trigger) begin inter_clk_count <= 0; + end else begin + if (inter_clk_count < INTER_CLK_COUNT_MAX) begin + inter_clk_count <= inter_clk_count + 1; + end else begin + inter_clk_count <= 0; + end end end end