forked from p_lusterinc_xsync/xsync_fpge
5 changed files with 411 additions and 84 deletions
-
96led_test.fdc
-
126led_test.pds
-
164source/src/timecode_output.v
-
99source/src/top.v
-
10source/src/zutils/zutils_pluse_generator.v
@ -0,0 +1,164 @@ |
|||||
|
module timecode_output #( |
||||
|
parameter REG_START_ADD = 0, |
||||
|
parameter SYS_CLOCK_FREQ = 10000000 |
||||
|
) ( |
||||
|
input clk, //clock input |
||||
|
input rst_n, //asynchronous reset input, low active |
||||
|
|
||||
|
//寄存器读写接口 |
||||
|
input [31:0] addr, |
||||
|
input [31:0] wr_data, |
||||
|
input wr_en, |
||||
|
output wire [31:0] rd_data, |
||||
|
|
||||
|
/******************************************************************************* |
||||
|
* TIMECODE输出 * |
||||
|
*******************************************************************************/ |
||||
|
|
||||
|
input [31:0] ext_timecode_format, |
||||
|
input [63:0] ext_timecode_data, |
||||
|
input ext_timecode_tigger_sig, |
||||
|
input ext_timecode_serial_data, |
||||
|
|
||||
|
input [63:0] internal_timecode_data, |
||||
|
input internal_timecode_tigger_sig, |
||||
|
input [31:0] internal_timecode_format, |
||||
|
input internal_timecode_serial_data, |
||||
|
|
||||
|
/******************************************************************************* |
||||
|
* 输出接口 * |
||||
|
*******************************************************************************/ |
||||
|
output stm32if_timecode_tigger_sig, |
||||
|
|
||||
|
output reg timecode_out_bnc, |
||||
|
output reg timecode_out_bnc_select, // 电平选择 0line,1:mic |
||||
|
output reg timecode_out_bnc_state_led, |
||||
|
|
||||
|
output reg timecode_out_headphone, |
||||
|
output reg timecode_out_headphone_select, // 电平选择 0line,1:mic |
||||
|
output reg timecode_out_headphone_state_led |
||||
|
|
||||
|
); |
||||
|
// 1ms |
||||
|
reg [31:0] r0_timecode_select; //时码输入选择器 |
||||
|
reg [31:0] r1_timecode0; //时码原始码0 //注意这个数据要比ext_timecode_serial_data晚一帧 |
||||
|
reg [31:0] r2_timecode1; //时码原始码1 //注意这个数据要比ext_timecode_serial_data晚一帧 |
||||
|
reg [31:0] r3_timecode_format; // |
||||
|
reg [31:0] r4_bnc_outut_level_select; // 0:line, 1:mic |
||||
|
reg [31:0] r5_headphone_outut_level_select; // 0:line, 1:mic |
||||
|
|
||||
|
wire [31:0] reg_wr_index; |
||||
|
|
||||
|
zutils_register_advanced #( |
||||
|
.REG_START_ADD(REG_START_ADD) |
||||
|
) _register ( |
||||
|
.clk(clk), |
||||
|
.rst_n(rst_n), |
||||
|
.addr(addr), |
||||
|
.wr_data(wr_data), |
||||
|
.wr_en(wr_en), |
||||
|
.rd_data(rd_data), |
||||
|
|
||||
|
.reg0(r0_timecode_select), |
||||
|
.reg1(r1_timecode0), |
||||
|
.reg2(r2_timecode1), |
||||
|
.reg3(r3_timecode_format), |
||||
|
.reg4(r4_bnc_outut_level_select), |
||||
|
.reg5(r5_headphone_outut_level_select), |
||||
|
|
||||
|
|
||||
|
.reg_wr_sig(reg_wr_sig), |
||||
|
.reg_index (reg_wr_index) |
||||
|
); |
||||
|
|
||||
|
always @(posedge clk or negedge rst_n) begin |
||||
|
if (!rst_n) begin |
||||
|
r0_timecode_select <= 0; |
||||
|
r4_bnc_outut_level_select <= 0; |
||||
|
r5_headphone_outut_level_select <= 0; |
||||
|
end else begin |
||||
|
if (reg_wr_sig) begin |
||||
|
case (reg_wr_index) |
||||
|
31'h0: r0_timecode_select <= wr_data; |
||||
|
31'h4: r4_bnc_outut_level_select <= wr_data; |
||||
|
31'h5: r5_headphone_outut_level_select <= wr_data; |
||||
|
default: begin |
||||
|
end |
||||
|
endcase |
||||
|
end |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
|
||||
|
reg out_timecode_serial_data; |
||||
|
reg timecode_tigger_sig; |
||||
|
always @(posedge clk or negedge rst_n) begin |
||||
|
if (!rst_n) begin |
||||
|
r1_timecode0 <= 0; |
||||
|
r2_timecode1 <= 0; |
||||
|
r3_timecode_format <= 0; |
||||
|
out_timecode_serial_data <= 0; |
||||
|
timecode_tigger_sig <= 0; |
||||
|
end else begin |
||||
|
case (r0_timecode_select) |
||||
|
0: begin |
||||
|
r1_timecode0 <= 0; |
||||
|
r2_timecode1 <= 0; |
||||
|
r3_timecode_format <= 0; |
||||
|
out_timecode_serial_data <= 0; |
||||
|
timecode_tigger_sig <= 0; |
||||
|
end |
||||
|
// 内部时码 |
||||
|
1: begin |
||||
|
r1_timecode0 <= internal_timecode_data[31:0]; |
||||
|
r2_timecode1 <= internal_timecode_data[63:32]; |
||||
|
r3_timecode_format <= internal_timecode_format; |
||||
|
out_timecode_serial_data <= internal_timecode_serial_data; |
||||
|
timecode_tigger_sig <= internal_timecode_tigger_sig; |
||||
|
end |
||||
|
// 外部时码 |
||||
|
2: begin |
||||
|
r1_timecode0 <= ext_timecode_data[31:0]; |
||||
|
r2_timecode1 <= ext_timecode_data[63:32]; |
||||
|
r3_timecode_format <= ext_timecode_format; |
||||
|
out_timecode_serial_data <= ext_timecode_serial_data; |
||||
|
timecode_tigger_sig <= ext_timecode_tigger_sig; |
||||
|
end |
||||
|
|
||||
|
default: begin |
||||
|
r1_timecode0 <= 0; |
||||
|
r2_timecode1 <= 0; |
||||
|
r3_timecode_format <= 0; |
||||
|
out_timecode_serial_data <= 0; |
||||
|
timecode_tigger_sig <= 0; |
||||
|
end |
||||
|
endcase |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
|
||||
|
zutils_pluse_generator _pluse_generator ( |
||||
|
.clk(clk), |
||||
|
.rst_n(rst_n), |
||||
|
.pluse_width(1000), //1ms |
||||
|
.pluse_delay(32'd0), |
||||
|
.trigger(timecode_tigger_sig), |
||||
|
.output_signal(stm32if_timecode_tigger_sig) |
||||
|
); |
||||
|
|
||||
|
|
||||
|
always @(*) begin |
||||
|
timecode_out_bnc <= out_timecode_serial_data; |
||||
|
timecode_out_bnc_select <= r4_bnc_outut_level_select[0]; |
||||
|
timecode_out_bnc_state_led <= 1; |
||||
|
|
||||
|
timecode_out_headphone <= out_timecode_serial_data; |
||||
|
timecode_out_headphone_select <= r5_headphone_outut_level_select[0]; |
||||
|
timecode_out_headphone_state_led <= 1; |
||||
|
end |
||||
|
|
||||
|
|
||||
|
|
||||
|
|
||||
|
|
||||
|
endmodule |
||||
Write
Preview
Loading…
Cancel
Save
Reference in new issue