From 5e08a6875f4ff76b41f118ec1c8e5813d83168a8 Mon Sep 17 00:00:00 2001 From: zhaohe Date: Mon, 26 Aug 2024 09:37:51 +0800 Subject: [PATCH] update --- constraint_check/constraint_check.ccr | 4 +- multiseed_summary.csv | 12 +- source/src/top.v | 153 ++++++++++++------------- xsync.fdc | 208 +++++++++++++++++++++------------- xsync.pds | 54 ++++----- xsync.pds.lock | 5 - 6 files changed, 238 insertions(+), 198 deletions(-) delete mode 100644 xsync.pds.lock diff --git a/constraint_check/constraint_check.ccr b/constraint_check/constraint_check.ccr index 7acdbcf..dc19425 100644 --- a/constraint_check/constraint_check.ccr +++ b/constraint_check/constraint_check.ccr @@ -1,4 +1,4 @@ -##### Written on 2024/08/25 23:04:22 ############################### +##### Written on 2024/08/26 00:05:03 ############################### ##### INFO ################################################## @@ -14,7 +14,7 @@ Constraint File(s) : ##### SUMMARY ###################################################### -Found 0 error(s), 9 critical warning(s), 15 warning(s), out of 292 constraint(s) +Found 0 error(s), 9 critical warning(s), 15 warning(s), out of 340 constraint(s) Inapplicable constraints(except overwritten constraints): diff --git a/multiseed_summary.csv b/multiseed_summary.csv index 2bd9ba6..acb1d22 100644 --- a/multiseed_summary.csv +++ b/multiseed_summary.csv @@ -3,23 +3,23 @@ project name,xsync.pds Single Seed: Seed,State,Convergence,Setup(Slow),Setup(Fast),Hold(Slow),Hold(Fast),Recovery(Slow),Recovery(Fast),Removal(Slow),Removal(Fast),PBM-GP,PBM-PreGP,PBM-PostGP,LP,Total Placement Cpu Time,Detailed routing,Total Routing Cpu Time,Wire Length After Post-GP,Wire Length After LP,Wire Length After DP,Routing Arc Length,Worst Slack After GP Timing,Worst Slack After LP Timing,Worst Slack Before RP,Worst Slack Before DP,Worst Slack After DP,Worst Slack After Placement,Worst Slack After TA By Preroute,TNS After DP,TNS Before Route,Setup(Slow) Total Failing TNS,Setup(Slow) Total Failing Endpoints,Hold(Slow) Total Failing THS,Hold(Slow) Total Failing Endpoints,Power -single,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,0.02,1.62,0.02,2.08,NA,NA,NA,665,NA,NA,997980,997980,997980,997980,NA,0,0,NA,NA,NA,NA,NA +single,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,0.12,7.09,1.67,9.17,NA,NA,NA,10137,NA,NA,995931,995931,995931,995931,NA,0,0,NA,NA,NA,NA,NA Pass Rate/Convergence Rate,0.00%,0.00% Synthesize: -control_set,3 +control_set,35 Synthesize Performance Summary: slack category,Synthesize Setup WNS,Synthesize Setup TNS,Synthesize Recovery WNS,Synthesize Recovery TNS -slack value,997.343,0.000,NA,NA -Synthesize Process Cpu Time,0h:0m:2s +slack value,995.809,0.000,NA,NA +Synthesize Process Cpu Time,0h:0m:10s Device Map: Device Map Resource Usage Summary: Logic Utilization,LUT,FF,DRM,APM,Distributed RAM,HSSTHP,USCM,HCKB,RCKB -Used,45,29,0,0,0,NA,1,0,0 +Used,516,715,0,0,0,NA,1,0,0 Available,66600,133200,155,240,19900,NA,32,96,24 Utilization(%),1%,1%,0%,0%,0%,NA,4%,0%,0% -Device Map Process Cpu Time,0h:0m:3s +Device Map Process Cpu Time,0h:0m:10s Project Configurations: top module,Top diff --git a/source/src/top.v b/source/src/top.v index 76e0462..74eb2c4 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -68,77 +68,6 @@ module Top ( output reg core_board_debug_led ); -//parameter define -parameter CNT_2US_MAX = 7'd100; -parameter CNT_2MS_MAX = 10'd1000; -parameter CNT_2S_MAX = 10'd1000; - -//reg define -reg [6:0] cnt_2us; -reg [9:0] cnt_2ms; -reg [9:0] cnt_2s; -reg inc_dec_flag; //亮度递增/递减 0:递增 1:递减 - -//***************************************************** -//** main code -//***************************************************** - -//cnt_2us:计数2us -always@(posedge ex_clk or negedge ex_rst_n) begin - if(!ex_rst_n) - cnt_2us <= 7'b0; - else if(cnt_2us == (CNT_2US_MAX - 7'b1 )) - cnt_2us <= 7'b0; - else - cnt_2us <= cnt_2us + 7'b1; -end - -//cnt_2ms:计数2ms -always@(posedge ex_clk or negedge ex_rst_n) begin - if(!ex_rst_n) - cnt_2ms <= 10'b0; - else if(cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) - cnt_2ms <= 10'b0; - else if(cnt_2us == CNT_2US_MAX - 7'b1) - cnt_2ms <= cnt_2ms + 10'b1; - else - cnt_2ms <= cnt_2ms; -end - -//cnt_2s:计数2s -always@(posedge ex_clk or negedge ex_rst_n) begin - if(!ex_rst_n) - cnt_2s <= 10'b0; - else if(cnt_2s == (CNT_2S_MAX - 10'b1) && cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) - cnt_2s <= 10'b0; - else if(cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) - cnt_2s <= cnt_2s + 10'b1; - else - cnt_2s <= cnt_2s; -end - -//inc_dec_flag为低电平，led灯由暗变亮，inc_dec_flag为高电平，led灯由亮变暗 -always@(posedge ex_clk or negedge ex_rst_n) begin - if(!ex_rst_n) - inc_dec_flag <= 1'b0; - else if(cnt_2s == (CNT_2S_MAX - 10'b1) && cnt_2ms ==( CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) - inc_dec_flag <= ~inc_dec_flag; - else - inc_dec_flag <= inc_dec_flag; -end - -//led:输出信号连接到外部的led灯 -always@(posedge ex_clk or negedge ex_rst_n) begin - if(!ex_rst_n) - core_board_debug_led <= 1'b0; - else if((inc_dec_flag == 1'b1 && cnt_2ms >= cnt_2s) || (inc_dec_flag == 1'b0 && cnt_2ms <= cnt_2s)) - core_board_debug_led <= 1'b1; - else - core_board_debug_led <= 1'b0; -end - - /* - localparam SYS_CLOCK_FREQ = 10000000; wire sys_clk; //! 系统时钟 wire sys_rst_n; //! 系统复位 @@ -240,11 +169,11 @@ end //系统时钟源 SPLL spll ( - .clkin1 (ex_clk), - .lock(pll_lock), - .clkout0 (sys_clk_25m), - .clkout1 (sys_clk_10m), - .clkout2 (sys_clk_5m) + .clkin1 (ex_clk), + .lock (pll_lock), + .clkout0(sys_clk_25m), + .clkout1(sys_clk_10m), + .clkout2(sys_clk_5m) ); assign sys_clk = sys_clk_10m; assign sys_rst_n = ex_rst_n & pll_lock; @@ -312,6 +241,73 @@ end .rd_data(rd_data_module_fpga_info) ); + + /*********************************************************************************************************************** + * 呼吸灯输出 * + ***********************************************************************************************************************/ + //parameter define + parameter CNT_2US_MAX = 7'd100; + parameter CNT_2MS_MAX = 10'd1000; + parameter CNT_2S_MAX = 10'd1000; + + //reg define + reg [6:0] cnt_2us; + reg [9:0] cnt_2ms; + reg [9:0] cnt_2s; + reg inc_dec_flag; //亮度递增/递减 0:递增 1:递减 + + //***************************************************** + //** main code + //***************************************************** + + //cnt_2us:计数2us + always @(posedge ex_clk or negedge ex_rst_n) begin + if (!ex_rst_n) cnt_2us <= 7'b0; + else if (cnt_2us == (CNT_2US_MAX - 7'b1)) cnt_2us <= 7'b0; + else cnt_2us <= cnt_2us + 7'b1; + end + + //cnt_2ms:计数2ms + always @(posedge ex_clk or negedge ex_rst_n) begin + if (!ex_rst_n) cnt_2ms <= 10'b0; + else if (cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) cnt_2ms <= 10'b0; + else if (cnt_2us == CNT_2US_MAX - 7'b1) cnt_2ms <= cnt_2ms + 10'b1; + else cnt_2ms <= cnt_2ms; + end + + //cnt_2s:计数2s + always @(posedge ex_clk or negedge ex_rst_n) begin + if (!ex_rst_n) cnt_2s <= 10'b0; + else if (cnt_2s == (CNT_2S_MAX - 10'b1) && cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) cnt_2s <= 10'b0; + else if (cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) cnt_2s <= cnt_2s + 10'b1; + else cnt_2s <= cnt_2s; + end + + //inc_dec_flag为低电平，led灯由暗变亮，inc_dec_flag为高电平，led灯由亮变暗 + always @(posedge ex_clk or negedge ex_rst_n) begin + if (!ex_rst_n) inc_dec_flag <= 1'b0; + else if (cnt_2s == (CNT_2S_MAX - 10'b1) && cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) inc_dec_flag <= ~inc_dec_flag; + else inc_dec_flag <= inc_dec_flag; + end + + //led:输出信号连接到外部的led灯 + always @(posedge ex_clk or negedge ex_rst_n) begin + if (!ex_rst_n) core_board_debug_led <= 1'b0; + else if ((inc_dec_flag == 1'b1 && cnt_2ms >= cnt_2s) || (inc_dec_flag == 1'b0 && cnt_2ms <= cnt_2s)) core_board_debug_led <= 1'b1; + else core_board_debug_led <= 1'b0; + end + + /*********************************************************************************************************************** + * 呼吸灯输出结束 * + ***********************************************************************************************************************/ + + assign debug_signal_output[0] = sys_clk; + assign debug_signal_output[1] = spi1_cs_pin; + assign debug_signal_output[2] = spi1_clk_pin; + assign debug_signal_output[3] = spi1_cs_pin; + assign debug_signal_output[4] = spi1_tx_pin; + + /* wire [15:0] sys_sig_delay_in; wire [15:0] sys_sig_delay_out; @@ -768,9 +764,10 @@ end .out_record_en_sig (signal_business_record_en_sig), .out_record_exposure_sig(signal_business_record_exposure_sig) ); +*/ - + /* assign debug_signal_output[0] = sys_clk; assign debug_signal_output[1] = af_delay__sync_ttl_in3; assign debug_signal_output[2] = af_delay__sync_ttl_in2; @@ -786,6 +783,6 @@ end assign debug_signal_output[12] = sync_ttl_in2; assign debug_signal_output[13] = sync_ttl_in3; assign debug_signal_output[15] = !sync_ttl_in4; - */ + endmodule diff --git a/xsync.fdc b/xsync.fdc index 4b353ba..7c91ed8 100644 --- a/xsync.fdc +++ b/xsync.fdc @@ -10,147 +10,147 @@ define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVCMOS15} define_attribute {p:ex_rst_n} {PAP_IO_NONE} {TRUE} define_attribute {p:genlock_in_hsync} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:genlock_in_hsync} {PAP_IO_LOC} {M15} -define_attribute {p:genlock_in_hsync} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_in_hsync} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_in_hsync} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_in_hsync} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_in_vsync} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:genlock_in_vsync} {PAP_IO_LOC} {M16} -define_attribute {p:genlock_in_vsync} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_in_vsync} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_in_vsync} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_in_vsync} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_in_fsync} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:genlock_in_fsync} {PAP_IO_LOC} {L16} -define_attribute {p:genlock_in_fsync} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_in_fsync} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_in_fsync} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_in_fsync} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[0]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:genlock_out_dac[0]} {PAP_IO_LOC} {E14} -define_attribute {p:genlock_out_dac[0]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_out_dac[0]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_out_dac[0]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[0]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[0]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[0]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[1]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:genlock_out_dac[1]} {PAP_IO_LOC} {E13} -define_attribute {p:genlock_out_dac[1]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_out_dac[1]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_out_dac[1]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[1]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[1]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[1]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[2]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:genlock_out_dac[2]} {PAP_IO_LOC} {F14} -define_attribute {p:genlock_out_dac[2]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_out_dac[2]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_out_dac[2]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[2]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[2]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[2]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[3]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:genlock_out_dac[3]} {PAP_IO_LOC} {F13} -define_attribute {p:genlock_out_dac[3]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_out_dac[3]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_out_dac[3]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[3]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[3]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[3]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[4]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:genlock_out_dac[4]} {PAP_IO_LOC} {C22} -define_attribute {p:genlock_out_dac[4]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_out_dac[4]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_out_dac[4]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[4]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[4]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[4]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[5]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:genlock_out_dac[5]} {PAP_IO_LOC} {B22} -define_attribute {p:genlock_out_dac[5]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_out_dac[5]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_out_dac[5]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[5]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[5]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[5]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[6]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:genlock_out_dac[6]} {PAP_IO_LOC} {C20} -define_attribute {p:genlock_out_dac[6]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_out_dac[6]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_out_dac[6]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[6]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[6]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[6]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[7]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:genlock_out_dac[7]} {PAP_IO_LOC} {D20} -define_attribute {p:genlock_out_dac[7]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_out_dac[7]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_out_dac[7]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[7]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[7]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[7]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[8]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:genlock_out_dac[8]} {PAP_IO_LOC} {C19} -define_attribute {p:genlock_out_dac[8]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_out_dac[8]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_out_dac[8]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac[8]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[8]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[8]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac_clk} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:genlock_out_dac_clk} {PAP_IO_LOC} {C18} -define_attribute {p:genlock_out_dac_clk} {PAP_IO_VCCIO} {1.5} -define_attribute {p:genlock_out_dac_clk} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:genlock_out_dac_clk} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_out_dac_clk} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac_clk} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac_clk} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_in1} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:sync_ttl_in1} {PAP_IO_LOC} {K18} -define_attribute {p:sync_ttl_in1} {PAP_IO_VCCIO} {1.5} -define_attribute {p:sync_ttl_in1} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:sync_ttl_in1} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_in1} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:sync_ttl_in2} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:sync_ttl_in2} {PAP_IO_LOC} {K19} -define_attribute {p:sync_ttl_in2} {PAP_IO_VCCIO} {1.5} -define_attribute {p:sync_ttl_in2} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:sync_ttl_in2} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_in2} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:sync_ttl_in3} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:sync_ttl_in3} {PAP_IO_LOC} {M13} -define_attribute {p:sync_ttl_in3} {PAP_IO_VCCIO} {1.5} -define_attribute {p:sync_ttl_in3} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:sync_ttl_in3} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_in3} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:sync_ttl_in4} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {L13} -define_attribute {p:sync_ttl_in4} {PAP_IO_VCCIO} {1.5} -define_attribute {p:sync_ttl_in4} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:sync_ttl_in4} {PAP_IO_VCCIO} {3.3} +define_attribute {p:sync_ttl_in4} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:sync_ttl_out1} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {AA8} define_attribute {p:sync_ttl_out1} {PAP_IO_VCCIO} {1.5} define_attribute {p:sync_ttl_out1} {PAP_IO_STANDARD} {LVCMOS15} -define_attribute {p:sync_ttl_out1} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_out1} {PAP_IO_DRIVE} {8} define_attribute {p:sync_ttl_out1} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_out2} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:sync_ttl_out2} {PAP_IO_LOC} {V9} define_attribute {p:sync_ttl_out2} {PAP_IO_VCCIO} {1.5} define_attribute {p:sync_ttl_out2} {PAP_IO_STANDARD} {LVCMOS15} -define_attribute {p:sync_ttl_out2} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_out2} {PAP_IO_DRIVE} {8} define_attribute {p:sync_ttl_out2} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_out3} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:sync_ttl_out3} {PAP_IO_LOC} {V8} define_attribute {p:sync_ttl_out3} {PAP_IO_VCCIO} {1.5} define_attribute {p:sync_ttl_out3} {PAP_IO_STANDARD} {LVCMOS15} -define_attribute {p:sync_ttl_out3} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_out3} {PAP_IO_DRIVE} {8} define_attribute {p:sync_ttl_out3} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_out4} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {T6} define_attribute {p:sync_ttl_out4} {PAP_IO_VCCIO} {1.5} define_attribute {p:sync_ttl_out4} {PAP_IO_STANDARD} {LVCMOS15} -define_attribute {p:sync_ttl_out4} {PAP_IO_DRIVE} {4} +define_attribute {p:sync_ttl_out4} {PAP_IO_DRIVE} {8} define_attribute {p:sync_ttl_out4} {PAP_IO_SLEW} {SLOW} define_attribute {p:timecode_headphone_in} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {L15} -define_attribute {p:timecode_headphone_in} {PAP_IO_VCCIO} {1.5} -define_attribute {p:timecode_headphone_in} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:timecode_headphone_in} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_headphone_in} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:timecode_bnc_in} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:timecode_bnc_in} {PAP_IO_LOC} {L14} -define_attribute {p:timecode_bnc_in} {PAP_IO_VCCIO} {1.5} -define_attribute {p:timecode_bnc_in} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:timecode_bnc_in} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_bnc_in} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:timecode_out_bnc} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:timecode_out_bnc} {PAP_IO_LOC} {W9} define_attribute {p:timecode_out_bnc} {PAP_IO_VCCIO} {1.5} define_attribute {p:timecode_out_bnc} {PAP_IO_STANDARD} {LVCMOS15} -define_attribute {p:timecode_out_bnc} {PAP_IO_DRIVE} {4} +define_attribute {p:timecode_out_bnc} {PAP_IO_DRIVE} {8} define_attribute {p:timecode_out_bnc} {PAP_IO_SLEW} {SLOW} define_attribute {p:timecode_out_bnc_select} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:timecode_out_bnc_select} {PAP_IO_LOC} {R6} define_attribute {p:timecode_out_bnc_select} {PAP_IO_VCCIO} {1.5} define_attribute {p:timecode_out_bnc_select} {PAP_IO_STANDARD} {LVCMOS15} -define_attribute {p:timecode_out_bnc_select} {PAP_IO_DRIVE} {4} +define_attribute {p:timecode_out_bnc_select} {PAP_IO_DRIVE} {8} define_attribute {p:timecode_out_bnc_select} {PAP_IO_SLEW} {SLOW} define_attribute {p:timecode_out_headphone} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:timecode_out_headphone} {PAP_IO_LOC} {Y9} define_attribute {p:timecode_out_headphone} {PAP_IO_VCCIO} {1.5} define_attribute {p:timecode_out_headphone} {PAP_IO_STANDARD} {LVCMOS15} -define_attribute {p:timecode_out_headphone} {PAP_IO_DRIVE} {4} +define_attribute {p:timecode_out_headphone} {PAP_IO_DRIVE} {8} define_attribute {p:timecode_out_headphone} {PAP_IO_SLEW} {SLOW} define_attribute {p:timecode_out_headphone_select} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:timecode_out_headphone_select} {PAP_IO_LOC} {T3} define_attribute {p:timecode_out_headphone_select} {PAP_IO_VCCIO} {1.5} define_attribute {p:timecode_out_headphone_select} {PAP_IO_STANDARD} {LVCMOS15} -define_attribute {p:timecode_out_headphone_select} {PAP_IO_DRIVE} {4} +define_attribute {p:timecode_out_headphone_select} {PAP_IO_DRIVE} {8} define_attribute {p:timecode_out_headphone_select} {PAP_IO_SLEW} {SLOW} define_attribute {p:stm32if_start_signal_out} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:stm32if_start_signal_out} {PAP_IO_LOC} {Y21} @@ -186,107 +186,155 @@ define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {Y8} define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {1.5} define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS15} -define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4} +define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {8} define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[0]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[0]} {PAP_IO_LOC} {Y11} -define_attribute {p:debug_signal_output[0]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[0]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[0]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[0]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[0]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[0]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[1]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[1]} {PAP_IO_LOC} {Y12} -define_attribute {p:debug_signal_output[1]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[1]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[1]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[1]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[1]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[1]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[2]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[2]} {PAP_IO_LOC} {AA10} -define_attribute {p:debug_signal_output[2]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[2]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[2]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[2]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[2]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[2]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[3]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[3]} {PAP_IO_LOC} {AA11} -define_attribute {p:debug_signal_output[3]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[3]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[3]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[3]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[3]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[3]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[4]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[4]} {PAP_IO_LOC} {AB11} -define_attribute {p:debug_signal_output[4]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[4]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[4]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[4]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[4]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[4]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[5]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[5]} {PAP_IO_LOC} {AB12} -define_attribute {p:debug_signal_output[5]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[5]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[5]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[5]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[5]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[5]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[6]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[6]} {PAP_IO_LOC} {W11} -define_attribute {p:debug_signal_output[6]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[6]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[6]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[6]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[6]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[6]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[7]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[7]} {PAP_IO_LOC} {W12} -define_attribute {p:debug_signal_output[7]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[7]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[7]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[7]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[7]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[7]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[8]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[8]} {PAP_IO_LOC} {AA13} -define_attribute {p:debug_signal_output[8]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[8]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[8]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[8]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[8]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[8]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[9]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[9]} {PAP_IO_LOC} {AB13} -define_attribute {p:debug_signal_output[9]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[9]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[9]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[9]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[9]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[9]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[10]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[10]} {PAP_IO_LOC} {Y13} -define_attribute {p:debug_signal_output[10]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[10]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[10]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[10]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[10]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[10]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[11]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[11]} {PAP_IO_LOC} {AA14} -define_attribute {p:debug_signal_output[11]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[11]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[11]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[11]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[11]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[11]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[12]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[12]} {PAP_IO_LOC} {AA15} -define_attribute {p:debug_signal_output[12]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[12]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[12]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[12]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[12]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[12]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[13]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[13]} {PAP_IO_LOC} {AB15} -define_attribute {p:debug_signal_output[13]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[13]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[13]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[13]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[13]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[13]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[14]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[14]} {PAP_IO_LOC} {Y16} -define_attribute {p:debug_signal_output[14]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[14]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[14]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[14]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[14]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[14]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_signal_output[15]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[15]} {PAP_IO_LOC} {AA16} -define_attribute {p:debug_signal_output[15]} {PAP_IO_VCCIO} {1.5} -define_attribute {p:debug_signal_output[15]} {PAP_IO_STANDARD} {LVCMOS15} +define_attribute {p:debug_signal_output[15]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[15]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_signal_output[15]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_signal_output[15]} {PAP_IO_SLEW} {SLOW} define_attribute {p:core_board_debug_led} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:core_board_debug_led} {PAP_IO_LOC} {W5} define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {1.5} define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS15} -define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {4} +define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {8} define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[15]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[14]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[13]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[12]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[11]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[10]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[9]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[8]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[7]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[6]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[5]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[4]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[3]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[2]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[1]} {PAP_IO_NONE} {TRUE} +define_attribute {p:debug_signal_output[0]} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_out_dac[8]} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_out_dac[7]} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_out_dac[6]} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_out_dac[5]} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_out_dac[4]} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_out_dac[3]} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_out_dac[2]} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_out_dac[1]} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_out_dac[0]} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_out_dac_clk} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_in_fsync} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_in_hsync} {PAP_IO_NONE} {TRUE} +define_attribute {p:genlock_in_vsync} {PAP_IO_NONE} {TRUE} +define_attribute {p:sync_ttl_in1} {PAP_IO_NONE} {TRUE} +define_attribute {p:sync_ttl_in2} {PAP_IO_NONE} {TRUE} +define_attribute {p:sync_ttl_in3} {PAP_IO_NONE} {TRUE} +define_attribute {p:sync_ttl_in4} {PAP_IO_NONE} {TRUE} +define_attribute {p:timecode_bnc_in} {PAP_IO_NONE} {TRUE} +define_attribute {p:timecode_headphone_in} {PAP_IO_NONE} {TRUE} +define_attribute {p:core_board_debug_led} {PAP_IO_NONE} {TRUE} +define_attribute {p:spi1_tx_pin} {PAP_IO_NONE} {TRUE} +define_attribute {p:sync_ttl_out1} {PAP_IO_NONE} {TRUE} +define_attribute {p:sync_ttl_out2} {PAP_IO_NONE} {TRUE} +define_attribute {p:sync_ttl_out3} {PAP_IO_NONE} {TRUE} +define_attribute {p:sync_ttl_out4} {PAP_IO_NONE} {TRUE} +define_attribute {p:timecode_out_bnc} {PAP_IO_NONE} {TRUE} +define_attribute {p:timecode_out_bnc_select} {PAP_IO_NONE} {TRUE} +define_attribute {p:timecode_out_headphone} {PAP_IO_NONE} {TRUE} +define_attribute {p:timecode_out_headphone_select} {PAP_IO_NONE} {TRUE} +define_attribute {p:spi1_clk_pin} {PAP_IO_NONE} {TRUE} +define_attribute {p:spi1_cs_pin} {PAP_IO_NONE} {TRUE} +define_attribute {p:spi1_rx_pin} {PAP_IO_NONE} {TRUE} diff --git a/xsync.pds b/xsync.pds index 313e504..4963a77 100644 --- a/xsync.pds +++ b/xsync.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2022.2-SP4.2" - (_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2) at Sun Aug 25 23:05:00 2024") + (_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2) at Mon Aug 26 09:10:50 2024") (_version "1.1.0") (_status "initial") (_project @@ -21,7 +21,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-08-25T21:00:01") + (_timespec "2024-08-26T00:04:16") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -263,7 +263,7 @@ (_input (_file "xsync.fdc" (_format fdc) - (_timespec "2024-08-25T23:04:08") + (_timespec "2024-08-25T23:52:07") ) ) ) @@ -314,17 +314,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-08-25T23:04:16") + (_timespec "2024-08-26T00:04:44") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-08-25T23:04:16") + (_timespec "2024-08-26T00:04:44") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-08-25T23:04:16") + (_timespec "2024-08-26T00:04:44") ) ) ) @@ -339,25 +339,25 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-08-25T23:04:22") + (_timespec "2024-08-26T00:05:12") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-08-25T23:04:22") + (_timespec "2024-08-26T00:05:13") ) (_file "synthesize/Top_controlsets.txt" (_format text) - (_timespec "2024-08-25T23:04:22") + (_timespec "2024-08-26T00:05:11") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-08-25T23:04:22") + (_timespec "2024-08-26T00:05:13") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-08-25T23:04:22") + (_timespec "2024-08-26T00:05:13") ) ) ) @@ -378,21 +378,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-08-25T23:04:30") + (_timespec "2024-08-26T00:05:43") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-08-25T23:04:30") + (_timespec "2024-08-26T00:05:42") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-08-25T23:04:30") + (_timespec "2024-08-26T00:05:43") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-08-25T23:04:30") + (_timespec "2024-08-26T00:05:44") ) ) ) @@ -401,7 +401,7 @@ (_input (_file "device_map/xsync.pcf" (_format pcf) - (_timespec "2024-08-25T23:04:30") + (_timespec "2024-08-26T00:05:43") ) ) ) @@ -422,33 +422,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-08-25T23:04:48") + (_timespec "2024-08-26T00:07:33") ) ) (_output (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-08-25T23:04:48") + (_timespec "2024-08-26T00:07:30") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-08-25T23:04:43") + (_timespec "2024-08-26T00:06:57") ) (_file "place_route/Top.prr" (_format text) - (_timespec "2024-08-25T23:04:48") + (_timespec "2024-08-26T00:07:34") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-08-25T23:04:48") + (_timespec "2024-08-26T00:07:30") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-08-25T23:04:48") + (_timespec "2024-08-26T00:07:33") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-08-25T23:04:48") + (_timespec "2024-08-26T00:07:34") ) ) ) @@ -484,19 +484,19 @@ (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-08-25T23:04:59") + (_timespec "2024-08-26T00:08:30") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-08-25T23:04:59") + (_timespec "2024-08-26T00:08:30") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-08-25T23:05:00") + (_timespec "2024-08-26T00:08:34") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-08-25T23:05:00") + (_timespec "2024-08-26T00:08:34") ) ) ) diff --git a/xsync.pds.lock b/xsync.pds.lock deleted file mode 100644 index a663ccc..0000000 --- a/xsync.pds.lock +++ /dev/null @@ -1,5 +0,0 @@ -19944 -pds -ZHAOHE -f8caf121-d1d2-4c26-8a45-7e1d59cde8b6 -