p_lusterinc_xsync
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xsync_fpge_v2
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master
zhaohe 11 months ago
parent
a7a69201b8
commit
5f6a3c9fe2
8 changed files with 122 additions and 39 deletions
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  1. 8
      constraint_check/constraint_check.ccr
  2. 2
      ipcore/SPLL/.settings
  3. 14
      multiseed_summary.csv
  4. 4
      source/src/input/timecode_input.v
  5. 17
      source/src/timecode/timecode_decoder.v
  6. 8
      source/src/top.v
  7. 4
      xsync.fdc
  8. 104
      xsync.pds

8
constraint_check/constraint_check.ccr
View File

@ -1,4 +1,4 @@
##### Written on 2024/08/28 20:08:14 ###############################
##### Written on 2024/08/28 22:14:17 ###############################
##### INFO ##################################################
@ -38,15 +38,15 @@ define_attribute {p:sync_ttl_in3} {PAP_IO_LOC} {M13}
define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {L13}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 101)] | Port sync_ttl_in4 has been placed at location L13, whose type is share pin.
define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {R14}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 105)] | Port sync_ttl_out1 has been placed at location R14, whose type is share pin.
define_attribute {p:sync_ttl_out2} {PAP_IO_LOC} {N14}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 111)] | Port sync_ttl_out2 has been placed at location N14, whose type is share pin.
define_attribute {p:sync_ttl_out3} {PAP_IO_LOC} {R17}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 117)] | Port sync_ttl_out3 has been placed at location R17, whose type is share pin.
define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {R14}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 123)] | Port sync_ttl_out4 has been placed at location R14, whose type is share pin.
define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {L15}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 129)] | Port timecode_headphone_in has been placed at location L15, whose type is share pin.

2
ipcore/SPLL/.settings
View File

@ -0,0 +1,2 @@
[not_show_again]

14
multiseed_summary.csv
View File

@ -3,23 +3,23 @@ project name,xsync.pds
Single Seed:
Seed,State,Convergence,Setup(Slow),Setup(Fast),Hold(Slow),Hold(Fast),Recovery(Slow),Recovery(Fast),Removal(Slow),Removal(Fast),PBM-GP,PBM-PreGP,PBM-PostGP,LP,Total Placement Cpu Time,Detailed routing,Total Routing Cpu Time,Wire Length After Post-GP,Wire Length After LP,Wire Length After DP,Routing Arc Length,Worst Slack After GP Timing,Worst Slack After LP Timing,Worst Slack Before RP,Worst Slack Before DP,Worst Slack After DP,Worst Slack After Placement,Worst Slack After TA By Preroute,TNS After DP,TNS Before Route,Setup(Slow) Total Failing TNS,Setup(Slow) Total Failing Endpoints,Hold(Slow) Total Failing THS,Hold(Slow) Total Failing Endpoints,Power
single,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA
single,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,0.83,13.73,15.14,20.03,NA,NA,NA,195954,NA,NA,991796,991796,991796,991796,NA,0,0,NA,NA,NA,NA,NA
Pass Rate/Convergence Rate,0.00%,0.00%
Synthesize:
control_set,418
control_set,424
Synthesize Performance Summary:
slack category,Synthesize Setup WNS,Synthesize Setup TNS,Synthesize Recovery WNS,Synthesize Recovery TNS
slack value,992.726,0.000,996.032,0.000
Synthesize Process Cpu Time,0h:0m:22s
Synthesize Process Cpu Time,0h:0m:12s
Device Map:
Device Map Resource Usage Summary:
Logic Utilization,LUT,FF,DRM,APM,Distributed RAM,HSSTHP,USCM,HCKB,RCKB
Used,NA,NA,NA,NA,NA,NA,NA,NA,NA
Available,NA,NA,NA,NA,NA,NA,NA,NA,NA
Utilization(%),NA,NA,NA,NA,NA,NA,NA,NA,NA
Device Map Process Cpu Time,NA
Used,12576,10121,0,0,0,NA,1,0,0
Available,66600,133200,155,240,19900,NA,32,96,24
Utilization(%),19%,8%,0%,0%,0%,NA,4%,0%,0%
Device Map Process Cpu Time,0h:0m:5s
Project Configurations:
top module,Top

4
source/src/input/timecode_input.v
View File

@ -22,7 +22,7 @@ module timecode_input_parser #(
output reg [31:0] timecode_format,
output reg [63:0] timecode_data,
output reg timecode_serial_data,
output timecode_is_detected,
output timecode_is_detected,
/*******************************************************************************
* 指示灯状态输出 *
@ -198,6 +198,6 @@ module timecode_input_parser #(
assign timecode_headphone_in_state_led = 1;
assign timecode_bnc_in_state_led = 1;
assign timecode_is_detected = (state == 1) || (state == 2);
assign timecode_is_detected = (state == 1) || (state == 2);
endmodule

17
source/src/timecode/timecode_decoder.v
View File

@ -33,17 +33,28 @@ module timecode_decoder #(
//
// 原始数据输出
assign timecode_serial_data = timecode_in;
assign timecode_in_state = timecode_in;
zutils_signal_filter_advance filter1 (
.clk (clk),
.rst_n (rst_n),
.filter_delay_count(32'd5),
.in (timecode_in),
.out (timecode_in_af_filter)
);
assign timecode_serial_data = timecode_in_af_filter;
assign timecode_in_state = timecode_in_af_filter;
wire timecode_sample_sig_generator_rest_sig;
wire timecode_in_edge;
assign timecode_sample_sig_generator_rest_sig = !timecode_in_edge & rst_n;
zutils_edge_detecter _signal_in (
.clk (clk),
.rst_n (rst_n),
.in_signal (timecode_in),
.in_signal (timecode_in_af_filter),
.in_signal_edge(timecode_in_edge)
);

8
source/src/top.v
View File

@ -148,10 +148,10 @@ module Top (
assign debug_signal_output[7] = sync_ttl_out3;
assign debug_signal_output[8] = sync_ttl_out4;
assign debug_signal_output[9] = genlock_in_vsync;
assign debug_signal_output[10] = timecode_out_headphone;
assign debug_signal_output[11] = timecode_out_bnc;
assign debug_signal_output[12] = stm32if_start_signal_out;
assign debug_signal_output[13] = stm32if_camera_sync_out;
assign debug_signal_output[10] = timecode_headphone_in;
assign debug_signal_output[11] = timecode_bnc_in;
assign debug_signal_output[12] = timecode_out_headphone;
assign debug_signal_output[13] = timecode_out_bnc;
assign debug_signal_output[14] = stm32if_timecode_sync_out;
endmodule

4
xsync.fdc
View File

@ -102,7 +102,7 @@ define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {L13}
define_attribute {p:sync_ttl_in4} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_in4} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out1} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {R14}
define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {N15}
define_attribute {p:sync_ttl_out1} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_out1} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out1} {PAP_IO_DRIVE} {4}
@ -120,7 +120,7 @@ define_attribute {p:sync_ttl_out3} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out3} {PAP_IO_DRIVE} {4}
define_attribute {p:sync_ttl_out3} {PAP_IO_SLEW} {SLOW}
define_attribute {p:sync_ttl_out4} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {N15}
define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {R14}
define_attribute {p:sync_ttl_out4} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_out4} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out4} {PAP_IO_DRIVE} {4}

104
xsync.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2022.2-SP4.2"
(_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Wed Aug 28 20:08:48 2024")
(_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Wed Aug 28 22:21:19 2024")
(_version "1.1.0")
(_status "initial")
(_project
@ -21,7 +21,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-08-28T20:07:59")
(_timespec "2024-08-28T22:14:00")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -129,11 +129,11 @@
)
(_file "source/src/input/timecode_input.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-08-28T21:51:29")
)
(_file "source/src/timecode/timecode_decoder.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-08-28T21:53:27")
)
(_file "source/src/timecode/timecode_sample_sig_generator.v"
(_format verilog)
@ -271,7 +271,7 @@
(_input
(_file "xsync.fdc"
(_format fdc)
(_timespec "2024-08-28T19:32:19")
(_timespec "2024-08-28T21:48:19")
)
)
)
@ -322,17 +322,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-08-28T20:08:07")
(_timespec "2024-08-28T22:14:10")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-08-28T20:08:07")
(_timespec "2024-08-28T22:14:10")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-08-28T20:08:07")
(_timespec "2024-08-28T22:14:10")
)
)
)
@ -347,25 +347,25 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-08-28T20:08:41")
(_timespec "2024-08-28T22:16:16")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-08-28T20:08:44")
(_timespec "2024-08-28T22:16:27")
)
(_file "synthesize/Top_controlsets.txt"
(_format text)
(_timespec "2024-08-28T20:08:39")
(_timespec "2024-08-28T22:16:02")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-08-28T20:08:45")
(_timespec "2024-08-28T22:16:33")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-08-28T20:08:45")
(_timespec "2024-08-28T22:16:33")
)
)
)
@ -382,14 +382,34 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-08-28T22:17:03")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-08-28T22:16:42")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-08-28T22:17:03")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-08-28T22:17:03")
)
)
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/xsync.pcf"
(_format pcf)
(_timespec "2024-08-28T19:47:25")
(_timespec "2024-08-28T22:17:03")
)
)
)
@ -399,7 +419,7 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_option gplace_seed (_integer 8))
(_option seed_step (_integer 4))
(_option saved_outcome (_integer 4))
@ -407,6 +427,38 @@
(_option share_router_control_signal (_boolean FALSE))
(_option check_clk_net_route_by_srb (_boolean FALSE))
(_option fix_hold_violation_in_route (_boolean FALSE))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-08-28T22:20:11")
)
)
(_output
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-08-28T22:19:38")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-08-28T22:18:13")
)
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-08-28T22:20:11")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-08-28T22:19:38")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-08-28T22:20:11")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-08-28T22:20:12")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -435,8 +487,26 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_option unused_io_status (_string "KEEPER"))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-08-28T22:21:15")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-08-28T22:21:16")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-08-28T22:21:19")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-08-28T22:21:18")
)
)
)
)
)
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