diff --git a/.vscode/settings.json b/.vscode/settings.json index e69de29..384106b 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -0,0 +1,6 @@ +{ + "files.associations": { + "*.hpp": "cpp", + "xtree": "cpp" + } +} \ No newline at end of file diff --git a/fdc_generator.exe b/fdc_generator.exe index f57c433..8e94811 100644 Binary files a/fdc_generator.exe and b/fdc_generator.exe differ diff --git a/ipcore/SPLL/.last_generated b/ipcore/SPLL/.last_generated index 8ec0a2e..dfaddc2 100644 --- a/ipcore/SPLL/.last_generated +++ b/ipcore/SPLL/.last_generated @@ -1,2 +1,2 @@ -2024-01-11 09:39 +2024-08-23 14:44 rev_1 \ No newline at end of file diff --git a/ipcore/SPLL/SPLL.idf b/ipcore/SPLL/SPLL.idf index e584f38..8d047fa 100644 --- a/ipcore/SPLL/SPLL.idf +++ b/ipcore/SPLL/SPLL.idf @@ -2,632 +2,1389 @@
Pango - 021001 + 041001 PLL - Logos PLL - 1.5 + 28nm PLL + 1.2 SPLL - Logos - PGL22G - MBG324 + Logos2 + PG2L100H + FBG484 -6 IP Compiler
- RST_ENABLE_basicPage + CLKOUT3_BUFCE false - CLKOUT0_REQ_PHASE_basicPage - 0.0000 - 4 + STATIC_RATIO5_advancedPage + 24 + + + CLKOUT2_GATE_EN_basicPage + false + + + STATIC_RATIOM_advancedPage + 1 + + + CLKOUT7_EN_basicPage + false + + + CLKOUT7_BUFXCE_EN + false + + + CLKOUT1_N_EN_basicPage + false + + + CLKOUT2_BUFFER_OPTION_advancedPage + NO BUFFER + + + STATIC_RATIOM + 1 + + + FB_basicPage + 7 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + CLKOUT5_REQ_FREQ_basicPage + 50.000000 + 6 + + + STATIC_PHASE + 0 + + + STATIC_CPHASE5_advancedPage + 0 + + + CLKOUT5_GATE_EN_basicPage + false + + + CLKOUT6_BUFGCE_EN + false + + + STATIC_CPHASE1_advancedPage + 0 + + + DEVICE_Titan2 + false + + + CLKOUT0_DPS_SEL_advancedPage + false + + + STATIC_RATIO7 + 12.0 + -1 + + + CLKOUT3_EN_advancedPage + false + + + CLKOUT3_REQ_FREQ_basicPage + 50.000000 + 6 + + + CLKOUT4_DPS_SEL_advancedPage + false + + + CLKOUT3_BUFFER_OPTION_basicPage + NO BUFFER + + + CLKOUT3_GATE_EN_basicPage + false + + + CLKOUT3_BUFG_EN + false + + + CLKOUT3_REQ_PHASE_basicPage + 0.000000 + 6 + + + CLKOUT2_EN_advancedPage + false + + + STATIC_PHASE7 + 0 + + + CLKOUT7_NOBUF_EN + true + + + CLKOUT4_BUFG_EN + false + + + CLKOUT3_N_EN_advancedPage + false + + + STATIC_DUTY7 + 12 + + + CLKOUT7_BUFGCE_EN + false + + + STATIC_PHASE8 + 0 + + + CLKOUT1_N_EN_advancedPage + false + + + CLKOUT6_REQ_DUTY_basicPage + 50.000000 + 6 + + + MODE_CFG + 0 + + + CLKIN2_SOURCE_advancedPage + No Buffer + + + CLKOUT0_EN_advancedPage + true + + + STATIC_RATIO3_advancedPage + 24 + + + CLKIN2_INBUFDS_EN + false + + + CLKOUT0_BUFX_EN + false + + + STATIC_CPHASE2_advancedPage + 0 + + + STATIC_PHASE4 + 0 + + + CLKOUT2_IOCLKBUF_EN + false + + + CLKOUT6_BUFFER_OPTION_basicPage + NO BUFFER + + + CLKOUT2_EN + true + + + CLKOUT6_EN_advancedPage + false + + + CLKOUT0_DPS_SEL_basicPage + false + + + CLKOUT4_REQ_DUTY_basicPage + 50.000000 + 6 + + + CLKOUT0_REQ_FREQ_basicPage + 25.000000 + 6 + + + CLKOUT6_BUFCE + false + + + STATIC_DUTY6 + 12 + + + RST_INNER_EN_basicPage + false + + + CLKOUT4_BUFX_EN + false + + + PLL_PWD_EN_basicPage + false + + + CLKOUT2_REQ_FREQ_basicPage + 5.000000 + 6 + + + CLK_DPS0_EN + false + + + CLKOUT3_GATE_EN_advancedPage + false + + + CLKOUT4_GATE_EN_basicPage + false + + + CLKOUT0_N_EN_advancedPage + false + + + CLKOUT2_BUFCE + false + + + STATIC_PHASE3_advancedPage + 0 + + + FB_MODE + false + + + CLKOUT6_NOBUF_EN + true + + + CLKOUT0_GATE_EN_advancedPage + false + + + CLKOUT2_BUFGCE_EN + false + + + CLKOUT8_N_EN_advancedPage + false + + + CLKOUT8_REQ_DUTY_advancedPage + 24 + + + CLKOUT6_DPS_SEL_advancedPage + false + + + SSC_FREQ + 25 + + + STATIC_PHASE6 + 0 + + + CLKOUT0_BUFG_EN + false + + + STATIC_FRAC7_advancedPage + 0 + + + CLKOUT0_NOBUF_EN + true + + + STATIC_PHASE2 + 0 + + + FB_MODE_advancedPage + 0 + + + APB_EN_advancedPage + false + + + CLKOUT1_BUFFER_OPTION_advancedPage + NO BUFFER + + + CLKOUT1_REQ_PHASE_basicPage + 0.000000 + 6 + + + STATIC_CPHASE3 + 0 + + + DYNAMIC_CLKIN_EN_advancedPage + false + + + PLL_SEL_advancedPage + 0 + + + STATIC_DUTY0 + 24 + + + CLKOUT6_GATE_EN_advancedPage + false + + + CLKOUT1_EN_basicPage + true + + + CLKOUT1_GATE_EN_advancedPage + false + + + CLKOUT6_SYN_EN + false + + + CLKOUT8_GATE_EN_advancedPage + false + + + EXTERNAL_FB + DISABLE + + + STATIC_PHASE5 + 0 + + + STATIC_RATIO5_basicPage + 1 + + + STATIC_RATIO5 + 12 + + + CLKOUT5_DPS_SEL_basicPage + false + + + CLKOUT8_REQ_DUTY_basicPage + 50.000000 + 6 + + + CLKOUT1_NOBUF_EN + true + + + CLKOUT3_REQ_DUTY_basicPage + 50.000000 + 6 + + + CLKOUT5_SYN_EN + false + + + STATIC_CPHASE8_advancedPage + 0 + + + CLKOUT0_SYN_EN + false + + + CLKOUT2_N_EN + false + + + STATIC_RATIO8_advancedPage + 24 + + + FB_advancedPage + 7 + + + CLKIN_FREQ_advancedPage + 50.000000 + 6 + + + STATIC_PHASE2_advancedPage + 0 + + + STATIC_CPHASE3_advancedPage + 0 + + + CLKOUT6_BUFXCE_EN + false + + + CLKOUT7_EN_advancedPage + false + + + CLKOUT3_EN + false + + + APB_EN + false + + + CLKOUT3_BUFX_EN + false + + + CLKOUT7_BUFCE + false + + + CLKOUT3_BUFR_EN + false + + + CLKOUT7_EN + false + + + CLKOUT0_N_EN_basicPage + false + + + STATIC_DUTY4 + 12 + + + CLKOUT7_SYN_EN + false + + + SSC_FREQ_basicPage + 25 + + + APB_EN_basicPage + false + + + CLKOUT0_REQ_DUTY_basicPage + 50.000000 + 6 + + + CLKOUT3_N_EN + false + + + DYNAMIC_PHASE_EN + false + + + CLKOUT4_EN + false + + + CLKOUT1_BUFG_EN + false + + + CLKOUT4_DPS_SEL_basicPage + false + + + CLKOUT1_N_EN + false + + + FB_MODE_basicPage + 0 + + + STATIC_CPHASE5 + 0 + + + STATIC_DUTY3 + 12 + + + CLKOUT1_DPS_SEL_advancedPage + false + + + STATIC_CPHASE4_advancedPage + 0 + + + CLKOUT6_REQ_DUTY_advancedPage + 24 + + + STATIC_RATIO1 + 60 + + + CLKOUT1_BUFX_EN + false + + + SSC_MODE + DISABLE + + + CLKOUT0_REQ_DUTY_advancedPage + 24 + + + CLKOUT2_BUFXCE_EN + false + + + CLKIN1_INBUF_EN + false + + + STATIC_RATIO8 + 1 + + + CLK_DPS6_EN + false + + + CLKOUT4_NOBUF_EN + true + + + CLKOUT2_GATE_EN_advancedPage + false + + + CLKOUT6_BUFG_EN + false + + + STATIC_PHASE4_advancedPage + 0 + + + CLKOUT3_DPS_SEL_basicPage + false + + + DYNAMIC_CLKIN_EN + false + + + CLKOUT8_GATE_EN_basicPage + false + + + PLL_PWD_EN_advancedPage + false + + + STATIC_DUTY1 + 60 + + + CLKOUT5_BUFXCE_EN + false + + + STATIC_PHASE5_advancedPage + 0 + + + SSC_FREQ_advancedPage + 25 + + + CLK_DPS1_EN + false + + + CLKIN1_SOURCE_advancedPage + No Buffer + + + CLKOUT5_BUFFER_OPTION_advancedPage + NO BUFFER + + + CLKOUT1_BUFFER_OPTION_basicPage + NO BUFFER + + + CLKOUT7_BUFFER_OPTION_advancedPage + NO BUFFER + + + CLKOUT2_REQ_DUTY_advancedPage + 24 + + + SSC_EN_advancedPage + DISABLE + + + STATIC_RATIO4 + 12 + + + CLKOUT8_N_EN + false + + + STATIC_RATIO6 + 12 + + + CLK_DPS5_EN + false + + + STATIC_RATIO2 + 120 + + + CLKOUT3_REQ_DUTY_advancedPage + 24 - RSTODIV_ENABLE_advancedPage + CLKIN1_INBUFDS_EN false - STATIC_RATIOF_basicPage - 24 + STATIC_PHASE0 + 0 - CLKOUT3_REQ_FREQ_basicPage - 50.0000 - 4 + STATIC_RATIO2_advancedPage + 24 - CLKOUT4_REQ_PHASE_basicPage - 0.0000 - 4 + CLKOUT5_GATE_EN_advancedPage + false - CLKOUT1_REQ_DUTY_basicPage - 50.0000 - 4 + LOCK_MODE_advancedPage + false - FEEDBACK_DELAY_ENABLE_advancedPage + CLKOUT1_BUFCE false - DYNAMIC_RATIO0_EN_advancedPage + CLKOUT2_BUFFER_OPTION_basicPage + NO BUFFER + + + CLKOUT2_BUFX_EN false - DYNAMIC_CLKIN_EN_basicPage + CLKOUT7_GATE_EN_advancedPage false - CLKOUT0_EN_basicPage + STATIC_PHASE1_advancedPage + 0 + + + CLKOUT3_NOBUF_EN true - DYNAMIC_PHASE0_EN_advancedPage + STATIC_RATIO7_advancedPage + 24 + + + CLKOUT7_GATE_EN_basicPage false - STATIC_RATIO2_advancedPage - 16 + CLK_DPS3_EN + false - CLKOUT3_EN_basicPage + DYNAMIC_CLKIN_EN_basicPage false - LOOP_MAPPING_EN_advancedPage + CLKOUT0_BUFCE false - STATIC_PHASE3_basicPage - 16 + CLKIN2_SOURCE_basicPage + No Buffer - STATIC_DUTY0_basicPage - 24 + CLKOUT4_REQ_FREQ_basicPage + 50.000000 + 6 - STATIC_RATIOM_advancedPage - 1 + CLKOUT5_EN + false + + + CLKOUT6_DPS_SEL_basicPage + false CLKOUT2_EN_basicPage true - STATIC_DUTY0_advancedPage - 16 + CLKOUT7_DPS_SEL_advancedPage + false - PFDEN_EN_advancedPage + CLKOUT6_EN false - FBDIV_SEL_basicPage - 0 + STATIC_RATIO4_advancedPage + 24 - CLKOUT4_REQ_FREQ_basicPage - 50.0000 - 4 + CLKOUT2_SYN_EN + false - CLKOUT4_GATE_EN_advancedPage + CLKIN2_BUFG_EN false - CLKIN_SEL_ENABLE_advancedPage - false + CLKOUT1_REQ_DUTY_advancedPage + 24 - CLKOUT5_EN_advancedPage + CLKOUT7_N_EN false - CLK_CAS4_EN_advancedPage + CLKOUT4_BUFCE false - CLKOUT5_SEL_advancedPage - 0 + CLKOUT6_REQ_FREQ_basicPage + 50.000000 + 6 - STATIC_DUTYF_basicPage - 24 + CLKOUT1_REQ_FREQ_basicPage + 10.000000 + 6 - STATIC_RATIO3_advancedPage - 16 + CLKOUT7_REQ_DUTY_advancedPage + 24 - DYNAMIC_PHASE1_EN_advancedPage - false + BANDWIDTH_advancedPage + OPTIMIZED - STATIC_DUTY1_advancedPage - 16 + CLKOUT4_BUFFER_OPTION_basicPage + NO BUFFER - CLKOUT2_REQ_PHASE_basicPage - 0.0000 - 4 + CLKIN_FREQ_basicPage + 50.000000 + 6 - CLKOUT4_EN_advancedPage - false + CLKOUT0_BUFFER_OPTION_basicPage + NO BUFFER - CLKOUT3_GATE_EN_advancedPage - false + STATIC_PHASE7_advancedPage + 0 - FBMODE_advancedPage - false + STATIC_RATIOI_advancedPage + 1 - CLKIN_BYPASS_EN_basicPage + PLL_PWD_EN false - DYNAMIC_RATIO4_EN_advancedPage + CLKOUT1_BUFR_EN false - CLKSWITCH_FLAG_ENABLE_advancedPage + CLKOUT7_BUFX_EN false - PLL_PWD_ENABLE_advancedPage - false + STATIC_CPHASE7_advancedPage + 0 - MODE - false + STATIC_PHASE1 + 0 - STATIC_RATIO4_advancedPage - 16 + SSC_EN_basicPage + DISABLE - DYNAMIC_RATIO2_EN_advancedPage + CLKOUT4_EN_advancedPage false - CLKOUT1_REQ_PHASE_basicPage - 0.0000 - 4 + CLKOUT0_EN_basicPage + true - CLK_CAS2_EN_basicPage + PLL_MODE false - CLKOUT3_EN_advancedPage + CLKOUT8_SYN_EN false - STATIC_PHASE4_advancedPage - 16 + STATIC_PHASE6_advancedPage + 0 - CLKIN_FREQ_basicPage - 50.0000 - 4 + STATIC_CPHASE8 + 0 - STATIC_RATIO0_basicPage - 24 + CLKOUT5_BUFFER_OPTION_basicPage + NO BUFFER - CLK_CAS4_EN_basicPage - false + CLKIN1_NOBUF_EN + true - CLKIN_FREQ_advancedPage - 50.0000 - 4 + STATIC_DUTY2 + 120 - PLL_PWD_ENABLE_basicPage + CLK_DPS7_EN false - CLKOUT0_GATE_EN_basicPage + CLKOUT3_BUFGCE_EN false - CLKOUT4_EN_basicPage + CLKOUT0_GATE_EN_basicPage false - SHOW_SETTING_EN_basicPage - false + CLKOUT8_REQ_FREQ_basicPage + 50.000000 + 6 - CLKOUT2_REQ_FREQ_basicPage - 5.0000 - 4 + CLKOUT0_BUFFER_OPTION_advancedPage + NO BUFFER - CLKOUT2_GATE_EN_advancedPage + CLKOUT4_REQ_PHASE_basicPage + 0.000000 + 6 + + + DYNAMIC_PHASE_EN_basicPage false - STATIC_RATIO2_basicPage - 120 + CLKOUT1_GATE_EN_basicPage + false - DYNAMIC_PHASE2_EN_advancedPage + CLKOUT8_EN_advancedPage false - CLKOUT1_REQ_FREQ_basicPage - 10.0000 - 4 + CLKOUT4_REQ_DUTY_advancedPage + 24 - CLKIN_BYPASS_EN_advancedPage + CLKOUT1_IOCLKBUF_EN false - STATIC_RATIOM_basicPage - 1 + DEVICE_PG2L50H + false - CLKOUT1_GATE_EN_basicPage + CLKOUT2_N_EN_basicPage false - CLKIN_SEL_ENABLE_basicPage - false + PLL_SEL_basicPage + 0 - CLKOUT1_GATE_EN_advancedPage - false + CLKOUT7_BUFFER_OPTION_basicPage + NO BUFFER - DYNAMIC_PHASE_EN_advancedPage - false + STATIC_CPHASE0_advancedPage + 0 - DYNAMIC_LOOP_EN_advancedPage + CLKOUT1_REQ_DUTY_basicPage + 50.000000 + 6 + + + CLKOUT6_GATE_EN_basicPage false - CLKOUT3_GATE_EN_basicPage + CLKOUT2_DPS_SEL_basicPage false - STATIC_DUTY3_basicPage - 16 + CLKOUT7_REQ_DUTY_basicPage + 50.000000 + 6 - FEEDBACK_DELAY_VALUE_advancedPage - 0.000 - 3 + CLKOUT5_EN_advancedPage + false - CLKOUT0_REQ_FREQ_basicPage - 25.0000 - 4 + CLKOUT1_BUFGCE_EN + false - CLKOUT4_GATE_EN_basicPage + ODIV5_CASCADE_EN_basicPage false - STATIC_RATIO4_basicPage - 16 + STATIC_PHASE8_advancedPage + 0 - CLKOUT0_EXT_GATE_EN_basicPage + CLKOUT0_N_EN false - CLKOUT0_EXT_EN_advancedPage - false + CLKOUT5_REQ_PHASE_basicPage + 0.000000 + 6 - CLKOUT2_REQ_DUTY_basicPage - 50.0000 - 4 + CLKOUT1_EN + true - CLKOUT2_GATE_EN_basicPage + CLKOUT8_EN_basicPage false - RST_ENABLE_advancedPage + CLKOUT3_N_EN_basicPage false - CLKOUT2_EN_advancedPage + CLKOUT1_BUFXCE_EN + false + + + InsertPhase_advancedPage + 0 + + + CLKOUT4_BUFGCE_EN false - FBMODE_basicPage + CLKOUT3_DPS_SEL_advancedPage false - STATIC_DUTY3_advancedPage - 16 + CLKIN2_NOBUF_EN + true - STATIC_DUTY2_advancedPage - 16 + STATIC_RATIO3 + 12 - STATIC_RATIOI_advancedPage - 2 + CLKOUT3_BUFXCE_EN + false - FBDIV_SEL_advancedPage + STATIC_FRAC0_advancedPage 0 - DYNAMIC_PHASE3_EN_advancedPage + CLK_CAS5_EN false - CLKIN_SEL_EN_ENABLE_basicPage + CLKOUT5_REQ_DUTY_advancedPage + 24 + + + STATIC_RATIO0 + 24.0 + -1 + + + CLKOUT0_BUFR_EN false - CLKOUT4_REQ_DUTY_basicPage - 50.0000 - 4 + CLKOUT4_BUFFER_OPTION_advancedPage + NO BUFFER - FEEDBACK_DELAY_VALUE_basicPage - 0.000 - 3 + STATIC_RATIO1_advancedPage + 24 - STATIC_PHASE1_advancedPage - 16 + CLKOUT0_REQ_PHASE_basicPage + 0.000000 + 6 - DYNAMIC_DUTY1_EN_advancedPage - false + STATIC_RATIO0_advancedPage + 24 - CLKSWITCH_FLAG_ENABLE_basicPage + CLKOUT7_N_EN_basicPage false - DYNAMIC_RATIOM_EN_advancedPage + CLKOUT1_SYN_EN false - DEVICE_PGL22 - true + STATIC_CPHASE2 + 0 - STATIC_PHASE2_basicPage - 16 + CLKOUT8_EN + false - FEEDBACK_DELAY_ENABLE_basicPage - false + STATIC_PHASE0_advancedPage + 0 - STATIC_DUTY4_basicPage - 16 + CLKIN1_SOURCE_basicPage + No Buffer - DYNAMIC_RATIOI_EN_advancedPage + CLKOUT5_DPS_SEL_advancedPage false - CLK_CAS2_EN_advancedPage - false + CLKOUT2_NOBUF_EN + true - VCODIV2_ENABLE_advancedPage + RST_INNER_EN false - CLKOUT0_EXT_EN_basicPage + CLKOUT5_NOBUF_EN + true + + + CLK_DPS2_EN false - MODE_CFG + STATIC_CPHASE4 0 - BANDWIDTH_advancedPage - OPTIMIZED + CLKOUT0_EN + true - STATIC_RATIO3_basicPage - 16 + CLKOUT4_EN_basicPage + false - STATIC_PHASE0_advancedPage - 16 + CLKOUT7_REQ_PHASE_basicPage + 0.000000 + 6 - STATIC_PHASE1_basicPage - 16 + STATIC_CPHASE7 + 0 - DYNAMIC_CLKIN_EN_advancedPage + CLKOUT4_BUFXCE_EN false - DEVICE_PGL35 + CLKOUT0_IOCLKBUF_EN false - STATIC_RATIO1_advancedPage - 16 + STATIC_DUTY5 + 12 - CLKOUT0_EXT_GATE_EN_advancedPage + CLKOUT0_BUFXCE_EN false - CLKOUT0_REQ_DUTY_basicPage - 50.0000 - 4 + CLKOUT2_REQ_PHASE_basicPage + 0.000000 + 6 - DYNAMIC_DUTY2_EN_advancedPage + CLKOUT7_BUFG_EN false - STATIC_DUTY4_advancedPage - 16 + DYNAMIC_PHASE_EN_advancedPage + false - STATIC_RATIO0_advancedPage - 16 + CLKOUT7_DPS_SEL_basicPage + false - FB_MODE_advancedPage - 0 + CLKIN1_BUFG_EN + false - STATIC_RATIOF_advancedPage - 16 + CLKOUT7_REQ_FREQ_basicPage + 50.000000 + 6 - STATIC_RATIOI_basicPage - 2 + STATIC_CPHASE1 + 0 - DYNAMIC_PHASE4_EN_advancedPage + CLKOUT3_IOCLKBUF_EN false - CLKOUT3_REQ_DUTY_basicPage - 50.0000 - 4 + CLKOUT4_SYN_EN + false - DYNAMIC_RATIO1_EN_advancedPage + CLKOUT3_SYN_EN false - STATIC_DUTY2_basicPage - 120 + CLKOUT4_GATE_EN_advancedPage + false - STATIC_PHASE3_advancedPage - 16 + CLKOUT2_BUFR_EN + false - STATIC_PHASE2_advancedPage - 16 + CLKOUT5_BUFCE + false - DYNAMIC_RATIO3_EN_advancedPage + RST_INNER_EN_advancedPage false - DYNAMIC_DUTY3_EN_advancedPage + INTERNAL_FB + CLKOUTF + + + CLKOUT2_REQ_DUTY_basicPage + 50.000000 + 6 + + + CLKOUT5_EN_basicPage false - BANDWIDTH_basicPage - OPTIMIZED + CLKOUT8_REQ_PHASE_basicPage + 0.000000 + 6 - STATIC_PHASE0_basicPage - 16 + STATIC_RATIO6_advancedPage + 24 - STATIC_RATIO1_basicPage - 60 + STATIC_CPHASE6_advancedPage + 0 - DYNAMIC_RATIOF_EN_advancedPage + CLKIN2_INBUF_EN false - CLKOUT5_GATE_EN_advancedPage + CLKOUT6_BUFX_EN false - FB_MODE_basicPage + CLKOUT6_BUFFER_OPTION_advancedPage + NO BUFFER + + + STATIC_CPHASE6 0 - CLK_CAS1_EN_advancedPage + STATIC_CPHASE0 + 0 + + + CLKOUT7_N_EN_advancedPage false - CLKOUT0_EN_advancedPage - true + CLKOUT8_N_EN_basicPage + false - CLKOUT1_EN_advancedPage + CLKOUT5_BUFGCE_EN false - CLK_CAS1_EN_basicPage + CLKOUT6_EN_basicPage false - CLKOUT1_EN_basicPage - true + CLKOUT5_BUFX_EN + false - DYNAMIC_DUTY4_EN_advancedPage + CLKOUT2_N_EN_advancedPage false - CLKOUT3_REQ_PHASE_basicPage - 0.0000 - 4 + CLK_DPS4_EN + false - DYNAMIC_DUTY0_EN_advancedPage + CLKOUT2_DPS_SEL_advancedPage false - CLKOUT0_GATE_EN_advancedPage + BANDWIDTH + HIGH + + + CLKOUT5_REQ_DUTY_basicPage + 50.000000 + 6 + + + CLKOUT3_BUFFER_OPTION_advancedPage + NO BUFFER + + + STATIC_DUTY8 + 2 + + + CLKOUT5_BUFG_EN + false + + + CLKOUT2_BUFG_EN + false + + + CLKOUT3_EN_basicPage false - DEVICE_PGL12 + LOCK_MODE + 0 + + + CLKOUT1_DPS_SEL_basicPage false - CLK_CAS3_EN_basicPage + CLKOUT1_EN_advancedPage false - CLK_CAS3_EN_advancedPage + CLKOUT0_BUFGCE_EN false - CLKIN_SEL_EN_ENABLE_advancedPage + CLKIN_FREQ + 50.000000 + 6 + + + ODIV5_CASCADE_EN_advancedPage false - STATIC_PHASE4_basicPage - 16 + CLKOUT6_REQ_PHASE_basicPage + 0.000000 + 6 - STATIC_DUTY1_basicPage - 60 + STATIC_RATIOI + 1 + + + STATIC_PHASE3 + 0 - clkin1 - clkin1 - input - left - - - pll_lock - pll_lock - output - right - - clkout0 clkout0 output @@ -645,6 +1402,18 @@ output right + + lock + lock + output + right + + + clkin1 + clkin1 + input + left + diff --git a/ipcore/SPLL/SPLL.v b/ipcore/SPLL/SPLL.v index c71a4d2..0a3c7e5 100644 --- a/ipcore/SPLL/SPLL.v +++ b/ipcore/SPLL/SPLL.v @@ -1,7 +1,6 @@ // Created by IP Generator (Version 2021.1-SP7 build 86875) - ////////////////////////////////////////////////////////////////////////////// // // Copyright (c) 2019 PANGO MICROSYSTEMS, INC @@ -16,284 +15,361 @@ // Library: // Filename:SPLL.v ////////////////////////////////////////////////////////////////////////////// +`timescale 1ns/10fs module SPLL ( - clkin1, - clkout0, - clkout1, - clkout2, - pll_lock + output wire clkout0, + + output wire clkout1, + + output wire clkout2, + + input wire clkin1, + + output wire lock ); - localparam real CLKIN_FREQ = 50.0; - localparam integer STATIC_RATIOI = 2; - localparam integer STATIC_RATIO0 = 24; - localparam integer STATIC_RATIO1 = 60; - localparam integer STATIC_RATIO2 = 120; - localparam integer STATIC_RATIO3 = 16; - localparam integer STATIC_RATIO4 = 16; - localparam integer STATIC_RATIOF = 24; - localparam integer STATIC_DUTY0 = 24; - localparam integer STATIC_DUTY1 = 60; - localparam integer STATIC_DUTY2 = 120; - localparam integer STATIC_DUTY3 = 16; - localparam integer STATIC_DUTY4 = 16; - localparam integer STATIC_DUTYF = 24; - localparam integer STATIC_PHASE0 = 16; - localparam integer STATIC_PHASE1 = 16; - localparam integer STATIC_PHASE2 = 16; - localparam integer STATIC_PHASE3 = 16; - localparam integer STATIC_PHASE4 = 16; - localparam CLK_CAS1_EN = "FALSE"; - localparam CLK_CAS2_EN = "FALSE"; - localparam CLK_CAS3_EN = "FALSE"; - localparam CLK_CAS4_EN = "FALSE"; - localparam CLKIN_BYPASS_EN = "FALSE"; - localparam CLKOUT0_GATE_EN = "FALSE"; - localparam CLKOUT0_EXT_GATE_EN = "FALSE"; - localparam CLKOUT1_GATE_EN = "FALSE"; - localparam CLKOUT2_GATE_EN = "FALSE"; - localparam CLKOUT3_GATE_EN = "FALSE"; - localparam CLKOUT4_GATE_EN = "FALSE"; - localparam FBMODE = "FALSE"; - localparam integer FBDIV_SEL = 0; - localparam BANDWIDTH = "OPTIMIZED"; - localparam PFDEN_EN = "FALSE"; - localparam VCOCLK_DIV2 = 1'b0; - localparam DYNAMIC_RATIOI_EN = "FALSE"; - localparam DYNAMIC_RATIO0_EN = "FALSE"; - localparam DYNAMIC_RATIO1_EN = "FALSE"; - localparam DYNAMIC_RATIO2_EN = "FALSE"; - localparam DYNAMIC_RATIO3_EN = "FALSE"; - localparam DYNAMIC_RATIO4_EN = "FALSE"; - localparam DYNAMIC_RATIOF_EN = "FALSE"; - localparam DYNAMIC_DUTY0_EN = "FALSE"; - localparam DYNAMIC_DUTY1_EN = "FALSE"; - localparam DYNAMIC_DUTY2_EN = "FALSE"; - localparam DYNAMIC_DUTY3_EN = "FALSE"; - localparam DYNAMIC_DUTY4_EN = "FALSE"; - localparam DYNAMIC_DUTYF_EN = "FALSE"; - localparam PHASE_ADJUST0_EN = "TRUE"; - localparam PHASE_ADJUST1_EN = (CLK_CAS1_EN == "TRUE") ? "FALSE" : "TRUE"; - localparam PHASE_ADJUST2_EN = (CLK_CAS2_EN == "TRUE") ? "FALSE" : "TRUE"; - localparam PHASE_ADJUST3_EN = (CLK_CAS3_EN == "TRUE") ? "FALSE" : "TRUE"; - localparam PHASE_ADJUST4_EN = (CLK_CAS4_EN == "TRUE") ? "FALSE" : "TRUE"; - localparam DYNAMIC_PHASE0_EN = "FALSE"; - localparam DYNAMIC_PHASE1_EN = "FALSE"; - localparam DYNAMIC_PHASE2_EN = "FALSE"; - localparam DYNAMIC_PHASE3_EN = "FALSE"; - localparam DYNAMIC_PHASE4_EN = "FALSE"; - localparam DYNAMIC_PHASEF_EN = "FALSE"; - localparam integer STATIC_PHASEF = 16; - localparam CLK_CAS0_EN = "FALSE"; - localparam integer CLKOUT5_SEL = 0; - localparam CLKOUT5_GATE_EN = "FALSE"; - localparam INTERNAL_FB = (FBMODE == "FALSE") ? "ENABLE":"DISABLE"; - localparam EXTERNAL_FB = (FBMODE == "FALSE") ? "DISABLE": - (FBDIV_SEL == 0) ? "CLKOUT0": - (FBDIV_SEL == 1) ? "CLKOUT1": - (FBDIV_SEL == 2) ? "CLKOUT2": - (FBDIV_SEL == 3) ? "CLKOUT3": - (FBDIV_SEL == 4) ? "CLKOUT4":"DISABLE"; - localparam RSTODIV_ENABLE = "FALSE"; - localparam SIM_DEVICE = "PGL22G"; - - input clkin1; - output clkout0; - output clkout1; - output clkout2; + // Parameter + + localparam real CLKIN_FREQ = 50.0; //@IPC float 10.0,500.0 + + localparam LOCK_MODE = 0; //@IPC enum 0,1 + + localparam integer STATIC_RATIOI = 1; //@IPC int 1,80 + + localparam integer STATIC_RATIOM = 1; //@IPC int 1,128 + + localparam real STATIC_RATIO0 = 24.0; //@IPC int 1.0000,128.0000 + + localparam integer STATIC_RATIO1 = 60; //@IPC int 1,128 + + localparam integer STATIC_RATIO2 = 120; //@IPC int 1,128 + + localparam integer STATIC_RATIO3 = 12; //@IPC int 1,128 + + localparam integer STATIC_RATIO4 = 12; //@IPC int 1,128 + + localparam integer STATIC_RATIO5 = 12; //@IPC int 1,128 + + localparam integer STATIC_RATIO6 = 12; //@IPC int 1,128 + + localparam real STATIC_RATIOF = 12.0; //@IPC int 1.0000,128.0000 + + localparam integer STATIC_RATIOPHY = 1; //@IPC int 1,128 + + localparam integer STATIC_DUTY0 = 24; //@IPC int 2,255 + + localparam integer STATIC_DUTY1 = 60; //@IPC int 2,255 + + localparam integer STATIC_DUTY2 = 120; //@IPC int 2,255 + + localparam integer STATIC_DUTY3 = 12; //@IPC int 2,255 + + localparam integer STATIC_DUTY4 = 12; //@IPC int 2,255 + + localparam integer STATIC_DUTY5 = 12; //@IPC int 2,255 + + localparam integer STATIC_DUTY6 = 12; //@IPC int 2,255 + + localparam integer STATIC_DUTYF = 12; //@IPC int 2,255 + + localparam integer STATIC_DUTYPHY = 2; //@IPC int 2,255 + + localparam integer STATIC_PHASE = 0; //@IPC int 0,63 + + localparam integer STATIC_PHASE0 = 0; //@IPC int 0,7 + + localparam integer STATIC_PHASE1 = 0; //@IPC int 0,7 + + localparam integer STATIC_PHASE2 = 0; //@IPC int 0,7 + + localparam integer STATIC_PHASE3 = 0; //@IPC int 0,7 + + localparam integer STATIC_PHASE4 = 0; //@IPC int 0,7 + + localparam integer STATIC_PHASE5 = 0; //@IPC int 0,7 + + localparam integer STATIC_PHASE6 = 0; //@IPC int 0,7 + + localparam integer STATIC_PHASEF = 0; //@IPC int 0,7 + + localparam integer STATIC_PHASEPHY = 0; //@IPC int 0,7 + + localparam integer STATIC_CPHASE0 = 0; //@IPC int 0,127 + + localparam integer STATIC_CPHASE1 = 0; //@IPC int 0,127 + + localparam integer STATIC_CPHASE2 = 0; //@IPC int 0,127 + + localparam integer STATIC_CPHASE3 = 0; //@IPC int 0,127 + + localparam integer STATIC_CPHASE4 = 0; //@IPC int 0,127 + + localparam integer STATIC_CPHASE5 = 0; //@IPC int 0,127 + + localparam integer STATIC_CPHASE6 = 0; //@IPC int 0,127 + + localparam integer STATIC_CPHASEF = 0; //@IPC int 0,127 + + localparam integer STATIC_CPHASEPHY = 0; //@IPC int 0,127 + + localparam CLK_DPS0_EN = "FALSE"; //@IPC bool + + localparam CLK_DPS1_EN = "FALSE"; //@IPC bool + + localparam CLK_DPS2_EN = "FALSE"; //@IPC bool + + localparam CLK_DPS3_EN = "FALSE"; //@IPC bool + + localparam CLK_DPS4_EN = "FALSE"; //@IPC bool + + localparam CLK_DPS5_EN = "FALSE"; //@IPC bool + + localparam CLK_DPS6_EN = "FALSE"; //@IPC bool + + localparam CLK_DPSF_EN = "FALSE"; //@IPC bool + + localparam CLK_CAS5_EN = "FALSE"; //@IPC bool + + localparam CLKOUT0_SYN_EN = "FALSE"; //@IPC bool + + localparam CLKOUT1_SYN_EN = "FALSE"; //@IPC bool + + localparam CLKOUT2_SYN_EN = "FALSE"; //@IPC bool + + localparam CLKOUT3_SYN_EN = "FALSE"; //@IPC bool + + localparam CLKOUT4_SYN_EN = "FALSE"; //@IPC bool + + localparam CLKOUT5_SYN_EN = "FALSE"; //@IPC bool + + localparam CLKOUT6_SYN_EN = "FALSE"; //@IPC bool + + localparam CLKOUTF_SYN_EN = "FALSE"; //@IPC bool + + localparam CLKOUTPHY_SYN_EN = "FALSE"; //@IPC bool + + localparam SSC_MODE = "DISABLE"; //@IPC enum DISABLE, DOWN_LOW, DOWN_HIGH, CENTER_LOW, CENTER_HIGH + + localparam real SSC_FREQ = 25; //@IPC int 25,250 + + localparam INTERNAL_FB = "CLKOUTF"; //@IPC enum CLKOUT0,CLKOUT1,CLKOUT2,CLKOUT3,CLKOUT4,CLKOUT5,CLKOUT6,DISABLE + + localparam EXTERNAL_FB = "DISABLE"; //@IPC enum CLKOUT0,CLKOUT1,CLKOUT2,CLKOUT3,CLKOUT4,CLKOUT5,CLKOUT6,DISABLE + + localparam BANDWIDTH = "HIGH"; //@IPC enum OPTIMIZED,LOW,HIGH - output pll_lock; - - wire clkout0; - wire clkout0_2pad; - wire clkout1; - wire clkout2; - wire clkout3; - wire clkout4; - wire clkout5; - wire clkswitch_flag; - wire pll_lock; - wire clkin1; wire clkin2; + assign clkin2 = 1'b0; + wire clkfb; + assign clkfb = 1'b0; + wire clkin_sel; - wire clkin_sel_en; - wire pfden; - wire clkout0_gate; - wire clkout0_2pad_gate; - wire clkout1_gate; - wire clkout2_gate; - wire clkout3_gate; - wire clkout4_gate; - wire clkout5_gate; - wire [9:0] dyn_idiv; - wire [9:0] dyn_odiv0; - wire [9:0] dyn_odiv1; - wire [9:0] dyn_odiv2; - wire [9:0] dyn_odiv3; - wire [9:0] dyn_odiv4; - wire [9:0] dyn_fdiv; - wire [9:0] dyn_duty0; - wire [9:0] dyn_duty1; - wire [9:0] dyn_duty2; - wire [9:0] dyn_duty3; - wire [9:0] dyn_duty4; - wire [12:0] dyn_phase0; - wire [12:0] dyn_phase1; - wire [12:0] dyn_phase2; - wire [12:0] dyn_phase3; - wire [12:0] dyn_phase4; + assign clkin_sel = 1'b0; + + wire dps_clk; + wire dps_en; + wire dps_dir; + assign dps_clk = 1'b0; + assign dps_en = 1'b0; + assign dps_dir = 1'b0; + + wire clkout0_syn; + assign clkout0_syn = 1'b0; + + wire clkout1_syn; + assign clkout1_syn = 1'b0; + + wire clkout2_syn; + assign clkout2_syn = 1'b0; + + wire clkout3_syn; + assign clkout3_syn = 1'b0; + + wire clkout4_syn; + assign clkout4_syn = 1'b0; + + wire clkout5_syn; + assign clkout5_syn = 1'b0; + + wire clkout6_syn; + assign clkout6_syn = 1'b0; + + wire clkoutf_syn; + assign clkoutf_syn = 1'b0; + wire pll_pwd; - wire pll_rst; - wire rstodiv; - wire icp_base; - wire [3:0] icp_sel; - wire [2:0] lpfres_sel; - wire cripple_sel; - wire [2:0] phase_sel; - wire phase_dir; - wire phase_step_n; - wire load_phase; - wire [6:0] dyn_mdiv; - - assign clkin2 = 1'b0; - assign clkin_sel = 1'b0; - assign clkin_sel_en = 1'b0; - - assign pll_pwd = 1'b0; - - assign pll_rst = 1'b0; - - assign rstodiv = 1'b0; + assign pll_pwd = 1'b0; + + wire rst; + assign rst = 1'b0; + + wire apb_clk; + wire apb_rst_n; + wire [4:0] apb_addr; + wire apb_sel; + wire apb_en; + wire apb_write; + wire [15:0] apb_wdata; + + assign apb_clk = 1'd0; + assign apb_rst_n = 1'd0; + assign apb_addr [4:0] = 5'd0; + assign apb_sel = 1'd0; + assign apb_en = 1'd0; + assign apb_write = 1'd0; + assign apb_wdata [15:0] = 16'd0; + + GTP_GPLL #( -GTP_PLL_E1 #( - .CLKIN_FREQ(CLKIN_FREQ), - .PFDEN_EN(PFDEN_EN), - .VCOCLK_DIV2(VCOCLK_DIV2), - .DYNAMIC_RATIOI_EN(DYNAMIC_RATIOI_EN), + .CLKIN_FREQ (CLKIN_FREQ ), + .LOCK_MODE (LOCK_MODE ), + .STATIC_RATIOI (STATIC_RATIOI ), + .STATIC_RATIOM (STATIC_RATIOM ), + + .STATIC_RATIO0 (STATIC_RATIO0 ), + .STATIC_RATIO1 (STATIC_RATIO1 ), + .STATIC_RATIO2 (STATIC_RATIO2 ), + .STATIC_RATIO3 (STATIC_RATIO3 ), + .STATIC_RATIO4 (STATIC_RATIO4 ), + + .STATIC_RATIO5 (STATIC_RATIO5 ), + .STATIC_RATIO6 (STATIC_RATIO6 ), + + .STATIC_RATIOF (STATIC_RATIOF ), + + .STATIC_DUTY0 (STATIC_DUTY0 ), + .STATIC_DUTY1 (STATIC_DUTY1 ), + .STATIC_DUTY2 (STATIC_DUTY2 ), + .STATIC_DUTY3 (STATIC_DUTY3 ), + .STATIC_DUTY4 (STATIC_DUTY4 ), + + .STATIC_DUTY5 (STATIC_DUTY5 ), + .STATIC_DUTY6 (STATIC_DUTY6 ), + + .STATIC_DUTYF (STATIC_DUTYF ), + + .STATIC_PHASE (STATIC_PHASE ), + + .STATIC_PHASE0 (STATIC_PHASE0 ), + .STATIC_PHASE1 (STATIC_PHASE1 ), + .STATIC_PHASE2 (STATIC_PHASE2 ), + .STATIC_PHASE3 (STATIC_PHASE3 ), + .STATIC_PHASE4 (STATIC_PHASE4 ), + + .STATIC_PHASE5 (STATIC_PHASE5 ), + .STATIC_PHASE6 (STATIC_PHASE6 ), + + .STATIC_PHASEF (STATIC_PHASEF ), + + .STATIC_CPHASE0 (STATIC_CPHASE0), + .STATIC_CPHASE1 (STATIC_CPHASE1), + .STATIC_CPHASE2 (STATIC_CPHASE2), + .STATIC_CPHASE3 (STATIC_CPHASE3), + .STATIC_CPHASE4 (STATIC_CPHASE4), + + .STATIC_CPHASE5 (STATIC_CPHASE5), + .STATIC_CPHASE6 (STATIC_CPHASE6), + + .STATIC_CPHASEF (STATIC_CPHASEF), + + .CLK_DPS0_EN (CLK_DPS0_EN ), + .CLK_DPS1_EN (CLK_DPS1_EN ), + .CLK_DPS2_EN (CLK_DPS2_EN ), + .CLK_DPS3_EN (CLK_DPS3_EN ), + .CLK_DPS4_EN (CLK_DPS4_EN ), + .CLK_DPS5_EN (CLK_DPS5_EN ), + .CLK_DPS6_EN (CLK_DPS6_EN ), + .CLK_DPSF_EN (CLK_DPSF_EN ), + .CLK_CAS5_EN (CLK_CAS5_EN ), + + .CLKOUT0_SYN_EN (CLKOUT0_SYN_EN), + .CLKOUT1_SYN_EN (CLKOUT1_SYN_EN), + .CLKOUT2_SYN_EN (CLKOUT2_SYN_EN), + .CLKOUT3_SYN_EN (CLKOUT3_SYN_EN), + .CLKOUT4_SYN_EN (CLKOUT4_SYN_EN), + + .CLKOUT5_SYN_EN (CLKOUT5_SYN_EN), + .CLKOUT6_SYN_EN (CLKOUT6_SYN_EN), + + .CLKOUTF_SYN_EN (CLKOUTF_SYN_EN), + + .SSC_MODE (SSC_MODE ), + .SSC_FREQ (SSC_FREQ ), + + .INTERNAL_FB (INTERNAL_FB ), + .EXTERNAL_FB (EXTERNAL_FB ), + + .BANDWIDTH (BANDWIDTH ) + + ) u_gpll ( + + .CLKOUT0 (clkout0 ), + + .CLKOUT0N ( ), + + .CLKOUT1 (clkout1 ), + + .CLKOUT1N ( ), + + .CLKOUT2 (clkout2 ), + + .CLKOUT2N ( ), + + .CLKOUT3 ( ), + + .CLKOUT3N ( ), + + .CLKOUT4 ( ), + + .CLKOUT5 ( ), - .DYNAMIC_RATIO0_EN(DYNAMIC_RATIO0_EN), - .DYNAMIC_RATIO1_EN(DYNAMIC_RATIO1_EN), - .DYNAMIC_RATIO2_EN(DYNAMIC_RATIO2_EN), - .DYNAMIC_RATIO3_EN(DYNAMIC_RATIO3_EN), - .DYNAMIC_RATIO4_EN(DYNAMIC_RATIO4_EN), - .DYNAMIC_RATIOF_EN(DYNAMIC_RATIOF_EN), - .STATIC_RATIOI(STATIC_RATIOI), + .CLKOUT6 ( ), - .STATIC_RATIO0(STATIC_RATIO0), - .STATIC_RATIO1(STATIC_RATIO1), - .STATIC_RATIO2(STATIC_RATIO2), - .STATIC_RATIO3(STATIC_RATIO3), - .STATIC_RATIO4(STATIC_RATIO4), - .STATIC_RATIOF(STATIC_RATIOF), - .DYNAMIC_DUTY0_EN(DYNAMIC_DUTY0_EN), - .DYNAMIC_DUTY1_EN(DYNAMIC_DUTY1_EN), - .DYNAMIC_DUTY2_EN(DYNAMIC_DUTY2_EN), - .DYNAMIC_DUTY3_EN(DYNAMIC_DUTY3_EN), - .DYNAMIC_DUTY4_EN(DYNAMIC_DUTY4_EN), - .DYNAMIC_DUTYF_EN(DYNAMIC_DUTYF_EN), - .STATIC_DUTY0(STATIC_DUTY0), - .STATIC_DUTY1(STATIC_DUTY1), - .STATIC_DUTY2(STATIC_DUTY2), - .STATIC_DUTY3(STATIC_DUTY3), - .STATIC_DUTY4(STATIC_DUTY4), - .STATIC_DUTYF(STATIC_DUTYF), - .PHASE_ADJUST0_EN(PHASE_ADJUST0_EN), - .PHASE_ADJUST1_EN(PHASE_ADJUST1_EN), - .PHASE_ADJUST2_EN(PHASE_ADJUST2_EN), - .PHASE_ADJUST3_EN(PHASE_ADJUST3_EN), - .PHASE_ADJUST4_EN(PHASE_ADJUST4_EN), - .DYNAMIC_PHASE0_EN(DYNAMIC_PHASE0_EN), - .DYNAMIC_PHASE1_EN(DYNAMIC_PHASE1_EN), - .DYNAMIC_PHASE2_EN(DYNAMIC_PHASE2_EN), - .DYNAMIC_PHASE3_EN(DYNAMIC_PHASE3_EN), - .DYNAMIC_PHASE4_EN(DYNAMIC_PHASE4_EN), - .DYNAMIC_PHASEF_EN(DYNAMIC_PHASEF_EN), - .STATIC_PHASE0(STATIC_PHASE0[2:0]), - .STATIC_PHASE1(STATIC_PHASE1[2:0]), - .STATIC_PHASE2(STATIC_PHASE2[2:0]), - .STATIC_PHASE3(STATIC_PHASE3[2:0]), - .STATIC_PHASE4(STATIC_PHASE4[2:0]), - .STATIC_PHASEF(STATIC_PHASEF[2:0]), - .STATIC_CPHASE0(STATIC_PHASE0[12:3]), - .STATIC_CPHASE1(STATIC_PHASE1[12:3]), - .STATIC_CPHASE2(STATIC_PHASE2[12:3]), - .STATIC_CPHASE3(STATIC_PHASE3[12:3]), - .STATIC_CPHASE4(STATIC_PHASE4[12:3]), - .STATIC_CPHASEF(STATIC_PHASEF[12:3]), - .CLK_CAS0_EN(CLK_CAS0_EN), - .CLK_CAS1_EN(CLK_CAS1_EN), - .CLK_CAS2_EN(CLK_CAS2_EN), - .CLK_CAS3_EN(CLK_CAS3_EN), - .CLK_CAS4_EN(CLK_CAS4_EN), - .CLKOUT5_SEL(CLKOUT5_SEL), - .CLKIN_BYPASS_EN(CLKIN_BYPASS_EN), - .CLKOUT0_SYN_EN(CLKOUT0_GATE_EN), - .CLKOUT0_EXT_SYN_EN(CLKOUT0_EXT_GATE_EN), - .CLKOUT1_SYN_EN(CLKOUT1_GATE_EN), - .CLKOUT2_SYN_EN(CLKOUT2_GATE_EN), - .CLKOUT3_SYN_EN(CLKOUT3_GATE_EN), - .CLKOUT4_SYN_EN(CLKOUT4_GATE_EN), - .CLKOUT5_SYN_EN(CLKOUT5_GATE_EN), - .INTERNAL_FB(INTERNAL_FB), - .EXTERNAL_FB(EXTERNAL_FB), - .RSTODIV_PHASE_EN(RSTODIV_ENABLE), - .SIM_DEVICE(SIM_DEVICE), - .BANDWIDTH(BANDWIDTH) - ) u_pll_e1 ( - .CLKOUT0(clkout0), - .CLKOUT0_EXT(clkout0_2pad), - .CLKOUT1(clkout1), - .CLKOUT2(clkout2), - .CLKOUT3(clkout3), - .CLKOUT4(clkout4), - .CLKOUT5(clkout5), - .CLKSWITCH_FLAG(clkswitch_flag), - .LOCK(pll_lock), - .CLKIN1(clkin1), - .CLKIN2(clkin2), - .CLKFB(clkfb), - .CLKIN_SEL(clkin_sel), - .CLKIN_SEL_EN(clkin_sel_en), - .PFDEN(pfden), + .CLKOUTF ( ), + + .CLKOUTFN ( ), + + .LOCK (lock ), + + .DPS_DONE ( ), - .RATIOI(dyn_idiv), - .RATIO0(dyn_odiv0), - .RATIO1(dyn_odiv1), - .RATIO2(dyn_odiv2), - .RATIO3(dyn_odiv3), - .RATIO4(dyn_odiv4), - .RATIOF(dyn_fdiv), - .DUTY0(dyn_duty0), - .DUTY1(dyn_duty1), - .DUTY2(dyn_duty2), - .DUTY3(dyn_duty3), - .DUTY4(dyn_duty4), - .DUTYF(), - .PHASE0(dyn_phase0[2:0]), - .PHASE1(dyn_phase1[2:0]), - .PHASE2(dyn_phase2[2:0]), - .PHASE3(dyn_phase3[2:0]), - .PHASE4(dyn_phase4[2:0]), - .PHASEF(), - .CPHASE0(dyn_phase0[12:3]), - .CPHASE1(dyn_phase1[12:3]), - .CPHASE2(dyn_phase2[12:3]), - .CPHASE3(dyn_phase3[12:3]), - .CPHASE4(dyn_phase4[12:3]), - .CPHASEF(), - .CLKOUT0_SYN(clkout0_gate), - .CLKOUT0_EXT_SYN(clkout0_2pad_gate), - .CLKOUT1_SYN(clkout1_gate), - .CLKOUT2_SYN(clkout2_gate), - .CLKOUT3_SYN(clkout3_gate), - .CLKOUT4_SYN(clkout4_gate), - .CLKOUT5_SYN(clkout5_gate), - .PLL_PWD(pll_pwd), - .RST(pll_rst), - .RSTODIV_PHASE(rstodiv) - ); + .DPS_CLK (dps_clk ), + .DPS_EN (dps_en ), + .DPS_DIR (dps_dir ), + .CLKIN1 (clkin1 ), + + .CLKIN2 (clkin2 ), + + .CLKFB (clkfb ), + .CLKIN_SEL (clkin_sel ), + .CLKOUT0_SYN (clkout0_syn ), + .CLKOUT1_SYN (clkout1_syn ), + .CLKOUT2_SYN (clkout2_syn ), + .CLKOUT3_SYN (clkout3_syn ), + .CLKOUT4_SYN (clkout4_syn ), + + .CLKOUT5_SYN (clkout5_syn ), + .CLKOUT6_SYN (clkout6_syn ), + + .CLKOUTF_SYN (clkoutf_syn ), + .PLL_PWD (pll_pwd ), + .RST (rst ), + + .APB_RDATA ( ), + .APB_READY ( ), + + .APB_CLK (apb_clk ), + .APB_RST_N (apb_rst_n ), + .APB_ADDR (apb_addr[4:0] ), + .APB_SEL (apb_sel ), + .APB_EN (apb_en ), + .APB_WRITE (apb_write ), + .APB_WDATA (apb_wdata[15:0]) +); + + endmodule diff --git a/ipcore/SPLL/SPLL_tb.v b/ipcore/SPLL/SPLL_tb.v index 60dd5fe..a69c74e 100644 --- a/ipcore/SPLL/SPLL_tb.v +++ b/ipcore/SPLL/SPLL_tb.v @@ -1,7 +1,7 @@ // Created by IP Generator (Version 2021.1-SP7 build 86875) - + ////////////////////////////////////////////////////////////////////////////// // // Copyright (c) 2019 PANGO MICROSYSTEMS, INC @@ -16,239 +16,202 @@ // Library: // Filename:SPLL.v ////////////////////////////////////////////////////////////////////////////// -`timescale 1 ns/1 ps +`timescale 1ns/10fs module SPLL_tb (); -localparam CLKIN_FREQ = 50.0; -localparam integer FBDIV_SEL = 0; -localparam FBMODE = "FALSE"; - - -// Generate testbench reset and clock -reg pll_rst; -reg rstodiv; -reg pll_pwd; -reg clkin1; -reg clkin2; -reg clkin_dsel; -reg clkin_dsel_en; -reg pfden; -reg clkout0_gate; -reg clkout0_2pad_gate; -reg clkout1_gate; -reg clkout2_gate; -reg clkout3_gate; -reg clkout4_gate; -reg clkout5_gate; -reg [9:0] dyn_idiv; -reg [9:0] dyn_odiv0; -reg [9:0] dyn_odiv1; -reg [9:0] dyn_odiv2; -reg [9:0] dyn_odiv3; -reg [9:0] dyn_odiv4; -reg [9:0] dyn_fdiv; -reg [9:0] dyn_duty0; -reg [9:0] dyn_duty1; -reg [9:0] dyn_duty2; -reg [9:0] dyn_duty3; -reg [9:0] dyn_duty4; -reg [12:0] dyn_phase0; -reg [12:0] dyn_phase1; -reg [12:0] dyn_phase2; -reg [12:0] dyn_phase3; -reg [12:0] dyn_phase4; -reg err_chk; -reg [2:0] results_cnt; - -reg rst_n; -reg clk_tb; - -wire clkout0; -wire clkout1; -wire clkout2; -wire clkout3; -wire clkout4; -wire clkfb = (FBMODE == "FALSE") ? clkin1 : - (FBDIV_SEL == 0 ) ? clkout0 : - (FBDIV_SEL == 1 ) ? clkout1 : - (FBDIV_SEL == 2 ) ? clkout2 : - (FBDIV_SEL == 3 ) ? clkout3 : - (FBDIV_SEL == 4 ) ? clkout4 : clkin1; - -initial -begin - rst_n = 0; - #20 - rst_n = 1; -end - -initial -begin - clk_tb = 0; - forever #1 clk_tb = ~clk_tb; -end - -parameter CLOCK_PERIOD1 = (500.0/CLKIN_FREQ); -//parameter CLOCK_PERIOD2 = (500.0/CLKIN_FREQ); - -initial -begin - clkin1 = 0; - forever #(CLOCK_PERIOD1) clkin1 = ~clkin1; -end - - -initial -begin - pll_pwd = 0; - pll_rst = 0; - rstodiv = 0; - clkin_dsel = 0; - clkin_dsel_en = 0; - pfden = 0; - clkout0_gate = 0; - clkout0_2pad_gate = 0; - clkout1_gate = 0; - clkout2_gate = 0; - clkout3_gate = 0; - clkout4_gate = 0; - clkout5_gate = 0; - dyn_idiv = 10'd2; - dyn_fdiv = 10'd32; - dyn_odiv0 = 10'd100; - dyn_odiv1 = 10'd100; - dyn_odiv2 = 10'd100; - dyn_odiv3 = 10'd100; - dyn_odiv4 = 10'd100; - dyn_duty0 = 10'd100; - dyn_duty1 = 10'd100; - dyn_duty2 = 10'd100; - dyn_duty3 = 10'd100; - dyn_duty4 = 10'd100; - dyn_phase0 = 13'd16; - dyn_phase1 = 13'd16; - dyn_phase2 = 13'd16; - dyn_phase3 = 13'd16; - dyn_phase4 = 13'd16; - - #10 - pll_pwd = 1; - #20 - pll_pwd = 0; - - pll_rst = 0; - #10 - pll_rst = 1; - #20 - pll_rst = 0; - - #1000000 - dyn_odiv0 = 10'd200; - dyn_odiv1 = 10'd200; - dyn_odiv2 = 10'd200; - dyn_odiv3 = 10'd200; - dyn_odiv4 = 10'd200; - dyn_duty0 = 10'd200; - dyn_duty1 = 10'd200; - dyn_duty2 = 10'd200; - dyn_duty3 = 10'd200; - dyn_duty4 = 10'd200; - #3000000 - $finish; -end - -initial -begin - $display("Simulation Starts.") ; - $display("Simulation is done.") ; - if (|results_cnt) - $display("Simulation Failed due to Error Found.") ; - else - $display("Simulation Success.") ; -end - - -GTP_GRS GRS_INST( - .GRS_N(1'b1) - ); - -SPLL U_SPLL ( -.clkout0(clkout0), - .clkout1(clkout1), - .clkout2(clkout2), + localparam real CLKIN_FREQ = 50.0; //@IPC float 10.0,500.0 - .clkin1(clkin1), + localparam INTERNAL_FB = "CLKOUTF"; - .pll_lock(pll_lock) - ); - - -//******************Results Cheching************************ - -reg [2:0] pll_lock_shift; -wire pll_lock_pulse = ~pll_lock_shift[2] & pll_lock_shift[1]; -always @( posedge clk_tb or negedge rst_n ) -begin - if (!rst_n) + localparam EXTERNAL_FB = "DISABLE"; + + + wire clkout0 ; + wire clkout0_n ; + wire clkout1 ; + wire clkout1_n ; + wire clkout2 ; + wire clkout2_n ; + wire clkout3 ; + wire clkout3_n ; + wire clkout4 ; + wire clkout5 ; + wire clkout6 ; + wire clkoutf ; + wire clkoutf_n ; + wire clkoutphy ; + wire clkoutphy_n ; + wire clkfb = (EXTERNAL_FB == "DISABLE") ? 1'b0 : + (EXTERNAL_FB == "CLKOUT0") ? clkout0 : + (EXTERNAL_FB == "CLKOUT1") ? clkout1 : + (EXTERNAL_FB == "CLKOUT2") ? clkout2 : + (EXTERNAL_FB == "CLKOUT3") ? clkout3 : + (EXTERNAL_FB == "CLKOUT4") ? clkout4 : + (EXTERNAL_FB == "CLKOUT5") ? clkout5 : + (EXTERNAL_FB == "CLKOUT6") ? clkout6 : + (EXTERNAL_FB == "CLKOUTF") ? clkoutf : 1'b0; + wire lock ; + wire dps_done ; + wire [15:0] apb_rdata ; + wire apb_ready ; + wire clkin1_p ; + wire clkin1_n ; + wire clkin2_p ; + wire clkin2_n ; + + reg clkin1 ; + reg clkin2 ; + reg clkin_sel ; + reg dps_clk ; + reg dps_en ; + reg dps_dir ; + reg clkout0_syn ; + reg clkout1_syn ; + reg clkout2_syn ; + reg clkout3_syn ; + reg clkout4_syn ; + reg clkout5_syn ; + reg clkout6_syn ; + reg clkoutf_syn ; + reg clkoutphy_syn ; + reg clkout0_bufce ; + reg clkout1_bufce ; + reg clkout2_bufce ; + reg clkout3_bufce ; + reg clkout4_bufce ; + reg clkout5_bufce ; + reg clkout6_bufce ; + reg clkoutf_bufce ; + reg pll_pwd ; + reg rst ; + reg apb_clk ; + reg apb_rst_n ; + reg [4:0] apb_addr ; + reg apb_sel ; + reg apb_en ; + reg apb_write ; + reg [15:0] apb_wdata ; + + assign clkin1_p = clkin1 ; + assign clkin1_n = ~clkin1; + assign clkin2_p = clkin2 ; + assign clkin2_n = ~clkin2; + + initial begin - pll_lock_shift <= 3'd0; + clkin_sel = 1'b0; + dps_clk = 1'b0; + dps_en = 1'b0; + dps_dir = 1'b0; + clkout0_syn = 1'b0; + clkout1_syn = 1'b0; + clkout2_syn = 1'b0; + clkout3_syn = 1'b0; + clkout4_syn = 1'b0; + clkout5_syn = 1'b0; + clkout6_syn = 1'b0; + clkoutf_syn = 1'b0; + clkoutphy_syn = 1'b0; + clkout0_bufce = 1'b1; + clkout1_bufce = 1'b1; + clkout2_bufce = 1'b1; + clkout3_bufce = 1'b1; + clkout4_bufce = 1'b1; + clkout5_bufce = 1'b1; + clkout6_bufce = 1'b1; + clkoutf_bufce = 1'b1; + pll_pwd = 1'b0; + apb_clk = 1'b0; + apb_rst_n = 1'b0; + apb_addr = 5'b0; + apb_sel = 1'b0; + apb_en = 1'b0; + apb_write = 1'b0; + apb_wdata = 16'b0; end - else + + // clkin1 generation + initial begin - pll_lock_shift[0] <= pll_lock; - pll_lock_shift[2:1] <= pll_lock_shift[1:0]; + clkin1 = 0; + forever #(500/CLKIN_FREQ) clkin1 = ~clkin1; end -end - -reg [1:0] pll_lock_pulse_cnt; -always @( posedge clk_tb or negedge rst_n ) -begin - if (!rst_n) + + // clkin2 generation + initial begin - pll_lock_pulse_cnt <= 2'd0; + clkin2 = 1; + forever #(500/CLKIN_FREQ) clkin2 = ~clkin2; end - else + + // reset and power down generation + initial begin - if (pll_lock_pulse) - pll_lock_pulse_cnt <= pll_lock_pulse_cnt + 1; - else ; + pll_pwd = 1'b1; + rst = 1'b1; + #50 + pll_pwd = 1'b0; + #50 + rst = 1'b0; end -end +SPLL U_SPLL( + + .clkout0 (clkout0 ), + + .clkout1 (clkout1 ), + + .clkout2 (clkout2 ), + + .clkin1 (clkin1 ), + + .lock (lock ) + ); + + -always @( posedge clk_tb or negedge rst_n ) -begin - if (!rst_n) +//******************Results Cheching************************ + reg lock_ff1 = 1'b0; + reg lock_ff2 = 1'b0; + reg lock_ff3 = 1'b0; + reg lock_neg = 1'b0; + wire chk_ok; + + + always @( posedge clkin1) begin - err_chk <= 1'b0; + lock_ff1 <= lock; + lock_ff2 <= lock_ff1; + lock_ff3 <= lock_ff2; end - else + + always @( posedge clkin1) begin - if ((!pll_lock) && (^pll_lock_pulse_cnt)) - err_chk <= 1'b1; - else if (pll_lock_pulse_cnt[1]) - err_chk <= 1'b1; - else - err_chk <= 1'b0; + if(rst==1'b1) + lock_neg <= 1'b0; + else if((lock_ff2==1'b0)&&(lock_ff3==1'b1)) + lock_neg <= 1'b1; + else ; + end + assign chk_ok = lock_ff3 & (~lock_neg); + + + + + integer handle; + initial begin + #50000 + handle = $fopen ("sim_results.log","a"); + $fdisplay(handle,"chk_ok = %b, $realtime = %-10d",chk_ok,$realtime ); + $display("Simulation Starts.") ; + $display("Simulation is done.") ; + if (chk_ok==1'b0) + $display("Simulation Failed due to Error Found.") ; + else + $display("Simulation Success.") ; + $finish; end -end -always @(posedge clk_tb or negedge rst_n) -begin - if (!rst_n) - results_cnt <= 3'b000 ; - else if (&results_cnt) - results_cnt <= 3'b100 ; - else if (err_chk) - results_cnt <= results_cnt + 3'd1 ; -end - - -integer result_fid; -initial begin - result_fid = $fopen ("sim_results.log","a"); - $fmonitor(result_fid,"err_chk=%b", err_chk); -end endmodule diff --git a/ipcore/SPLL/SPLL_tmpl.v b/ipcore/SPLL/SPLL_tmpl.v index 0d0a436..5fcf6e0 100644 --- a/ipcore/SPLL/SPLL_tmpl.v +++ b/ipcore/SPLL/SPLL_tmpl.v @@ -7,9 +7,9 @@ SPLL the_instance_name ( - .clkin1(clkin1), // input - .pll_lock(pll_lock), // output - .clkout0(clkout0), // output - .clkout1(clkout1), // output - .clkout2(clkout2) // output + .clkout0(clkout0), // output + .clkout1(clkout1), // output + .clkout2(clkout2), // output + .lock(lock), // output + .clkin1(clkin1) // input ); diff --git a/ipcore/SPLL/SPLL_tmpl.vhdl b/ipcore/SPLL/SPLL_tmpl.vhdl index c75c06f..56fe060 100644 --- a/ipcore/SPLL/SPLL_tmpl.vhdl +++ b/ipcore/SPLL/SPLL_tmpl.vhdl @@ -8,20 +8,20 @@ COMPONENT SPLL PORT ( - clkin1 : IN STD_LOGIC; - pll_lock : OUT STD_LOGIC; clkout0 : OUT STD_LOGIC; clkout1 : OUT STD_LOGIC; - clkout2 : OUT STD_LOGIC + clkout2 : OUT STD_LOGIC; + lock : OUT STD_LOGIC; + clkin1 : IN STD_LOGIC ); END COMPONENT; the_instance_name : SPLL PORT MAP ( - clkin1 => clkin1, - pll_lock => pll_lock, clkout0 => clkout0, clkout1 => clkout1, - clkout2 => clkout2 + clkout2 => clkout2, + lock => lock, + clkin1 => clkin1 ); diff --git a/ipcore/SPLL/generate.log b/ipcore/SPLL/generate.log index 2fb1a16..8dabeda 100644 --- a/ipcore/SPLL/generate.log +++ b/ipcore/SPLL/generate.log @@ -1,15 +1,15 @@ IP Generator (Version 2021.1-SP7 build 86875) Check out license ... -Start generating at 2024-01-11 09:39 -Instance: SPLL (D:\workspace\fpga_demo\xsync\ipcore\SPLL\SPLL.idf) -IP: PLL (1.5) -Part: Logos-PGL22G-MBG324--6 +Start generating at 2024-08-23 14:44 +Instance: SPLL (D:\workspace\p_lusterinc_xsync\xsync_fpge_v2\ipcore\SPLL\SPLL.idf) +IP: PLL (1.2) +Part: Logos2-PG2L100H-FBG484--6 Create directory 'rtl' ... -Copy 'ipml_pll_wrapper_v1_4.v.xml' ... -Compile file 'ipml_pll_wrapper_v1_4.v.xml' to 'SPLL.v' ... +Copy 'ipm2l_pll_wrapper_v1_1.v.xml' ... +Compile file 'ipm2l_pll_wrapper_v1_1.v.xml' to 'SPLL.v' ... Found top module 'SPLL' in file 'SPLL.v'. -Copy 'ipml_pll_wrapper_v1_4_tb.v.xml' ... -Compile file 'ipml_pll_wrapper_v1_4_tb.v.xml' to 'SPLL_tb.v' ... +Copy 'ipm2l_pll_wrapper_v1_1_tb.v.xml' ... +Compile file 'ipm2l_pll_wrapper_v1_1_tb.v.xml' to 'SPLL_tb.v' ... Create template file 'SPLL_tmpl.v' ... Create template file 'SPLL_tmpl.vhdl' ... There is 1 source file to synthesize. diff --git a/pango_tools/fdc_generator.cpp b/pango_tools/fdc_generator.cpp index 589f01c..b0a575f 100644 --- a/pango_tools/fdc_generator.cpp +++ b/pango_tools/fdc_generator.cpp @@ -57,7 +57,12 @@ int _main() { string pin = zcsv->getdata(i + 1, 1); string name = zcsv->getdata(i + 1, 2); string direction = zcsv->getdata(i + 1, 3); - if(pins.find(pin) != pins.end()){ + if (pin.empty() || pin == "N/A") { + ZLOGI(TAG, "line %d pin name is empty, skip", i + 1); + continue; + } + + if (pins.find(pin) != pins.end()) { ZLOGE(TAG, "parse pin.csv fail, pin repeat, line num:%d,%s", i + 1, pin.c_str()); return -1; } diff --git a/pin.csv b/pin.csv index 08dc557..007cfbb 100644 --- a/pin.csv +++ b/pin.csv @@ -1,46 +1,71 @@ xsync.fdc,, -B5,ex_clk,INPUT -P17,spi_cs_pin ,INPUT -L12,spi_clk_pin,INPUT -R17,spi_tx_pin,OUTPUT -R18,spi_rx_pin,INPUT -L17,uart_tx,OUTPUT -L18,uart_rx,INPUT -T11,core_board_debug_led,OUTPUT -M18,stm32_output_bus[0],OUTPUT -K18,stm32_output_bus[1],OUTPUT -K17,stm32_output_bus[2],OUTPUT -H18,stm32_output_bus[3],OUTPUT -H17,stm32_output_bus[4],OUTPUT -G18,stm32_output_bus[5],OUTPUT -G17,stm32_output_bus[6],OUTPUT -F18,stm32_output_bus[7],OUTPUT -F17,stm32_input_bus[0],INPUT -G16,stm32_input_bus[1],INPUT -F16,stm32_input_bus[2],INPUT -H16,stm32_input_bus[3],INPUT -J16,stm32_input_bus[4],INPUT -C17,stm32_input_bus[5],INPUT -C18,stm32_input_bus[6],INPUT -A18,stm32_input_bus[7],INPUT -J15,debug_bus[0],OUTPUT -J14,debug_bus[1],OUTPUT -F14,debug_bus[2],OUTPUT -F13,debug_bus[3],OUTPUT -G14,debug_bus[4],OUTPUT -G13,debug_bus[5],OUTPUT -H14,debug_bus[6],OUTPUT -H13,debug_bus[7],OUTPUT -E17,debug_bus[8],OUTPUT -E18,debug_bus[9],OUTPUT -D18,debug_bus[10],OUTPUT -D17,debug_bus[11],OUTPUT -A16,debug_bus[12],OUTPUT -B16,debug_bus[13],OUTPUT -A15,debug_bus[14],OUTPUT -B15,debug_bus[15],OUTPUT -N18,out1,OUTPUT -L15,extOutputEn1,OUTPUT -L14,extOutputEn2,OUTPUT -M16,triSig,INPUT - +R4,ex_clk,INPUT +U7,ex_rst_n,INPUT +M15,genlock_in_hsync,INPUT +M16,genlock_in_vsync,INPUT +L16,genlock_in_fsync,INPUT +N/A,genlock_in_state_led,OUTPUT +E14,genlock_out_dac[0],OUTPUT +E13,genlock_out_dac[1],OUTPUT +F14,genlock_out_dac[2],OUTPUT +F13,genlock_out_dac[3],OUTPUT +C22,genlock_out_dac[4],OUTPUT +B22,genlock_out_dac[5],OUTPUT +C20,genlock_out_dac[6],OUTPUT +D20,genlock_out_dac[7],OUTPUT +C19,genlock_out_dac[8],OUTPUT +C18,genlock_out_dac_clk,OUTPUT +,genlock_out_dac_state_led,OUTPUT +K18,sync_ttl_in1,INPUT +,sync_ttl_in1_state_led,OUTPUT +K19,sync_ttl_in2,INPUT +,sync_ttl_in2_state_led,OUTPUT +M13,sync_ttl_in3,INPUT +,sync_ttl_in3_state_led,OUTPUT +L13,sync_ttl_in4,INPUT +,sync_ttl_in4_state_led,OUTPUT +AA8,sync_ttl_out1,OUTPUT +,sync_ttl_out1_state_led,OUTPUT +V9,sync_ttl_out2,OUTPUT +,sync_ttl_out2_state_led,OUTPUT +V8,sync_ttl_out3,OUTPUT +,sync_ttl_out3_state_led,OUTPUT +T6,sync_ttl_out4,OUTPUT +,sync_ttl_out4_state_led,OUTPUT +L15,timecode_headphone_in,INPUT +,timecode_headphone_in_state_led,OUTPUT +L14,timecode_bnc_in,INPUT +,timecode_bnc_in_state_led,OUTPUT +W9,timecode_out_bnc,OUTPUT +R6,timecode_out_bnc_select,OUTPUT +,timecode_out_bnc_state_led,OUTPUT +Y9,timecode_out_headphone,OUTPUT +T3,timecode_out_headphone_select,OUTPUT +,timecode_out_headphone_state_led,OUTPUT +Y21,stm32if_start_signal_out,OUTPUT +Y22,stm32if_camera_sync_out,OUTPUT +AB20,stm32if_timecode_sync_out,OUTPUT +W7,spi1_cs_pin,INPUT +V7,spi1_clk_pin,INPUT +Y7,spi1_rx_pin,INPUT +Y8,spi1_tx_pin,OUTPUT +Y11,debug_signal_output[0],OUTPUT +Y12,debug_signal_output[1],OUTPUT +AA10,debug_signal_output[2],OUTPUT +AA11,debug_signal_output[3],OUTPUT +AB11,debug_signal_output[4],OUTPUT +AB12,debug_signal_output[5],OUTPUT +W11,debug_signal_output[6],OUTPUT +W12,debug_signal_output[7],OUTPUT +AA13,debug_signal_output[8],OUTPUT +AB13,debug_signal_output[9],OUTPUT +Y13,debug_signal_output[10],OUTPUT +AA14,debug_signal_output[11],OUTPUT +AA15,debug_signal_output[12],OUTPUT +AB15,debug_signal_output[13],OUTPUT +Y16,debug_signal_output[14],OUTPUT +AA16,debug_signal_output[15],OUTPUT +W5,core_board_debug_led,OUTPUT +N/A,debug_signal_output[14] ,OUTPUT +N/A,debug_signal_output[15] ,OUTPUT +W5,core_board_debug_led,OUTPUT diff --git a/source/src/top.v b/source/src/top.v index 2c18fa1..fa72dab 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -62,12 +62,6 @@ module Top ( input wire spi1_rx_pin, output wire spi1_tx_pin, - //SPI 串行总线2 - input wire spi2_cs_pin, - input wire spi2_clk_pin, - input wire spi2_rx_pin, - output wire spi2_tx_pin, - output [15:0] debug_signal_output, @@ -181,7 +175,7 @@ module Top ( //系统时钟源 SPLL spll ( .clkin1 (ex_clk), - .pll_lock(pll_lock), + .lock(pll_lock), .clkout0 (sys_clk_25m), .clkout1 (sys_clk_10m), .clkout2 (sys_clk_5m) @@ -195,10 +189,10 @@ module Top ( .addr (RegReaderBus_addr), .wr_data (RegReaderBus_wr_data), .wr_en (RegReaderBus_wr_en), - .spi_cs_pin (spi2_cs_pin), - .spi_clk_pin(spi2_clk_pin), - .spi_rx_pin (spi2_rx_pin), - .spi_tx_pin (spi2_tx_pin), + .spi_cs_pin (spi1_cs_pin), + .spi_clk_pin(spi1_clk_pin), + .spi_rx_pin (spi1_rx_pin), + .spi_tx_pin (spi1_tx_pin), .rd_data_module_fpga_info (rd_data_module_fpga_info), .rd_data_module_ttlin (rd_data_module_ttlin), @@ -639,8 +633,6 @@ module Top ( .ttloutput_state_led(sync_ttl_out2_state_led) ); -/* - ttl_output #( .REG_START_ADD(`REGADDOFF__TTLOUT3), .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), @@ -659,7 +651,6 @@ module Top ( .ttloutput (before_delay__sync_ttl_out3), .ttloutput_state_led(sync_ttl_out3_state_led) ); -*/ ttl_output #( .REG_START_ADD(`REGADDOFF__TTLOUT4), diff --git a/source/src/zutils/zutils_sig_delayer_v2.v b/source/src/zutils/zutils_sig_delayer_v2.v index 04ba89f..8aa3915 100644 --- a/source/src/zutils/zutils_sig_delayer_v2.v +++ b/source/src/zutils/zutils_sig_delayer_v2.v @@ -5,7 +5,7 @@ // 2. 相比使用FIFO的方式缓存信号的方式,这个延时模块使用的资源更少。 // 3. 无法延迟非周期短时高频信号。最多缓存3个短时脉冲(缓存脉冲数量与zutils_edge_detecter的实力数量有关) // -/* +// /* module zutils_sig_delayer_v2 ( input clk, input rst_n, @@ -123,9 +123,9 @@ module zutils_sig_delayer_v2 ( endmodule -*/ +// */ -// /* +/* module zutils_sig_delayer_v2 ( input clk, input rst_n, @@ -140,4 +140,4 @@ module zutils_sig_delayer_v2 ( assign out = in; endmodule -// */ +*/ diff --git a/xsync.fdc b/xsync.fdc index d0f23bb..2c8d66b 100644 --- a/xsync.fdc +++ b/xsync.fdc @@ -1,581 +1,290 @@ -# debug_signal_output[0] output M18 -# debug_signal_output[1] output K18 -# debug_signal_output[2] output K17 -# debug_signal_output[3] output H18 -# debug_signal_output[4] output H17 -# debug_signal_output[5] output G18 -# debug_signal_output[6] output G17 -# debug_signal_output[7] output F18 -# debug_signal_output[8] output F17 -# debug_signal_output[9] output G16 -# debug_signal_output[10] output F16 -# debug_signal_output[11] output H16 -# debug_signal_output[12] output J16 -# debug_signal_output[13] output C17 -# debug_signal_output[14] output C18 -# debug_signal_output[15] output A18 -# genlock_out_dac[0] OUTPUT A16 -# genlock_out_dac[1] OUTPUT B16 -# genlock_out_dac[2] OUTPUT A15 -# genlock_out_dac[3] OUTPUT B15 -# genlock_out_dac[4] OUTPUT A14 -# genlock_out_dac[5] OUTPUT B14 -# genlock_out_dac[6] OUTPUT A12 -# genlock_out_dac[7] OUTPUT B12 -# genlock_out_dac[8] OUTPUT A11 -# genlock_out_dac[9] OUTPUT B11 -# genlock_out_dac_clk OUTPUT H13 -# genlock_out_dac_state_led OUTPUT D17 -# stm32if_camera_sync_out OUTPUT C10 -# stm32if_start_signal_out OUTPUT F12 -# stm32if_timecode_sync_out OUTPUT G12 -# stm32if_timecode_add[0] OUTPUT D13 -# stm32if_timecode_add[1] OUTPUT D15 -# stm32if_timecode_add[2] OUTPUT C15 -# stm32if_timecode_add[3] OUTPUT E15 -# stm32if_timecode_data[0] OUTPUT E16 -# stm32if_timecode_data[1] OUTPUT A17 -# stm32if_timecode_data[2] OUTPUT B17 -# stm32if_timecode_data[3] OUTPUT B18 -# spi2_cs_pin INPUT V14 -# spi2_clk_pin INPUT V13 -# spi2_rx_pin INPUT U14 -# spi2_tx_pin OUTPUT U13 -# spi1_cs_pin INPUT P17 -# spi1_clk_pin INPUT L12 -# spi1_rx_pin INPUT R18 -# spi1_tx_pin OUTPUT R17 -# sync_ttl_in1 INPUT R11 -# sync_ttl_in1_state_led OUTPUT U10 -# sync_ttl_in2 INPUT P11 -# sync_ttl_in2_state_led OUTPUT V10 -# sync_ttl_in3 INPUT R13 -# sync_ttl_in3_state_led OUTPUT U11 -# sync_ttl_in4 INPUT R14 -# sync_ttl_in4_state_led OUTPUT U12 -# sync_ttl_out1 OUTPUT V17 -# sync_ttl_out1_state_led OUTPUT L18 -# sync_ttl_out2 OUTPUT T17 -# sync_ttl_out2_state_led OUTPUT L17 -# sync_ttl_out3 OUTPUT U17 -# sync_ttl_out3_state_led OUTPUT N16 -# sync_ttl_out4 OUTPUT M13 -# sync_ttl_out4_state_led OUTPUT N15 -# genlock_in_hsync INPUT U16 -# genlock_in_vsync INPUT V16 -# genlock_in_fsync INPUT T16 -# genlock_in_state_led OUTPUT N14 -# timecode_out_bnc OUTPUT L15 -# timecode_out_bnc_select OUTPUT A10 -# timecode_out_bnc_state_led OUTPUT E17 -# timecode_out_headphone OUTPUT N18 -# timecode_out_headphone_select OUTPUT B10 -# timecode_out_headphone_state_led OUTPUT E18 -# timecode_headphone_in INPUT R16 -# timecode_headphone_in_state_led OUTPUT V12 -# timecode_bnc_in INPUT R15 -# timecode_bnc_in_state_led INPUT D18 - -# define_attribute {p:ex_rst_n} {PAP_IO_DIRECTION} {INPUT} -# define_attribute {p:ex_rst_n} {PAP_IO_LOC} {G13} -# define_attribute {p:ex_rst_n} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVTTL33} define_attribute {p:ex_clk} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:ex_clk} {PAP_IO_LOC} {B5} +define_attribute {p:ex_clk} {PAP_IO_LOC} {R4} define_attribute {p:ex_clk} {PAP_IO_VCCIO} {3.3} define_attribute {p:ex_clk} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:core_board_debug_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:core_board_debug_led} {PAP_IO_LOC} {E2} -define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {4} -define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {SLOW} -# define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} -# define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {U13} -# define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} -# define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4} -# define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} -# define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT} -# define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {V13} -# define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33} -# define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT} -# define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {V14} -# define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVTTL33} -# define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT} -# define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {U14} -# define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:debug_signal_output[0]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[0]} {PAP_IO_LOC} {M18} -define_attribute {p:debug_signal_output[0]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[0]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[0]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[0]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[1]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[1]} {PAP_IO_LOC} {K18} -define_attribute {p:debug_signal_output[1]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[1]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[1]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[1]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[2]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[2]} {PAP_IO_LOC} {K17} -define_attribute {p:debug_signal_output[2]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[2]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[2]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[2]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[3]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[3]} {PAP_IO_LOC} {H18} -define_attribute {p:debug_signal_output[3]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[3]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[3]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[3]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[4]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[4]} {PAP_IO_LOC} {H17} -define_attribute {p:debug_signal_output[4]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[4]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[4]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[4]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[5]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[5]} {PAP_IO_LOC} {G18} -define_attribute {p:debug_signal_output[5]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[5]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[5]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[5]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[6]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[6]} {PAP_IO_LOC} {G17} -define_attribute {p:debug_signal_output[6]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[6]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[6]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[6]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[7]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[7]} {PAP_IO_LOC} {F18} -define_attribute {p:debug_signal_output[7]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[7]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[7]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[7]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[8]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[8]} {PAP_IO_LOC} {F17} -define_attribute {p:debug_signal_output[8]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[8]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[8]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[8]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[9]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[9]} {PAP_IO_LOC} {G16} -define_attribute {p:debug_signal_output[9]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[9]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[9]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[9]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[10]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[10]} {PAP_IO_LOC} {F16} -define_attribute {p:debug_signal_output[10]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[10]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[10]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[10]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[11]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[11]} {PAP_IO_LOC} {H16} -define_attribute {p:debug_signal_output[11]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[11]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[11]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[11]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[12]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[12]} {PAP_IO_LOC} {J16} -define_attribute {p:debug_signal_output[12]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[12]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[12]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[12]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[13]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[13]} {PAP_IO_LOC} {C17} -define_attribute {p:debug_signal_output[13]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[13]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[13]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[13]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[14]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[14]} {PAP_IO_LOC} {C18} -define_attribute {p:debug_signal_output[14]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[14]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[14]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[14]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:debug_signal_output[15]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_signal_output[15]} {PAP_IO_LOC} {A18} -define_attribute {p:debug_signal_output[15]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:debug_signal_output[15]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:debug_signal_output[15]} {PAP_IO_DRIVE} {4} -define_attribute {p:debug_signal_output[15]} {PAP_IO_SLEW} {SLOW} - - - +define_attribute {p:ex_rst_n} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:ex_rst_n} {PAP_IO_LOC} {U7} +define_attribute {p:ex_rst_n} {PAP_IO_VCCIO} {3.3} +define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:genlock_in_hsync} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:genlock_in_hsync} {PAP_IO_LOC} {M15} +define_attribute {p:genlock_in_hsync} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_in_hsync} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:genlock_in_vsync} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:genlock_in_vsync} {PAP_IO_LOC} {M16} +define_attribute {p:genlock_in_vsync} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_in_vsync} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:genlock_in_fsync} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:genlock_in_fsync} {PAP_IO_LOC} {L16} +define_attribute {p:genlock_in_fsync} {PAP_IO_VCCIO} {3.3} +define_attribute {p:genlock_in_fsync} {PAP_IO_STANDARD} {LVTTL33} define_attribute {p:genlock_out_dac[0]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_out_dac[0]} {PAP_IO_LOC} {A16} +define_attribute {p:genlock_out_dac[0]} {PAP_IO_LOC} {E14} define_attribute {p:genlock_out_dac[0]} {PAP_IO_VCCIO} {3.3} define_attribute {p:genlock_out_dac[0]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[0]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[0]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[1]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_out_dac[1]} {PAP_IO_LOC} {B16} +define_attribute {p:genlock_out_dac[1]} {PAP_IO_LOC} {E13} define_attribute {p:genlock_out_dac[1]} {PAP_IO_VCCIO} {3.3} define_attribute {p:genlock_out_dac[1]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[1]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[1]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[2]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_out_dac[2]} {PAP_IO_LOC} {A15} +define_attribute {p:genlock_out_dac[2]} {PAP_IO_LOC} {F14} define_attribute {p:genlock_out_dac[2]} {PAP_IO_VCCIO} {3.3} define_attribute {p:genlock_out_dac[2]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[2]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[2]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[3]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_out_dac[3]} {PAP_IO_LOC} {B15} +define_attribute {p:genlock_out_dac[3]} {PAP_IO_LOC} {F13} define_attribute {p:genlock_out_dac[3]} {PAP_IO_VCCIO} {3.3} define_attribute {p:genlock_out_dac[3]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[3]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[3]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[4]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_out_dac[4]} {PAP_IO_LOC} {A14} +define_attribute {p:genlock_out_dac[4]} {PAP_IO_LOC} {C22} define_attribute {p:genlock_out_dac[4]} {PAP_IO_VCCIO} {3.3} define_attribute {p:genlock_out_dac[4]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[4]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[4]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[5]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_out_dac[5]} {PAP_IO_LOC} {B14} +define_attribute {p:genlock_out_dac[5]} {PAP_IO_LOC} {B22} define_attribute {p:genlock_out_dac[5]} {PAP_IO_VCCIO} {3.3} define_attribute {p:genlock_out_dac[5]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[5]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[5]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[6]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_out_dac[6]} {PAP_IO_LOC} {A12} +define_attribute {p:genlock_out_dac[6]} {PAP_IO_LOC} {C20} define_attribute {p:genlock_out_dac[6]} {PAP_IO_VCCIO} {3.3} define_attribute {p:genlock_out_dac[6]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[6]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[6]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[7]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_out_dac[7]} {PAP_IO_LOC} {B12} +define_attribute {p:genlock_out_dac[7]} {PAP_IO_LOC} {D20} define_attribute {p:genlock_out_dac[7]} {PAP_IO_VCCIO} {3.3} define_attribute {p:genlock_out_dac[7]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[7]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[7]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac[8]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_out_dac[8]} {PAP_IO_LOC} {A11} +define_attribute {p:genlock_out_dac[8]} {PAP_IO_LOC} {C19} define_attribute {p:genlock_out_dac[8]} {PAP_IO_VCCIO} {3.3} define_attribute {p:genlock_out_dac[8]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac[8]} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac[8]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:genlock_out_dac[9]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_out_dac[9]} {PAP_IO_LOC} {B11} -define_attribute {p:genlock_out_dac[9]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:genlock_out_dac[9]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:genlock_out_dac[9]} {PAP_IO_DRIVE} {4} -define_attribute {p:genlock_out_dac[9]} {PAP_IO_SLEW} {SLOW} define_attribute {p:genlock_out_dac_clk} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_out_dac_clk} {PAP_IO_LOC} {H13} +define_attribute {p:genlock_out_dac_clk} {PAP_IO_LOC} {C18} define_attribute {p:genlock_out_dac_clk} {PAP_IO_VCCIO} {3.3} define_attribute {p:genlock_out_dac_clk} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:genlock_out_dac_clk} {PAP_IO_DRIVE} {4} define_attribute {p:genlock_out_dac_clk} {PAP_IO_SLEW} {SLOW} -define_attribute {p:genlock_out_dac_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_out_dac_state_led} {PAP_IO_LOC} {D17} -define_attribute {p:genlock_out_dac_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:genlock_out_dac_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:genlock_out_dac_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:genlock_out_dac_state_led} {PAP_IO_SLEW} {SLOW} -define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:stm32if_camera_sync_out} {PAP_IO_LOC} {C10} -define_attribute {p:stm32if_camera_sync_out} {PAP_IO_VCCIO} {3.3} -define_attribute {p:stm32if_camera_sync_out} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DRIVE} {4} -define_attribute {p:stm32if_camera_sync_out} {PAP_IO_SLEW} {SLOW} -define_attribute {p:stm32if_start_signal_out} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:stm32if_start_signal_out} {PAP_IO_LOC} {F12} -define_attribute {p:stm32if_start_signal_out} {PAP_IO_VCCIO} {3.3} -define_attribute {p:stm32if_start_signal_out} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:stm32if_start_signal_out} {PAP_IO_DRIVE} {4} -define_attribute {p:stm32if_start_signal_out} {PAP_IO_SLEW} {SLOW} -define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_LOC} {G12} -define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_VCCIO} {3.3} -define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DRIVE} {4} -define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_SLEW} {SLOW} -# define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_DIRECTION} {OUTPUT} -# define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_LOC} {D13} -# define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_STANDARD} {LVCMOS33} -# define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_DRIVE} {4} -# define_attribute {p:stm32if_timecode_add[0]} {PAP_IO_SLEW} {SLOW} -# define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_DIRECTION} {OUTPUT} -# define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_LOC} {D15} -# define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_STANDARD} {LVCMOS33} -# define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_DRIVE} {4} -# define_attribute {p:stm32if_timecode_add[1]} {PAP_IO_SLEW} {SLOW} -# define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_DIRECTION} {OUTPUT} -# define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_LOC} {C15} -# define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_STANDARD} {LVCMOS33} -# define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_DRIVE} {4} -# define_attribute {p:stm32if_timecode_add[2]} {PAP_IO_SLEW} {SLOW} -# define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_DIRECTION} {OUTPUT} -# define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_LOC} {E15} -# define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_STANDARD} {LVCMOS33} -# define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_DRIVE} {4} -# define_attribute {p:stm32if_timecode_add[3]} {PAP_IO_SLEW} {SLOW} -# define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_DIRECTION} {OUTPUT} -# define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_LOC} {E16} -# define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_STANDARD} {LVCMOS33} -# define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_DRIVE} {4} -# define_attribute {p:stm32if_timecode_data[0]} {PAP_IO_SLEW} {SLOW} -# define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_DIRECTION} {OUTPUT} -# define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_LOC} {A17} -# define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_STANDARD} {LVCMOS33} -# define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_DRIVE} {4} -# define_attribute {p:stm32if_timecode_data[1]} {PAP_IO_SLEW} {SLOW} -# define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_DIRECTION} {OUTPUT} -# define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_LOC} {B17} -# define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_STANDARD} {LVCMOS33} -# define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_DRIVE} {4} -# define_attribute {p:stm32if_timecode_data[2]} {PAP_IO_SLEW} {SLOW} -# define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_DIRECTION} {OUTPUT} -# define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_LOC} {B18} -# define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_STANDARD} {LVCMOS33} -# define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_DRIVE} {4} -# define_attribute {p:stm32if_timecode_data[3]} {PAP_IO_SLEW} {SLOW} -# define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT} -# define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {P17} -# define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVTTL33} -# define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT} -# define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {L12} -# define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33} -# define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT} -# define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {R18} -# define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVTTL33} -# define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} -# define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {R17} -# define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} -# define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4} -# define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} - -# define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} -# define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {U13} -# define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} -# define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4} -# define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} -# define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT} -# define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {V13} -# define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33} -# define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT} -# define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {V14} -# define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVTTL33} -# define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT} -# define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {U14} -# define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3} -# define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVTTL33} - -define_attribute {p:spi2_cs_pin} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:spi2_cs_pin} {PAP_IO_LOC} {V14} -define_attribute {p:spi2_cs_pin} {PAP_IO_VCCIO} {3.3} -define_attribute {p:spi2_cs_pin} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:spi2_clk_pin} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:spi2_clk_pin} {PAP_IO_LOC} {V13} -define_attribute {p:spi2_clk_pin} {PAP_IO_VCCIO} {3.3} -define_attribute {p:spi2_clk_pin} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:spi2_rx_pin} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:spi2_rx_pin} {PAP_IO_LOC} {U14} -define_attribute {p:spi2_rx_pin} {PAP_IO_VCCIO} {3.3} -define_attribute {p:spi2_rx_pin} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:spi2_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:spi2_tx_pin} {PAP_IO_LOC} {U13} -define_attribute {p:spi2_tx_pin} {PAP_IO_VCCIO} {3.3} -define_attribute {p:spi2_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:spi2_tx_pin} {PAP_IO_DRIVE} {4} -define_attribute {p:spi2_tx_pin} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_in1} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:sync_ttl_in1} {PAP_IO_LOC} {R11} +define_attribute {p:sync_ttl_in1} {PAP_IO_LOC} {K18} define_attribute {p:sync_ttl_in1} {PAP_IO_VCCIO} {3.3} define_attribute {p:sync_ttl_in1} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:sync_ttl_in1_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:sync_ttl_in1_state_led} {PAP_IO_LOC} {U10} -define_attribute {p:sync_ttl_in1_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:sync_ttl_in1_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:sync_ttl_in1_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:sync_ttl_in1_state_led} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_in2} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:sync_ttl_in2} {PAP_IO_LOC} {P11} +define_attribute {p:sync_ttl_in2} {PAP_IO_LOC} {K19} define_attribute {p:sync_ttl_in2} {PAP_IO_VCCIO} {3.3} define_attribute {p:sync_ttl_in2} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:sync_ttl_in2_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:sync_ttl_in2_state_led} {PAP_IO_LOC} {V10} -define_attribute {p:sync_ttl_in2_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:sync_ttl_in2_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:sync_ttl_in2_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:sync_ttl_in2_state_led} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_in3} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:sync_ttl_in3} {PAP_IO_LOC} {R13} +define_attribute {p:sync_ttl_in3} {PAP_IO_LOC} {M13} define_attribute {p:sync_ttl_in3} {PAP_IO_VCCIO} {3.3} define_attribute {p:sync_ttl_in3} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:sync_ttl_in3_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:sync_ttl_in3_state_led} {PAP_IO_LOC} {U11} -define_attribute {p:sync_ttl_in3_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:sync_ttl_in3_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:sync_ttl_in3_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:sync_ttl_in3_state_led} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_in4} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {R14} +define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {L13} define_attribute {p:sync_ttl_in4} {PAP_IO_VCCIO} {3.3} define_attribute {p:sync_ttl_in4} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:sync_ttl_in4_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:sync_ttl_in4_state_led} {PAP_IO_LOC} {U12} -define_attribute {p:sync_ttl_in4_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:sync_ttl_in4_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:sync_ttl_in4_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:sync_ttl_in4_state_led} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_out1} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {V17} +define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {AA8} define_attribute {p:sync_ttl_out1} {PAP_IO_VCCIO} {3.3} define_attribute {p:sync_ttl_out1} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:sync_ttl_out1} {PAP_IO_DRIVE} {4} define_attribute {p:sync_ttl_out1} {PAP_IO_SLEW} {SLOW} -define_attribute {p:sync_ttl_out1_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:sync_ttl_out1_state_led} {PAP_IO_LOC} {L18} -define_attribute {p:sync_ttl_out1_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:sync_ttl_out1_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:sync_ttl_out1_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:sync_ttl_out1_state_led} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_out2} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:sync_ttl_out2} {PAP_IO_LOC} {T17} +define_attribute {p:sync_ttl_out2} {PAP_IO_LOC} {V9} define_attribute {p:sync_ttl_out2} {PAP_IO_VCCIO} {3.3} define_attribute {p:sync_ttl_out2} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:sync_ttl_out2} {PAP_IO_DRIVE} {4} define_attribute {p:sync_ttl_out2} {PAP_IO_SLEW} {SLOW} -define_attribute {p:sync_ttl_out2_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:sync_ttl_out2_state_led} {PAP_IO_LOC} {L17} -define_attribute {p:sync_ttl_out2_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:sync_ttl_out2_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:sync_ttl_out2_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:sync_ttl_out2_state_led} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_out3} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:sync_ttl_out3} {PAP_IO_LOC} {U17} +define_attribute {p:sync_ttl_out3} {PAP_IO_LOC} {V8} define_attribute {p:sync_ttl_out3} {PAP_IO_VCCIO} {3.3} define_attribute {p:sync_ttl_out3} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:sync_ttl_out3} {PAP_IO_DRIVE} {4} define_attribute {p:sync_ttl_out3} {PAP_IO_SLEW} {SLOW} - - -define_attribute {p:sync_ttl_out3_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:sync_ttl_out3_state_led} {PAP_IO_LOC} {N16} -define_attribute {p:sync_ttl_out3_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:sync_ttl_out3_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:sync_ttl_out3_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:sync_ttl_out3_state_led} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_out4} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {M13} +define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {T6} define_attribute {p:sync_ttl_out4} {PAP_IO_VCCIO} {3.3} define_attribute {p:sync_ttl_out4} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:sync_ttl_out4} {PAP_IO_DRIVE} {4} define_attribute {p:sync_ttl_out4} {PAP_IO_SLEW} {SLOW} -define_attribute {p:sync_ttl_out4_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:sync_ttl_out4_state_led} {PAP_IO_LOC} {N15} -define_attribute {p:sync_ttl_out4_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:sync_ttl_out4_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:sync_ttl_out4_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:sync_ttl_out4_state_led} {PAP_IO_SLEW} {SLOW} -define_attribute {p:genlock_in_hsync} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:genlock_in_hsync} {PAP_IO_LOC} {U16} -define_attribute {p:genlock_in_hsync} {PAP_IO_VCCIO} {3.3} -define_attribute {p:genlock_in_hsync} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:genlock_in_vsync} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:genlock_in_vsync} {PAP_IO_LOC} {V16} -define_attribute {p:genlock_in_vsync} {PAP_IO_VCCIO} {3.3} -define_attribute {p:genlock_in_vsync} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:genlock_in_fsync} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:genlock_in_fsync} {PAP_IO_LOC} {T16} -define_attribute {p:genlock_in_fsync} {PAP_IO_VCCIO} {3.3} -define_attribute {p:genlock_in_fsync} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:genlock_in_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:genlock_in_state_led} {PAP_IO_LOC} {N14} -define_attribute {p:genlock_in_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:genlock_in_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:genlock_in_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:genlock_in_state_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:timecode_headphone_in} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {L15} +define_attribute {p:timecode_headphone_in} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_headphone_in} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:timecode_bnc_in} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:timecode_bnc_in} {PAP_IO_LOC} {L14} +define_attribute {p:timecode_bnc_in} {PAP_IO_VCCIO} {3.3} +define_attribute {p:timecode_bnc_in} {PAP_IO_STANDARD} {LVTTL33} define_attribute {p:timecode_out_bnc} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:timecode_out_bnc} {PAP_IO_LOC} {L15} +define_attribute {p:timecode_out_bnc} {PAP_IO_LOC} {W9} define_attribute {p:timecode_out_bnc} {PAP_IO_VCCIO} {3.3} define_attribute {p:timecode_out_bnc} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:timecode_out_bnc} {PAP_IO_DRIVE} {4} define_attribute {p:timecode_out_bnc} {PAP_IO_SLEW} {SLOW} define_attribute {p:timecode_out_bnc_select} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:timecode_out_bnc_select} {PAP_IO_LOC} {A10} +define_attribute {p:timecode_out_bnc_select} {PAP_IO_LOC} {R6} define_attribute {p:timecode_out_bnc_select} {PAP_IO_VCCIO} {3.3} define_attribute {p:timecode_out_bnc_select} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:timecode_out_bnc_select} {PAP_IO_DRIVE} {4} define_attribute {p:timecode_out_bnc_select} {PAP_IO_SLEW} {SLOW} -define_attribute {p:timecode_out_bnc_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:timecode_out_bnc_state_led} {PAP_IO_LOC} {E17} -define_attribute {p:timecode_out_bnc_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:timecode_out_bnc_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:timecode_out_bnc_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:timecode_out_bnc_state_led} {PAP_IO_SLEW} {SLOW} define_attribute {p:timecode_out_headphone} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:timecode_out_headphone} {PAP_IO_LOC} {N18} +define_attribute {p:timecode_out_headphone} {PAP_IO_LOC} {Y9} define_attribute {p:timecode_out_headphone} {PAP_IO_VCCIO} {3.3} define_attribute {p:timecode_out_headphone} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:timecode_out_headphone} {PAP_IO_DRIVE} {4} define_attribute {p:timecode_out_headphone} {PAP_IO_SLEW} {SLOW} define_attribute {p:timecode_out_headphone_select} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:timecode_out_headphone_select} {PAP_IO_LOC} {B10} +define_attribute {p:timecode_out_headphone_select} {PAP_IO_LOC} {T3} define_attribute {p:timecode_out_headphone_select} {PAP_IO_VCCIO} {3.3} define_attribute {p:timecode_out_headphone_select} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:timecode_out_headphone_select} {PAP_IO_DRIVE} {4} define_attribute {p:timecode_out_headphone_select} {PAP_IO_SLEW} {SLOW} -define_attribute {p:timecode_out_headphone_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:timecode_out_headphone_state_led} {PAP_IO_LOC} {E18} -define_attribute {p:timecode_out_headphone_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:timecode_out_headphone_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:timecode_out_headphone_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:timecode_out_headphone_state_led} {PAP_IO_SLEW} {SLOW} - - -define_attribute {p:timecode_headphone_in} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {R16} -define_attribute {p:timecode_headphone_in} {PAP_IO_VCCIO} {3.3} -define_attribute {p:timecode_headphone_in} {PAP_IO_STANDARD} {LVTTL33} - -define_attribute {p:timecode_headphone_in_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:timecode_headphone_in_state_led} {PAP_IO_LOC} {V12} -define_attribute {p:timecode_headphone_in_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:timecode_headphone_in_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:timecode_headphone_in_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:timecode_headphone_in_state_led} {PAP_IO_SLEW} {SLOW} - -define_attribute {p:timecode_bnc_in} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:timecode_bnc_in} {PAP_IO_LOC} {R15} -define_attribute {p:timecode_bnc_in} {PAP_IO_VCCIO} {3.3} -define_attribute {p:timecode_bnc_in} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_LOC} {D18} -define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_VCCIO} {3.3} -define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_DRIVE} {4} -define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_SLEW} {SLOW} -define_attribute {p:ex_rst_n} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:ex_rst_n} {PAP_IO_LOC} {C13} -define_attribute {p:ex_rst_n} {PAP_IO_VCCIO} {3.3} -define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:sync_ttl_in1} {PAP_IO_PULLDW} {TRUE} -define_attribute {p:sync_ttl_in2} {PAP_IO_PULLDW} {TRUE} -define_attribute {p:sync_ttl_in3} {PAP_IO_PULLDW} {TRUE} -define_attribute {p:sync_ttl_in4} {PAP_IO_NONE} {TRUE} -define_attribute {p:timecode_bnc_in} {PAP_IO_NONE} {TRUE} -define_attribute {p:timecode_headphone_in} {PAP_IO_NONE} {TRUE} +define_attribute {p:stm32if_start_signal_out} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_start_signal_out} {PAP_IO_LOC} {Y21} +define_attribute {p:stm32if_start_signal_out} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_start_signal_out} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_start_signal_out} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_start_signal_out} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_camera_sync_out} {PAP_IO_LOC} {Y22} +define_attribute {p:stm32if_camera_sync_out} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_camera_sync_out} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_camera_sync_out} {PAP_IO_SLEW} {SLOW} +define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_LOC} {AB20} +define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_VCCIO} {3.3} +define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DRIVE} {4} +define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_SLEW} {SLOW} +define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {W7} +define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {V7} +define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {Y7} +define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {Y8} +define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4} +define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[0]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[0]} {PAP_IO_LOC} {Y11} +define_attribute {p:debug_signal_output[0]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[0]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[0]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[0]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[1]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[1]} {PAP_IO_LOC} {Y12} +define_attribute {p:debug_signal_output[1]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[1]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[1]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[1]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[2]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[2]} {PAP_IO_LOC} {AA10} +define_attribute {p:debug_signal_output[2]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[2]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[2]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[2]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[3]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[3]} {PAP_IO_LOC} {AA11} +define_attribute {p:debug_signal_output[3]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[3]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[3]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[3]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[4]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[4]} {PAP_IO_LOC} {AB11} +define_attribute {p:debug_signal_output[4]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[4]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[4]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[4]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[5]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[5]} {PAP_IO_LOC} {AB12} +define_attribute {p:debug_signal_output[5]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[5]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[5]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[5]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[6]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[6]} {PAP_IO_LOC} {W11} +define_attribute {p:debug_signal_output[6]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[6]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[6]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[6]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[7]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[7]} {PAP_IO_LOC} {W12} +define_attribute {p:debug_signal_output[7]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[7]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[7]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[7]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[8]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[8]} {PAP_IO_LOC} {AA13} +define_attribute {p:debug_signal_output[8]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[8]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[8]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[8]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[9]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[9]} {PAP_IO_LOC} {AB13} +define_attribute {p:debug_signal_output[9]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[9]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[9]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[9]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[10]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[10]} {PAP_IO_LOC} {Y13} +define_attribute {p:debug_signal_output[10]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[10]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[10]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[10]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[11]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[11]} {PAP_IO_LOC} {AA14} +define_attribute {p:debug_signal_output[11]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[11]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[11]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[11]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[12]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[12]} {PAP_IO_LOC} {AA15} +define_attribute {p:debug_signal_output[12]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[12]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[12]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[12]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[13]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[13]} {PAP_IO_LOC} {AB15} +define_attribute {p:debug_signal_output[13]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[13]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[13]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[13]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[14]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[14]} {PAP_IO_LOC} {Y16} +define_attribute {p:debug_signal_output[14]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[14]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[14]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[14]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:debug_signal_output[15]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:debug_signal_output[15]} {PAP_IO_LOC} {AA16} +define_attribute {p:debug_signal_output[15]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:debug_signal_output[15]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:debug_signal_output[15]} {PAP_IO_DRIVE} {4} +define_attribute {p:debug_signal_output[15]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:core_board_debug_led} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:core_board_debug_led} {PAP_IO_LOC} {W5} +define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {3.3} +define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {4} +define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {SLOW} diff --git a/xsync.pds b/xsync.pds index b18e0cd..3f55766 100644 --- a/xsync.pds +++ b/xsync.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Fri Aug 23 13:40:20 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Fri Aug 23 15:51:49 2024") (_version "1.0.5") (_status "initial") (_project @@ -8,10 +8,10 @@ (_widget wgt_select_arch (_input (_part - (_family Logos) - (_device PGL22G) + (_family Logos2) + (_device PG2L100H) (_speedgrade -6) - (_package MBG324) + (_package FBG484) ) ) ) @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-08-23T13:36:15") + (_timespec "2024-08-23T15:50:29") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -81,10 +81,6 @@ (_format verilog) (_timespec "2024-08-23T13:36:15") ) - (_file "source/src/xsync_internal_generator.v" - (_format verilog) - (_timespec "2024-08-23T13:36:15") - ) (_file "source/src/zutils/zutils_pwm_generator_advanced.v" (_format verilog) (_timespec "2024-08-23T13:36:15") @@ -223,7 +219,7 @@ ) (_file "source/src/zutils/zutils_sig_delayer_v2.v" (_format verilog) - (_timespec "2024-08-23T13:36:15") + (_timespec "2024-08-23T15:51:36") ) (_file "source/src/zutils/zutils_pluse_delayer.v" (_format verilog) @@ -241,15 +237,6 @@ ) (_widget wgt_my_ips_src (_input - (_ip "ipcore/SPLL/SPLL.idf" - (_timespec "2024-08-23T13:36:15") - (_ip_source_item "ipcore/SPLL/SPLL.v" - (_timespec "2024-08-23T13:36:15") - ) - ) - (_ip "ipcore/genlock_sig_gen_pll/genlock_sig_gen_pll.idf" - (_timespec "2024-08-23T13:36:15") - ) (_ip "ipcore/ShiftRegister/ShiftRegister.idf" (_timespec "2024-08-23T13:36:15") (_ip_source_item "ipcore/ShiftRegister/rtl/ipm_distributed_sdpram_v1_2_ShiftRegister.v" @@ -262,13 +249,19 @@ (_timespec "2024-08-23T13:36:15") ) ) + (_ip "ipcore/SPLL/SPLL.idf" + (_timespec "2024-08-23T14:44:49") + (_ip_source_item "ipcore/SPLL/SPLL.v" + (_timespec "2024-08-23T14:44:49") + ) + ) ) ) (_widget wgt_import_logic_con_file (_input (_file "xsync.fdc" (_format fdc) - (_timespec "2024-08-23T13:36:15") + (_timespec "2024-08-23T15:44:26") ) ) ) @@ -319,17 +312,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-08-23T13:39:59") + (_timespec "2024-08-23T15:51:49") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-08-23T13:39:49") + (_timespec "2024-08-23T15:51:45") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-08-23T13:39:59") + (_timespec "2024-08-23T15:51:49") ) ) ) @@ -339,7 +332,7 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 5)) + (_gci_state (_integer 0)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) ) @@ -363,7 +356,7 @@ (_input (_file "device_map/xsync.pcf" (_format pcf) - (_timespec "") + (_timespec "2024-08-23T15:46:12") ) ) )