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添加呼吸灯模块

master
zhaohe 11 months ago
parent
5e08a6875f
commit
64320fea7f
7 changed files with 221 additions and 153 deletions
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  1. 31
      constraint_check/constraint_check.ccr
  2. 12
      multiseed_summary.csv
  3. 100
      source/src/top.v
  4. 63
      source/src/zutils/breathing_lamp.v
  5. 105
      xsync.fdc
  6. 58
      xsync.pds
  7. 5
      xsync.pds.lock

31
constraint_check/constraint_check.ccr
View File

@ -1,4 +1,4 @@
##### Written on 2024/08/26 00:05:03 ###############################
##### Written on 2024/08/28 18:19:19 ###############################
##### INFO ################################################## ##### INFO ##################################################
@ -14,7 +14,7 @@ Constraint File(s) :
##### SUMMARY ###################################################### ##### SUMMARY ######################################################
Found 0 error(s), 9 critical warning(s), 15 warning(s), out of 340 constraint(s)
Found 0 error(s), 18 critical warning(s), 15 warning(s), out of 343 constraint(s)
Inapplicable constraints(except overwritten constraints): Inapplicable constraints(except overwritten constraints):
@ -35,18 +35,45 @@ define_attribute {p:sync_ttl_in3} {PAP_IO_LOC} {M13}
define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {L13} define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {L13}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 96)] | Port sync_ttl_in4 has been placed at location L13, whose type is share pin. C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 96)] | Port sync_ttl_in4 has been placed at location L13, whose type is share pin.
define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {R14}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 100)] | Port sync_ttl_out1 has been placed at location R14, whose type is share pin.
define_attribute {p:sync_ttl_out2} {PAP_IO_LOC} {N14}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 106)] | Port sync_ttl_out2 has been placed at location N14, whose type is share pin.
define_attribute {p:sync_ttl_out3} {PAP_IO_LOC} {R17}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 112)] | Port sync_ttl_out3 has been placed at location R17, whose type is share pin.
define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {L15} define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {L15}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 124)] | Port timecode_headphone_in has been placed at location L15, whose type is share pin. C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 124)] | Port timecode_headphone_in has been placed at location L15, whose type is share pin.
define_attribute {p:timecode_bnc_in} {PAP_IO_LOC} {L14} define_attribute {p:timecode_bnc_in} {PAP_IO_LOC} {L14}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 128)] | Port timecode_bnc_in has been placed at location L14, whose type is share pin. C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 128)] | Port timecode_bnc_in has been placed at location L14, whose type is share pin.
define_attribute {p:timecode_out_bnc} {PAP_IO_LOC} {P17}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 132)] | Port timecode_out_bnc has been placed at location P17, whose type is share pin.
define_attribute {p:timecode_out_bnc_select} {PAP_IO_LOC} {R18}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 138)] | Port timecode_out_bnc_select has been placed at location R18, whose type is share pin.
define_attribute {p:timecode_out_headphone} {PAP_IO_LOC} {R16}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 144)] | Port timecode_out_headphone has been placed at location R16, whose type is share pin.
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_LOC} {Y22} define_attribute {p:stm32if_camera_sync_out} {PAP_IO_LOC} {Y22}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 162)] | Port stm32if_camera_sync_out has been placed at location Y22, whose type is share pin. C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 162)] | Port stm32if_camera_sync_out has been placed at location Y22, whose type is share pin.
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_LOC} {AB20} define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_LOC} {AB20}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 168)] | Port stm32if_timecode_sync_out has been placed at location AB20, whose type is share pin. C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 168)] | Port stm32if_timecode_sync_out has been placed at location AB20, whose type is share pin.
define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {P14}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 178)] | Port spi1_clk_pin has been placed at location P14, whose type is share pin.
define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {P15}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 182)] | Port spi1_rx_pin has been placed at location P15, whose type is share pin.
define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {P16}
C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 186)] | Port spi1_tx_pin has been placed at location P16, whose type is share pin.
Constraints with issues: Constraints with issues:
******************************************** ********************************************

12
multiseed_summary.csv
View File

@ -3,23 +3,23 @@ project name,xsync.pds
Single Seed: Single Seed:
Seed,State,Convergence,Setup(Slow),Setup(Fast),Hold(Slow),Hold(Fast),Recovery(Slow),Recovery(Fast),Removal(Slow),Removal(Fast),PBM-GP,PBM-PreGP,PBM-PostGP,LP,Total Placement Cpu Time,Detailed routing,Total Routing Cpu Time,Wire Length After Post-GP,Wire Length After LP,Wire Length After DP,Routing Arc Length,Worst Slack After GP Timing,Worst Slack After LP Timing,Worst Slack Before RP,Worst Slack Before DP,Worst Slack After DP,Worst Slack After Placement,Worst Slack After TA By Preroute,TNS After DP,TNS Before Route,Setup(Slow) Total Failing TNS,Setup(Slow) Total Failing Endpoints,Hold(Slow) Total Failing THS,Hold(Slow) Total Failing Endpoints,Power Seed,State,Convergence,Setup(Slow),Setup(Fast),Hold(Slow),Hold(Fast),Recovery(Slow),Recovery(Fast),Removal(Slow),Removal(Fast),PBM-GP,PBM-PreGP,PBM-PostGP,LP,Total Placement Cpu Time,Detailed routing,Total Routing Cpu Time,Wire Length After Post-GP,Wire Length After LP,Wire Length After DP,Routing Arc Length,Worst Slack After GP Timing,Worst Slack After LP Timing,Worst Slack Before RP,Worst Slack Before DP,Worst Slack After DP,Worst Slack After Placement,Worst Slack After TA By Preroute,TNS After DP,TNS Before Route,Setup(Slow) Total Failing TNS,Setup(Slow) Total Failing Endpoints,Hold(Slow) Total Failing THS,Hold(Slow) Total Failing Endpoints,Power
single,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,0.12,7.09,1.67,9.17,NA,NA,NA,10137,NA,NA,995931,995931,995931,995931,NA,0,0,NA,NA,NA,NA,NA
single,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,0.03,4.62,1.14,5.58,NA,NA,NA,10319,NA,NA,995944,995944,995944,995944,NA,0,0,NA,NA,NA,NA,NA
Pass Rate/Convergence Rate,0.00%,0.00% Pass Rate/Convergence Rate,0.00%,0.00%
Synthesize: Synthesize:
control_set,35
control_set,38
Synthesize Performance Summary: Synthesize Performance Summary:
slack category,Synthesize Setup WNS,Synthesize Setup TNS,Synthesize Recovery WNS,Synthesize Recovery TNS slack category,Synthesize Setup WNS,Synthesize Setup TNS,Synthesize Recovery WNS,Synthesize Recovery TNS
slack value,995.809,0.000,NA,NA slack value,995.809,0.000,NA,NA
Synthesize Process Cpu Time,0h:0m:10s
Synthesize Process Cpu Time,0h:0m:3s
Device Map: Device Map:
Device Map Resource Usage Summary: Device Map Resource Usage Summary:
Logic Utilization,LUT,FF,DRM,APM,Distributed RAM,HSSTHP,USCM,HCKB,RCKB Logic Utilization,LUT,FF,DRM,APM,Distributed RAM,HSSTHP,USCM,HCKB,RCKB
Used,516,715,0,0,0,NA,1,0,0
Used,561,744,0,0,0,NA,2,0,0
Available,66600,133200,155,240,19900,NA,32,96,24 Available,66600,133200,155,240,19900,NA,32,96,24
Utilization(%),1%,1%,0%,0%,0%,NA,4%,0%,0%
Device Map Process Cpu Time,0h:0m:10s
Utilization(%),1%,1%,0%,0%,0%,NA,7%,0%,0%
Device Map Process Cpu Time,0h:0m:2s
Project Configurations: Project Configurations:
top module,Top top module,Top

100
source/src/top.v
View File

@ -65,12 +65,40 @@ module Top (
output [15:0] debug_signal_output, output [15:0] debug_signal_output,
output reg core_board_debug_led
output core_board_debug_led
); );
/***********************************************************************************************************************
* 时钟 *
***********************************************************************************************************************/
localparam SYS_CLOCK_FREQ = 10000000; localparam SYS_CLOCK_FREQ = 10000000;
wire sys_clk; //! 系统时钟
wire sys_rst_n; //! 系统复位
wire sys_clk; //! 系统时钟
wire sys_rst_n; //! 系统复位
//系统时钟源
SPLL spll (
.clkin1 (ex_clk),
.lock (pll_lock),
.clkout0(sys_clk_25m),
.clkout1(sys_clk_10m),
.clkout2(sys_clk_5m)
);
assign sys_clk = sys_clk_10m;
assign sys_rst_n = ex_rst_n & pll_lock;
/***********************************************************************************************************************
* 调试指示灯 *
***********************************************************************************************************************/
breathing_lamp breathing_lamp_ins (
.clk (ex_clk),
.rst_n (ex_rst_n),
.lampio(core_board_debug_led)
);
/***********************************************************************************************************************
* 其他 *
***********************************************************************************************************************/
//寄存器读写总线 //寄存器读写总线
wire [31:0] RegReaderBus_addr; //!寄存器读写-地址总线 wire [31:0] RegReaderBus_addr; //!寄存器读写-地址总线
@ -167,16 +195,7 @@ module Top (
assign signal_sys_timecode_freq_output = sys_timecode_tigger_sig; assign signal_sys_timecode_freq_output = sys_timecode_tigger_sig;
//系统时钟源
SPLL spll (
.clkin1 (ex_clk),
.lock (pll_lock),
.clkout0(sys_clk_25m),
.clkout1(sys_clk_10m),
.clkout2(sys_clk_5m)
);
assign sys_clk = sys_clk_10m;
assign sys_rst_n = ex_rst_n & pll_lock;
spi_reg_bus _spi_reg_bus ( spi_reg_bus _spi_reg_bus (
.clk (sys_clk), .clk (sys_clk),
@ -242,60 +261,7 @@ module Top (
); );
/***********************************************************************************************************************
* 呼吸灯输出 *
***********************************************************************************************************************/
//parameter define
parameter CNT_2US_MAX = 7'd100;
parameter CNT_2MS_MAX = 10'd1000;
parameter CNT_2S_MAX = 10'd1000;
//reg define
reg [6:0] cnt_2us;
reg [9:0] cnt_2ms;
reg [9:0] cnt_2s;
reg inc_dec_flag; //亮度递增/递减 0:递增 1:递减
//*****************************************************
//** main code
//*****************************************************
//cnt_2us:计数2us
always @(posedge ex_clk or negedge ex_rst_n) begin
if (!ex_rst_n) cnt_2us <= 7'b0;
else if (cnt_2us == (CNT_2US_MAX - 7'b1)) cnt_2us <= 7'b0;
else cnt_2us <= cnt_2us + 7'b1;
end
//cnt_2ms:计数2ms
always @(posedge ex_clk or negedge ex_rst_n) begin
if (!ex_rst_n) cnt_2ms <= 10'b0;
else if (cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) cnt_2ms <= 10'b0;
else if (cnt_2us == CNT_2US_MAX - 7'b1) cnt_2ms <= cnt_2ms + 10'b1;
else cnt_2ms <= cnt_2ms;
end
//cnt_2s:计数2s
always @(posedge ex_clk or negedge ex_rst_n) begin
if (!ex_rst_n) cnt_2s <= 10'b0;
else if (cnt_2s == (CNT_2S_MAX - 10'b1) && cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) cnt_2s <= 10'b0;
else if (cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) cnt_2s <= cnt_2s + 10'b1;
else cnt_2s <= cnt_2s;
end
//inc_dec_flag为低电平，led灯由暗变亮，inc_dec_flag为高电平，led灯由亮变暗
always @(posedge ex_clk or negedge ex_rst_n) begin
if (!ex_rst_n) inc_dec_flag <= 1'b0;
else if (cnt_2s == (CNT_2S_MAX - 10'b1) && cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) inc_dec_flag <= ~inc_dec_flag;
else inc_dec_flag <= inc_dec_flag;
end
//led:输出信号连接到外部的led灯
always @(posedge ex_clk or negedge ex_rst_n) begin
if (!ex_rst_n) core_board_debug_led <= 1'b0;
else if ((inc_dec_flag == 1'b1 && cnt_2ms >= cnt_2s) || (inc_dec_flag == 1'b0 && cnt_2ms <= cnt_2s)) core_board_debug_led <= 1'b1;
else core_board_debug_led <= 1'b0;
end
/*********************************************************************************************************************** /***********************************************************************************************************************
* 呼吸灯输出结束 * * 呼吸灯输出结束 *

63
source/src/zutils/breathing_lamp.v
View File

@ -0,0 +1,63 @@
module breathing_lamp (
input clk, //!clock input
input rst_n, //!asynchronous reset input, low active
output reg lampio
);
/***********************************************************************************************************************
* 呼吸灯输出 *
***********************************************************************************************************************/
//parameter define
parameter CNT_2US_MAX = 7'd100;
parameter CNT_2MS_MAX = 10'd1000;
parameter CNT_2S_MAX = 10'd1000;
//reg define
reg [6:0] cnt_2us;
reg [9:0] cnt_2ms;
reg [9:0] cnt_2s;
reg inc_dec_flag; //亮度递增/递减 0:递增 1:递减
//*****************************************************
//** main code
//*****************************************************
//cnt_2us:计数2us
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_2us <= 7'b0;
else if (cnt_2us == (CNT_2US_MAX - 7'b1)) cnt_2us <= 7'b0;
else cnt_2us <= cnt_2us + 7'b1;
end
//cnt_2ms:计数2ms
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_2ms <= 10'b0;
else if (cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) cnt_2ms <= 10'b0;
else if (cnt_2us == CNT_2US_MAX - 7'b1) cnt_2ms <= cnt_2ms + 10'b1;
else cnt_2ms <= cnt_2ms;
end
//cnt_2s:计数2s
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_2s <= 10'b0;
else if (cnt_2s == (CNT_2S_MAX - 10'b1) && cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) cnt_2s <= 10'b0;
else if (cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) cnt_2s <= cnt_2s + 10'b1;
else cnt_2s <= cnt_2s;
end
//inc_dec_flag为低电平，led灯由暗变亮，inc_dec_flag为高电平，led灯由亮变暗
always @(posedge clk or negedge rst_n) begin
if (!rst_n) inc_dec_flag <= 1'b0;
else if (cnt_2s == (CNT_2S_MAX - 10'b1) && cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1)) inc_dec_flag <= ~inc_dec_flag;
else inc_dec_flag <= inc_dec_flag;
end
//led:输出信号连接到外部的led灯
always @(posedge clk or negedge rst_n) begin
if (!rst_n) lampio <= 1'b0;
else if ((inc_dec_flag == 1'b1 && cnt_2ms >= cnt_2s) || (inc_dec_flag == 1'b0 && cnt_2ms <= cnt_2s)) lampio <= 1'b1;
else lampio <= 1'b0;
end
endmodule

105
xsync.fdc
View File

@ -97,28 +97,28 @@ define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {L13}
define_attribute {p:sync_ttl_in4} {PAP_IO_VCCIO} {3.3} define_attribute {p:sync_ttl_in4} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_in4} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:sync_ttl_in4} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out1} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:sync_ttl_out1} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {AA8}
define_attribute {p:sync_ttl_out1} {PAP_IO_VCCIO} {1.5}
define_attribute {p:sync_ttl_out1} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:sync_ttl_out1} {PAP_IO_DRIVE} {8}
define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {R14}
define_attribute {p:sync_ttl_out1} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_out1} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out1} {PAP_IO_DRIVE} {4}
define_attribute {p:sync_ttl_out1} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_out1} {PAP_IO_SLEW} {SLOW}
define_attribute {p:sync_ttl_out2} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:sync_ttl_out2} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:sync_ttl_out2} {PAP_IO_LOC} {V9}
define_attribute {p:sync_ttl_out2} {PAP_IO_VCCIO} {1.5}
define_attribute {p:sync_ttl_out2} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:sync_ttl_out2} {PAP_IO_DRIVE} {8}
define_attribute {p:sync_ttl_out2} {PAP_IO_LOC} {N14}
define_attribute {p:sync_ttl_out2} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_out2} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out2} {PAP_IO_DRIVE} {4}
define_attribute {p:sync_ttl_out2} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_out2} {PAP_IO_SLEW} {SLOW}
define_attribute {p:sync_ttl_out3} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:sync_ttl_out3} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:sync_ttl_out3} {PAP_IO_LOC} {V8}
define_attribute {p:sync_ttl_out3} {PAP_IO_VCCIO} {1.5}
define_attribute {p:sync_ttl_out3} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:sync_ttl_out3} {PAP_IO_DRIVE} {8}
define_attribute {p:sync_ttl_out3} {PAP_IO_LOC} {R17}
define_attribute {p:sync_ttl_out3} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_out3} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out3} {PAP_IO_DRIVE} {4}
define_attribute {p:sync_ttl_out3} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_out3} {PAP_IO_SLEW} {SLOW}
define_attribute {p:sync_ttl_out4} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:sync_ttl_out4} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {T6}
define_attribute {p:sync_ttl_out4} {PAP_IO_VCCIO} {1.5}
define_attribute {p:sync_ttl_out4} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:sync_ttl_out4} {PAP_IO_DRIVE} {8}
define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {N15}
define_attribute {p:sync_ttl_out4} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_out4} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out4} {PAP_IO_DRIVE} {4}
define_attribute {p:sync_ttl_out4} {PAP_IO_SLEW} {SLOW} define_attribute {p:sync_ttl_out4} {PAP_IO_SLEW} {SLOW}
define_attribute {p:timecode_headphone_in} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:timecode_headphone_in} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {L15} define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {L15}
@ -129,64 +129,64 @@ define_attribute {p:timecode_bnc_in} {PAP_IO_LOC} {L14}
define_attribute {p:timecode_bnc_in} {PAP_IO_VCCIO} {3.3} define_attribute {p:timecode_bnc_in} {PAP_IO_VCCIO} {3.3}
define_attribute {p:timecode_bnc_in} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:timecode_bnc_in} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:timecode_out_bnc} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:timecode_out_bnc} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:timecode_out_bnc} {PAP_IO_LOC} {W9}
define_attribute {p:timecode_out_bnc} {PAP_IO_VCCIO} {1.5}
define_attribute {p:timecode_out_bnc} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:timecode_out_bnc} {PAP_IO_DRIVE} {8}
define_attribute {p:timecode_out_bnc} {PAP_IO_LOC} {P17}
define_attribute {p:timecode_out_bnc} {PAP_IO_VCCIO} {3.3}
define_attribute {p:timecode_out_bnc} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:timecode_out_bnc} {PAP_IO_DRIVE} {4}
define_attribute {p:timecode_out_bnc} {PAP_IO_SLEW} {SLOW} define_attribute {p:timecode_out_bnc} {PAP_IO_SLEW} {SLOW}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:timecode_out_bnc_select} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_LOC} {R6}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_VCCIO} {1.5}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_DRIVE} {8}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_LOC} {R18}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_VCCIO} {3.3}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_DRIVE} {4}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_SLEW} {SLOW} define_attribute {p:timecode_out_bnc_select} {PAP_IO_SLEW} {SLOW}
define_attribute {p:timecode_out_headphone} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:timecode_out_headphone} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:timecode_out_headphone} {PAP_IO_LOC} {Y9}
define_attribute {p:timecode_out_headphone} {PAP_IO_VCCIO} {1.5}
define_attribute {p:timecode_out_headphone} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:timecode_out_headphone} {PAP_IO_DRIVE} {8}
define_attribute {p:timecode_out_headphone} {PAP_IO_LOC} {R16}
define_attribute {p:timecode_out_headphone} {PAP_IO_VCCIO} {3.3}
define_attribute {p:timecode_out_headphone} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:timecode_out_headphone} {PAP_IO_DRIVE} {4}
define_attribute {p:timecode_out_headphone} {PAP_IO_SLEW} {SLOW} define_attribute {p:timecode_out_headphone} {PAP_IO_SLEW} {SLOW}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:timecode_out_headphone_select} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_LOC} {T3}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_VCCIO} {1.5}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_DRIVE} {8}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_LOC} {P20}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_VCCIO} {3.3}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_DRIVE} {4}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_SLEW} {SLOW} define_attribute {p:timecode_out_headphone_select} {PAP_IO_SLEW} {SLOW}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:stm32if_start_signal_out} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_LOC} {Y21} define_attribute {p:stm32if_start_signal_out} {PAP_IO_LOC} {Y21}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_VCCIO} {1.5}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_VCCIO} {3.3}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_DRIVE} {4} define_attribute {p:stm32if_start_signal_out} {PAP_IO_DRIVE} {4}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_SLEW} {SLOW} define_attribute {p:stm32if_start_signal_out} {PAP_IO_SLEW} {SLOW}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_LOC} {Y22} define_attribute {p:stm32if_camera_sync_out} {PAP_IO_LOC} {Y22}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_VCCIO} {1.5}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_VCCIO} {3.3}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DRIVE} {4} define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DRIVE} {4}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_SLEW} {SLOW} define_attribute {p:stm32if_camera_sync_out} {PAP_IO_SLEW} {SLOW}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_LOC} {AB20} define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_LOC} {AB20}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_VCCIO} {1.5}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_VCCIO} {3.3}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DRIVE} {4} define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DRIVE} {4}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_SLEW} {SLOW} define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_SLEW} {SLOW}
define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {W7}
define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {1.5}
define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {N17}
define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3}
define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {V7}
define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {1.5}
define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {P14}
define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3}
define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {Y7}
define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {1.5}
define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {P15}
define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3}
define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {Y8}
define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {1.5}
define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {8}
define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {P16}
define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3}
define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4}
define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[0]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:debug_signal_output[0]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[0]} {PAP_IO_LOC} {Y11} define_attribute {p:debug_signal_output[0]} {PAP_IO_LOC} {Y11}
@ -338,3 +338,6 @@ define_attribute {p:timecode_out_headphone_select} {PAP_IO_NONE} {TRUE}
define_attribute {p:spi1_clk_pin} {PAP_IO_NONE} {TRUE} define_attribute {p:spi1_clk_pin} {PAP_IO_NONE} {TRUE}
define_attribute {p:spi1_cs_pin} {PAP_IO_NONE} {TRUE} define_attribute {p:spi1_cs_pin} {PAP_IO_NONE} {TRUE}
define_attribute {p:spi1_rx_pin} {PAP_IO_NONE} {TRUE} define_attribute {p:spi1_rx_pin} {PAP_IO_NONE} {TRUE}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_NONE} {TRUE}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_NONE} {TRUE}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_NONE} {TRUE}

58
xsync.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2022.2-SP4.2" (_flow fab_demo "2022.2-SP4.2"
(_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Mon Aug 26 09:10:50 2024")
(_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Wed Aug 28 18:21:09 2024")
(_version "1.1.0") (_version "1.1.0")
(_status "initial") (_status "initial")
(_project (_project
@ -21,7 +21,7 @@
(_input (_input
(_file "source/src/top.v" + "Top:" (_file "source/src/top.v" + "Top:"
(_format verilog) (_format verilog)
(_timespec "2024-08-26T00:04:16")
(_timespec "2024-08-28T18:03:33")
) )
(_file "source/src/spi_reg_reader.v" (_file "source/src/spi_reg_reader.v"
(_format verilog) (_format verilog)
@ -235,6 +235,10 @@
(_format verilog) (_format verilog)
(_timespec "2024-08-23T13:36:15") (_timespec "2024-08-23T13:36:15")
) )
(_file "source/src/zutils/breathing_lamp.v"
(_format verilog)
(_timespec "2024-08-28T18:00:19")
)
) )
) )
(_widget wgt_my_ips_src (_widget wgt_my_ips_src
@ -263,7 +267,7 @@
(_input (_input
(_file "xsync.fdc" (_file "xsync.fdc"
(_format fdc) (_format fdc)
(_timespec "2024-08-25T23:52:07")
(_timespec "2024-08-28T17:49:50")
) )
) )
) )
@ -314,17 +318,17 @@
(_db_output (_db_output
(_file "compile/Top_comp.adf" (_file "compile/Top_comp.adf"
(_format adif) (_format adif)
(_timespec "2024-08-26T00:04:44")
(_timespec "2024-08-28T18:19:12")
) )
) )
(_output (_output
(_file "compile/Top.cmr" (_file "compile/Top.cmr"
(_format verilog) (_format verilog)
(_timespec "2024-08-26T00:04:44")
(_timespec "2024-08-28T18:19:12")
) )
(_file "compile/cmr.db" (_file "compile/cmr.db"
(_format text) (_format text)
(_timespec "2024-08-26T00:04:44")
(_timespec "2024-08-28T18:19:13")
) )
) )
) )
@ -339,25 +343,25 @@
(_db_output (_db_output
(_file "synthesize/Top_syn.adf" (_file "synthesize/Top_syn.adf"
(_format adif) (_format adif)
(_timespec "2024-08-26T00:05:12")
(_timespec "2024-08-28T18:19:20")
) )
) )
(_output (_output
(_file "synthesize/Top_syn.vm" (_file "synthesize/Top_syn.vm"
(_format structural_verilog) (_format structural_verilog)
(_timespec "2024-08-26T00:05:13")
(_timespec "2024-08-28T18:19:20")
) )
(_file "synthesize/Top_controlsets.txt" (_file "synthesize/Top_controlsets.txt"
(_format text) (_format text)
(_timespec "2024-08-26T00:05:11")
(_timespec "2024-08-28T18:19:20")
) )
(_file "synthesize/snr.db" (_file "synthesize/snr.db"
(_format text) (_format text)
(_timespec "2024-08-26T00:05:13")
(_timespec "2024-08-28T18:19:21")
) )
(_file "synthesize/Top.snr" (_file "synthesize/Top.snr"
(_format text) (_format text)
(_timespec "2024-08-26T00:05:13")
(_timespec "2024-08-28T18:19:21")
) )
) )
) )
@ -378,21 +382,21 @@
(_db_output (_db_output
(_file "device_map/Top_map.adf" (_file "device_map/Top_map.adf"
(_format adif) (_format adif)
(_timespec "2024-08-26T00:05:43")
(_timespec "2024-08-28T18:19:29")
) )
) )
(_output (_output
(_file "device_map/Top_dmr.prt" (_file "device_map/Top_dmr.prt"
(_format text) (_format text)
(_timespec "2024-08-26T00:05:42")
(_timespec "2024-08-28T18:19:28")
) )
(_file "device_map/Top.dmr" (_file "device_map/Top.dmr"
(_format text) (_format text)
(_timespec "2024-08-26T00:05:43")
(_timespec "2024-08-28T18:19:29")
) )
(_file "device_map/dmr.db" (_file "device_map/dmr.db"
(_format text) (_format text)
(_timespec "2024-08-26T00:05:44")
(_timespec "2024-08-28T18:19:29")
) )
) )
) )
@ -401,7 +405,7 @@
(_input (_input
(_file "device_map/xsync.pcf" (_file "device_map/xsync.pcf"
(_format pcf) (_format pcf)
(_timespec "2024-08-26T00:05:43")
(_timespec "2024-08-28T18:19:29")
) )
) )
) )
@ -422,33 +426,33 @@
(_db_output (_db_output
(_file "place_route/Top_pnr.adf" (_file "place_route/Top_pnr.adf"
(_format adif) (_format adif)
(_timespec "2024-08-26T00:07:33")
(_timespec "2024-08-28T18:20:40")
) )
) )
(_output (_output
(_file "place_route/clock_utilization.txt" (_file "place_route/clock_utilization.txt"
(_format text) (_format text)
(_timespec "2024-08-26T00:07:30")
(_timespec "2024-08-28T18:20:36")
) )
(_file "place_route/Top_plc.adf" (_file "place_route/Top_plc.adf"
(_format adif) (_format adif)
(_timespec "2024-08-26T00:06:57")
(_timespec "2024-08-28T18:20:11")
) )
(_file "place_route/Top.prr" (_file "place_route/Top.prr"
(_format text) (_format text)
(_timespec "2024-08-26T00:07:34")
(_timespec "2024-08-28T18:20:40")
) )
(_file "place_route/Top_prr.prt" (_file "place_route/Top_prr.prt"
(_format text) (_format text)
(_timespec "2024-08-26T00:07:30")
(_timespec "2024-08-28T18:20:36")
) )
(_file "place_route/Top_pnr.netlist" (_file "place_route/Top_pnr.netlist"
(_format text) (_format text)
(_timespec "2024-08-26T00:07:33")
(_timespec "2024-08-28T18:20:40")
) )
(_file "place_route/prr.db" (_file "place_route/prr.db"
(_format text) (_format text)
(_timespec "2024-08-26T00:07:34")
(_timespec "2024-08-28T18:20:40")
) )
) )
) )
@ -484,19 +488,19 @@
(_output (_output
(_file "generate_bitstream/Top.sbit" (_file "generate_bitstream/Top.sbit"
(_format text) (_format text)
(_timespec "2024-08-26T00:08:30")
(_timespec "2024-08-28T18:21:06")
) )
(_file "generate_bitstream/Top.smsk" (_file "generate_bitstream/Top.smsk"
(_format text) (_format text)
(_timespec "2024-08-26T00:08:30")
(_timespec "2024-08-28T18:21:06")
) )
(_file "generate_bitstream/bgr.db" (_file "generate_bitstream/bgr.db"
(_format text) (_format text)
(_timespec "2024-08-26T00:08:34")
(_timespec "2024-08-28T18:21:09")
) )
(_file "generate_bitstream/Top.bgr" (_file "generate_bitstream/Top.bgr"
(_format text) (_format text)
(_timespec "2024-08-26T00:08:34")
(_timespec "2024-08-28T18:21:09")
) )
) )
) )

5
xsync.pds.lock
View File

@ -0,0 +1,5 @@
25920
pds
ZHAOHE
f8caf121-d1d2-4c26-8a45-7e1d59cde8b6
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