diff --git a/led_test.fdc b/led_test.fdc
index bd642af..d56a766 100644
--- a/led_test.fdc
+++ b/led_test.fdc
@@ -573,3 +573,9 @@ define_attribute {p:ex_rst_n} {PAP_IO_DIRECTION} {INPUT}
 define_attribute {p:ex_rst_n} {PAP_IO_LOC} {C13}
 define_attribute {p:ex_rst_n} {PAP_IO_VCCIO} {3.3}
 define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:sync_ttl_in1} {PAP_IO_PULLDW} {TRUE}
+define_attribute {p:sync_ttl_in2} {PAP_IO_PULLDW} {TRUE}
+define_attribute {p:sync_ttl_in3} {PAP_IO_PULLDW} {TRUE}
+define_attribute {p:sync_ttl_in4} {PAP_IO_PULLDW} {TRUE}
+define_attribute {p:timecode_bnc_in} {PAP_IO_PULLDW} {TRUE}
+define_attribute {p:timecode_headphone_in} {PAP_IO_PULLDW} {TRUE}
diff --git a/led_test.pds b/led_test.pds
index d15f807..022c403 100644
--- a/led_test.pds
+++ b/led_test.pds
@@ -1,5 +1,5 @@
 (_flow fab_demo "2021.1-SP7"
-    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Mar 26 22:08:39 2024")
+    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Wed Mar 27 16:10:02 2024")
     (_version "1.0.5")
     (_status "initial")
     (_project 
@@ -19,7 +19,7 @@
             (_input
                 (_file "source/src/top.v" + "Top:"
                     (_format verilog)
-                    (_timespec "2024-03-26T22:07:22")
+                    (_timespec "2024-03-27T15:36:20")
                 )
                 (_file "source/src/spi_reg_reader.v"
                     (_format verilog)
@@ -59,7 +59,7 @@
                 )
                 (_file "source/src/output/ttl_output.v"
                     (_format verilog)
-                    (_timespec "2024-03-25T14:05:59")
+                    (_timespec "2024-03-27T16:06:42")
                 )
                 (_file "source/src/zutils/zutils_pwm_generator.v"
                     (_format verilog)
@@ -163,7 +163,7 @@
                 )
                 (_file "source/src/zutils/zsimple_pll.v"
                     (_format verilog)
-                    (_timespec "2024-03-26T18:46:59")
+                    (_timespec "2024-03-27T12:48:00")
                 )
                 (_file "source/src/zutils/zutils_freq_detector_v2.v"
                     (_format verilog)
@@ -191,7 +191,7 @@
                 )
                 (_file "source/src/internal/internal_clock_generator.v"
                     (_format verilog)
-                    (_timespec "2024-03-23T16:38:57")
+                    (_timespec "2024-03-27T12:08:29")
                 )
                 (_file "source/src/internal/internal_genlock_generator.v"
                     (_format verilog)
@@ -203,11 +203,11 @@
                 )
                 (_file "source/src/sys/sys_clock.v"
                     (_format verilog)
-                    (_timespec "2024-03-05T16:10:23")
+                    (_timespec "2024-03-27T12:19:38")
                 )
                 (_file "source/src/output/camera_sync_signal_output.v"
                     (_format verilog)
-                    (_timespec "2024-03-26T16:56:33")
+                    (_timespec "2024-03-27T12:07:13")
                 )
                 (_file "source/src/business/record_sig_generator.v"
                     (_format verilog)
@@ -215,7 +215,7 @@
                 )
                 (_file "source/src/sys_signal_delayer.v"
                     (_format verilog)
-                    (_timespec "2024-03-26T21:16:17")
+                    (_timespec "2024-03-27T14:18:37")
                 )
                 (_file "source/src/zutils/zutils_sig_delayer.v"
                     (_format verilog)
@@ -223,7 +223,7 @@
                 )
                 (_file "source/src/zutils/zutils_sig_delayer_v2.v"
                     (_format verilog)
-                    (_timespec "2024-03-25T17:37:50")
+                    (_timespec "2024-03-27T15:35:13")
                 )
                 (_file "source/src/zutils/zutils_pluse_delayer.v"
                     (_format verilog)
@@ -264,7 +264,7 @@
             (_input
                 (_file "led_test.fdc"
                     (_format fdc)
-                    (_timespec "2024-02-27T20:28:55")
+                    (_timespec "2024-03-27T14:50:54")
                 )
             )
         )
@@ -315,17 +315,17 @@
             (_db_output
                 (_file "compile/Top_comp.adf"
                     (_format adif)
-                    (_timespec "2024-03-26T22:07:42")
+                    (_timespec "2024-03-27T16:07:36")
                 )
             )
             (_output
                 (_file "compile/Top.cmr"
                     (_format verilog)
-                    (_timespec "2024-03-26T22:07:41")
+                    (_timespec "2024-03-27T16:07:33")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2024-03-26T22:07:42")
+                    (_timespec "2024-03-27T16:07:36")
                 )
             )
         )
@@ -341,21 +341,21 @@
             (_db_output
                 (_file "synthesize/Top_syn.adf"
                     (_format adif)
-                    (_timespec "2024-03-26T22:07:54")
+                    (_timespec "2024-03-27T16:09:41")
                 )
             )
             (_output
                 (_file "synthesize/Top_syn.vm"
                     (_format structural_verilog)
-                    (_timespec "2024-03-26T22:07:54")
+                    (_timespec "2024-03-27T16:09:50")
                 )
                 (_file "synthesize/Top.snr"
                     (_format text)
-                    (_timespec "2024-03-26T22:07:55")
+                    (_timespec "2024-03-27T16:09:56")
                 )
                 (_file "synthesize/snr.db"
                     (_format text)
-                    (_timespec "2024-03-26T22:07:55")
+                    (_timespec "2024-03-27T16:09:56")
                 )
             )
         )
@@ -376,21 +376,21 @@
             (_db_output
                 (_file "device_map/Top_map.adf"
                     (_format adif)
-                    (_timespec "2024-03-26T22:07:58")
+                    (_timespec "2024-03-27T16:10:02")
                 )
             )
             (_output
                 (_file "device_map/Top_dmr.prt"
                     (_format text)
-                    (_timespec "2024-03-26T22:07:57")
+                    (_timespec "2024-03-27T16:09:59")
                 )
                 (_file "device_map/Top.dmr"
                     (_format text)
-                    (_timespec "2024-03-26T22:07:58")
+                    (_timespec "2024-03-27T16:10:02")
                 )
                 (_file "device_map/dmr.db"
                     (_format text)
-                    (_timespec "2024-03-26T22:07:58")
+                    (_timespec "2024-03-27T16:10:02")
                 )
             )
         )
@@ -399,7 +399,7 @@
             (_input
                 (_file "device_map/led_test.pcf"
                     (_format pcf)
-                    (_timespec "2024-03-26T22:07:58")
+                    (_timespec "2024-03-27T16:10:02")
                 )
             )
         )
@@ -409,47 +409,14 @@
     )
     (_task tsk_pnr
         (_command cmd_pnr
-            (_gci_state (_integer 2))
+            (_gci_state (_integer 0))
             (_option gplace_seed (_integer 8))
             (_option seed_step (_integer 4))
             (_option saved_outcome (_integer 4))
             (_option parallel (_integer 4))
             (_option share_router_control_signal (_boolean FALSE))
             (_option check_clk_net_route_by_srb (_boolean FALSE))
-            (_option mode (_string "fast"))
             (_option fix_hold_violation_in_route (_boolean FALSE))
-            (_db_output
-                (_file "place_route/Top_pnr.adf"
-                    (_format adif)
-                    (_timespec "2024-03-26T22:08:18")
-                )
-            )
-            (_output
-                (_file "place_route/Top.prr"
-                    (_format text)
-                    (_timespec "2024-03-26T22:08:18")
-                )
-                (_file "place_route/Top_prr.prt"
-                    (_format text)
-                    (_timespec "2024-03-26T22:08:17")
-                )
-                (_file "place_route/clock_utilization.txt"
-                    (_format text)
-                    (_timespec "2024-03-26T22:08:17")
-                )
-                (_file "place_route/Top_plc.adf"
-                    (_format adif)
-                    (_timespec "2024-03-26T22:08:04")
-                )
-                (_file "place_route/Top_pnr.netlist"
-                    (_format text)
-                    (_timespec "2024-03-26T22:08:18")
-                )
-                (_file "place_route/prr.db"
-                    (_format text)
-                    (_timespec "2024-03-26T22:08:19")
-                )
-            )
         )
         (_widget wgt_power_calculator
             (_attribute _click_to_run (_switch ON))
@@ -458,24 +425,8 @@
             (_attribute _click_to_run (_switch ON))
         )
         (_command cmd_report_post_pnr_timing
-            (_gci_state (_integer 2))
+            (_gci_state (_integer 0))
             (_attribute _auto_exe_lock (_switch OFF))
-            (_db_output
-                (_file "report_timing/Top_rtp.adf"
-                    (_format adif)
-                    (_timespec "2024-03-26T22:08:23")
-                )
-            )
-            (_output
-                (_file "report_timing/Top.rtr"
-                    (_format text)
-                    (_timespec "2024-03-26T22:08:23")
-                )
-                (_file "report_timing/rtr.db"
-                    (_format text)
-                    (_timespec "2024-03-26T22:08:24")
-                )
-            )
         )
         (_widget wgt_arch_browser
             (_attribute _click_to_run (_switch ON))
@@ -493,25 +444,8 @@
     )
     (_task tsk_gen_bitstream
         (_command cmd_gen_bitstream
-            (_gci_state (_integer 2))
-            (_output
-                (_file "generate_bitstream/Top.sbit"
-                    (_format text)
-                    (_timespec "2024-03-26T22:08:38")
-                )
-                (_file "generate_bitstream/Top.smsk"
-                    (_format text)
-                    (_timespec "2024-03-26T22:08:38")
-                )
-                (_file "generate_bitstream/Top.bgr"
-                    (_format text)
-                    (_timespec "2024-03-26T22:08:38")
-                )
-                (_file "generate_bitstream/bgr.db"
-                    (_format text)
-                    (_timespec "2024-03-26T22:08:39")
-                )
-            )
+            (_gci_state (_integer 0))
+            (_option unused_io_status (_string "KEEPER"))
         )
     )
 )
diff --git a/rdfile_2024_3_26_21_12_43 b/rdfile_2024_3_26_21_12_43
new file mode 100644
index 0000000..9933f55
Binary files /dev/null and b/rdfile_2024_3_26_21_12_43 differ
diff --git a/source/src/internal/internal_clock_generator.v b/source/src/internal/internal_clock_generator.v
index cb602c1..9f10fab 100644
--- a/source/src/internal/internal_clock_generator.v
+++ b/source/src/internal/internal_clock_generator.v
@@ -45,7 +45,7 @@ module internal_clock_generator #(
     if (!rst_n) begin
       r1_contrl_mode <= 0;
       r2_en          <= 1;
-      r3_setting_cnt <= (32'd1_000_000 - 32'd1);
+      r3_setting_cnt <= (SYS_CLOCK_FREQ / 100 - 1);
     end else begin
       if (reg_wr_sig) begin
         case (reg_wr_index)
diff --git a/source/src/output/camera_sync_signal_output.v b/source/src/output/camera_sync_signal_output.v
index 041fcce..9326f98 100644
--- a/source/src/output/camera_sync_signal_output.v
+++ b/source/src/output/camera_sync_signal_output.v
@@ -46,6 +46,7 @@ module camera_sync_signal_output #(
       .reg1      (reg1_pulse_mode_valid_len),
       .reg2      (reg2_timecode_snapshot0),
       .reg3      (reg3_timecode_snapshot1),
+      .reg4      (reg4_sub_frame_cnt),
       .reg_wr_sig(reg_wr_sig),
       .reg_index (reg_wr_index)
   );
diff --git a/source/src/output/ttl_output.v b/source/src/output/ttl_output.v
index 8e3d7d0..bdf297b 100644
--- a/source/src/output/ttl_output.v
+++ b/source/src/output/ttl_output.v
@@ -149,15 +149,23 @@ module ttl_output #(
       .clk                (clk),
       .rst_n              (rst_n),
       .insignal           (signal_in_choose),
-      .trigger_eage_type  (reg6_pllout_trigger_edge_select[0]),
+      .trigger_eage_type  (reg6_pllout_trigger_edge_select),
       .freq_detect_bias   (reg9_freq_detect_bias),
       .freq_division      (reg3_pllout_freq_division_ctrl),
       .freq_multiplication(reg4_pllout_freq_multiplication_ctrl),
       .polarity_ctrl      (1'd0),
       .cfg_change         (reg_wr_sig),
-      // .outsignal          (signal_in_af_pll),
-      .output_trigger_sig (signal_in_af_pll_trigger_sig)
+      .outsignal          (signal_in_af_pll)
+      // .output_trigger_sig (signal_in_af_pll_trigger_sig)
   );
+
+  zutils_edge_detecter cs_edge_detecter (
+    .clk(clk),
+    .rst_n(rst_n),
+    .in_signal(signal_in_af_pll),
+    .in_signal_rising_edge(signal_in_af_pll_trigger_sig)
+);
+
   //!脉冲生成
   zutils_pluse_generator _pluse_generator (
       .clk          (clk),
@@ -168,7 +176,7 @@ module ttl_output #(
       .output_signal(signal_in_af_pll_raw)
   );
 
-  assign signal_in_af_pll = signal_in_af_pll_raw ^ reg5_pllout_polarity_ctrl[0];
+  assign signal_in_af_pll_af_pluse_gen = signal_in_af_pll_raw ^ reg5_pllout_polarity_ctrl[0];
 
   //!100HZ测试信号发生器
   // zutils_pwm_generator #(
@@ -189,7 +197,7 @@ module ttl_output #(
       .chooseindex(reg1_signal_process_mode),
       .signal0    (1'b0),
       .signal1    (1'b1),
-      .signal2    (signal_in_af_pll),
+      .signal2    (signal_in_af_pll_af_pluse_gen),
       .signal3    (signal_in_af_forward_mode_polarity_ctrl),
       .signal4    (1'b0),
       .signal5    (1'b0),
@@ -198,14 +206,13 @@ module ttl_output #(
       .signalout  (ttloutput)
   );
 
-  //
-  zutils_freq_detector_v2 in_freq_detector (
-      .clk             (clk),
-      .rst_n           (rst_n),
-      .freq_detect_bias(reg9_freq_detect_bias),
-      .pluse_input     (signal_in_choose),
-      .pluse_width_cnt (regE_sig_in_freq_detect)
-  );
+  // zutils_freq_detector_v2 in_freq_detector (
+  //     .clk             (clk),
+  //     .rst_n           (rst_n),
+  //     .freq_detect_bias(reg9_freq_detect_bias),
+  //     .pluse_input     (signal_in_choose),
+  //     .pluse_width_cnt (regE_sig_in_freq_detect)
+  // );
 
   zutils_freq_detector_v2 output_freq_detector (
       .clk             (clk),
diff --git a/source/src/sys/sys_clock.v b/source/src/sys/sys_clock.v
index 595703a..c8b0ea2 100644
--- a/source/src/sys/sys_clock.v
+++ b/source/src/sys/sys_clock.v
@@ -46,6 +46,7 @@ module sys_clock #(
       .reg2   (reg2_freq_division_ctrl),
       .reg3   (reg3_freq_multiplication_ctrl),
       .reg4   (reg4_freq_detect_bias),
+      .reg5   (reg5_trigger_edge_select),
 
       .regE      (regE_infreq_detect),
       .regF      (regF_outfreq_detect),
@@ -68,6 +69,7 @@ module sys_clock #(
           2: reg2_freq_division_ctrl <= wr_data;
           3: reg3_freq_multiplication_ctrl <= wr_data;
           4: reg4_freq_detect_bias <= wr_data;
+          5: reg5_trigger_edge_select <= wr_data;
           default: begin
           end
         endcase
@@ -87,7 +89,7 @@ module sys_clock #(
       .clk                (clk),
       .rst_n              (rst_n),
       .insignal           (signal_in_choose),
-      .trigger_eage_type  (reg5_trigger_edge_select[0]),
+      .trigger_eage_type  (reg5_trigger_edge_select),
       .freq_detect_bias   (reg4_freq_detect_bias),
       .freq_division      (reg2_freq_division_ctrl),
       .freq_multiplication(reg3_freq_multiplication_ctrl),
diff --git a/source/src/sys_signal_delayer.v b/source/src/sys_signal_delayer.v
index b0f9753..fc28794 100644
--- a/source/src/sys_signal_delayer.v
+++ b/source/src/sys_signal_delayer.v
@@ -43,50 +43,55 @@ module sys_signal_delayer #(
   integer m;
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
-      r1_ctrl_reg_index <= 32'hffff_ffff;
-      r2_delay_cnt_ctrl <= 0;
+      r1_ctrl_reg_index <= 0;
+      r2_delay_cnt_ctrl <= delay_ctrl[r1_ctrl_reg_index][31:0];
 
       for (m = 0; m <= SIG_BUS_WIDTH; m = m + 1) begin
         delay_ctrl[m] <= 0;
       end
-
       delayer_rst_n_ctrl <= 1;
     end else begin
-      if (reg_wr_sig) begin
-        case (reg_wr_index)
-          1: r1_ctrl_reg_index <= wr_data;
-          2: begin
-            if (r1_ctrl_reg_index <= SIG_BUS_WIDTH) begin
-              r2_delay_cnt_ctrl[r1_ctrl_reg_index] <= wr_data;
+
+      case (reg_wr_sig)
+        0: begin
+          delayer_rst_n_ctrl <= 1;
+          // r2_delay_cnt_ctrl  <= delay_ctrl[r1_ctrl_reg_index][31:0];
+        end
+        1: begin
+          delayer_rst_n_ctrl <= 0;
+          case (reg_wr_index)
+            1: begin
+              if (wr_data <= SIG_BUS_WIDTH) begin
+                r1_ctrl_reg_index <= wr_data;
+                r2_delay_cnt_ctrl <= delay_ctrl[wr_data][31:0];
+              end
             end
-          end
-          default: begin
-          end
-        endcase
-        delayer_rst_n_ctrl <= 0;
-      end else begin
-        delayer_rst_n_ctrl <= 1;
-      end
+            2: begin
+              delay_ctrl[r1_ctrl_reg_index][31:0] <= wr_data;
+              r2_delay_cnt_ctrl                   <= wr_data;
+            end
+          endcase
+        end
+      endcase
     end
   end
 
   assign delayer_rst_n = delayer_rst_n_ctrl & rst_n;
-  // genvar i;
-  // generate
-  //   for (i = 0; i <= SIG_BUS_WIDTH; i = i + 1) begin
-  //     // zutils_sig_delayer_v2 sig_delayer_inst (
-  //     //     .clk      (clk),
-  //     //     .rst_n    (delayer_rst_n),
-  //     //     .delay_cnt(delay_ctrl[i]),
-  //     //     .in       (sig_in[i]),
-  //     //     .out      (sig_out[i])
-  //     // );
-
-  //     assign sig_out[i] = sig_in[i];
-  //   end
-  // endgenerate
+  genvar i;
+  generate
+    for (i = 0; i <= SIG_BUS_WIDTH; i = i + 1) begin
+      zutils_sig_delayer_v2 sig_delayer_inst (
+          .clk      (clk),
+          .rst_n    (delayer_rst_n),
+          .delay_cnt(delay_ctrl[i]),
+          .in       (sig_in[i]),
+          .out      (sig_out[i])
+      );
+      // assign sig_out[i] = sig_in[i];
+    end
+  endgenerate
 
-  assign sig_out   = sig_in;
+  // assign sig_out   = sig_in;
 
 
 endmodule
diff --git a/source/src/top.v b/source/src/top.v
index abe3fbd..f126ed1 100644
--- a/source/src/top.v
+++ b/source/src/top.v
@@ -280,8 +280,8 @@ module Top (
   assign sys_sig_delay_in[3]             = sync_ttl_in4;  //
   assign sys_sig_delay_in[4]             = timecode_headphone_in;  //
   assign sys_sig_delay_in[5]             = timecode_bnc_in;  //
-  assign sys_sig_delay_in[6]             = genlock_in_hsync;  //
   assign sys_sig_delay_in[7]             = genlock_in_vsync;  //
+  assign sys_sig_delay_in[6]             = genlock_in_hsync;  //
   assign sys_sig_delay_in[8]             = genlock_in_fsync;  //
   assign sys_sig_delay_in[9]             = before_delay__sync_ttl_out1;  //
   assign sys_sig_delay_in[10]            = before_delay__sync_ttl_out2;  //
@@ -297,8 +297,8 @@ module Top (
   assign af_delay__sync_ttl_in4          = sys_sig_delay_out[3];
   assign af_delay__timecode_headphone_in = sys_sig_delay_out[4];
   assign af_delay__timecode_bnc_in       = sys_sig_delay_out[5];
-  assign af_delay__genlock_in_hsync      = sys_sig_delay_out[6];
   assign af_delay__genlock_in_vsync      = sys_sig_delay_out[7];
+  assign af_delay__genlock_in_hsync      = sys_sig_delay_out[6];
   assign af_delay__genlock_in_fsync      = sys_sig_delay_out[8];
   assign sync_ttl_out1                   = sys_sig_delay_out[9];
   assign sync_ttl_out2                   = sys_sig_delay_out[10];
@@ -312,7 +312,8 @@ module Top (
 
   sys_signal_delayer #(
       .REG_START_ADD (`REGADDOFF__DELAYER),
-      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
+      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
+      .SIG_BUS_WIDTH(15)
   ) sys_signal_delayer_ins (
       .clk  (sys_clk),
       .rst_n(sys_rst_n),
@@ -328,6 +329,7 @@ module Top (
 
 
 
+
   internal_sig_generator_en_contrler #(
       .REG_START_ADD (`REGADDOFF__INTERNAL_SIG_EN_CONTRLER),
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
@@ -451,12 +453,9 @@ module Top (
   );
 
 
-  //    
-
 
 
 
-  /*
   genlock_input_module #(
       .REG_START_ADD (`REGADDOFF__GENLOCK_IN),
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
@@ -493,6 +492,24 @@ module Top (
 
       .genlock_freq_signal(signal_internal_genlock_freq)
   );
+  
+  sys_genlock #(
+      .REG_START_ADD (`REGADDOFF__SYS_GENLOCK),
+      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
+  ) sys_genlock0 (
+      .clk  (sys_clk),
+      .rst_n(sys_rst_n),
+
+      .addr   (RegReaderBus_addr),
+      .wr_data(RegReaderBus_wr_data),
+      .wr_en  (RegReaderBus_wr_en),
+      .rd_data(rd_data_module_sys_genlock),
+
+      .internal_genlock_sig(signal_internal_genlock_freq),
+      .external_genlock_sig(signal_ext_genlock_freq),
+
+      .sys_genlock_tigger_sig(signal_sys_genlock_output)
+  );
 
   internal_clock_generator #(
       .REG_START_ADD (`REGADDOFF__INTERNAL_CLOCK),
@@ -542,23 +559,6 @@ module Top (
   );
 
 
-  sys_genlock #(
-      .REG_START_ADD (`REGADDOFF__SYS_GENLOCK),
-      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
-  ) sys_genlock0 (
-      .clk  (sys_clk),
-      .rst_n(sys_rst_n),
-
-      .addr   (RegReaderBus_addr),
-      .wr_data(RegReaderBus_wr_data),
-      .wr_en  (RegReaderBus_wr_en),
-      .rd_data(rd_data_module_sys_genlock),
-
-      .internal_genlock_sig(signal_internal_genlock_freq),
-      .external_genlock_sig(signal_ext_genlock_freq),
-
-      .sys_genlock_tigger_sig(signal_sys_genlock_output)
-  );
   sys_clock #(
       .REG_START_ADD (`REGADDOFF__SYS_CLOCK),
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
@@ -576,32 +576,31 @@ module Top (
   );
 
   camera_sync_signal_output #(
-    .REG_START_ADD (`REGADDOFF__CAMERA_SYNC_OUT),
-    .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
-) camera_sync_signal_output0 (
-    .clk  (sys_clk),
-    .rst_n(sys_rst_n),
-
-    .addr   (RegReaderBus_addr),
-    .wr_data(RegReaderBus_wr_data),
-    .wr_en  (RegReaderBus_wr_en),
-    .rd_data(rd_data_module_camera_sync_out),
-
-    .in_timecode_tigger_sig (sys_timecode_tigger_sig),
-    .in_timecode_format     (sys_timecode_format),
-    .in_timecode_data       (sys_timecode_data),
-    .in_timecode_serial_data(sys_timecode_serial_data),
+      .REG_START_ADD (`REGADDOFF__CAMERA_SYNC_OUT),
+      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
+  ) camera_sync_signal_output0 (
+      .clk  (sys_clk),
+      .rst_n(sys_rst_n),
 
-    .frame_sig    (signal_sys_clk_output),
-    .record_en_sig(signal_business_record_en_sig),
+      .addr   (RegReaderBus_addr),
+      .wr_data(RegReaderBus_wr_data),
+      .wr_en  (RegReaderBus_wr_en),
+      .rd_data(rd_data_module_camera_sync_out),
 
+      .in_timecode_tigger_sig (sys_timecode_tigger_sig),
+      .in_timecode_format     (sys_timecode_format),
+      .in_timecode_data       (sys_timecode_data),
+      .in_timecode_serial_data(sys_timecode_serial_data),
 
-    .stm32if_camera_sync_out        (before_delay__stm32if_camera_sync_out),
-    .stm32if_record_state_change_sig(before_delay__stm32if_start_signal_out),
-    .stm32if_timecode_tigger_sig    (before_delay__stm32if_timecode_sync_out)
-);
+      .frame_sig    (signal_sys_clk_output),
+      .record_en_sig(signal_business_record_en_sig),
 
 
+      .stm32if_camera_sync_out        (before_delay__stm32if_camera_sync_out),
+      .stm32if_record_state_change_sig(before_delay__stm32if_start_signal_out),
+      .stm32if_timecode_tigger_sig    (before_delay__stm32if_timecode_sync_out)
+  );
+  // /*
 
   ttl_output #(
       .REG_START_ADD(`REGADDOFF__TTLOUT1),
@@ -621,7 +620,6 @@ module Top (
       .ttloutput          (before_delay__sync_ttl_out1),
       .ttloutput_state_led(sync_ttl_out1_state_led)
   );
-
   ttl_output #(
       .REG_START_ADD(`REGADDOFF__TTLOUT2),
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
@@ -640,6 +638,9 @@ module Top (
       .ttloutput          (before_delay__sync_ttl_out2),
       .ttloutput_state_led(sync_ttl_out2_state_led)
   );
+
+/*
+
   ttl_output #(
       .REG_START_ADD(`REGADDOFF__TTLOUT3),
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
@@ -658,6 +659,7 @@ module Top (
       .ttloutput          (before_delay__sync_ttl_out3),
       .ttloutput_state_led(sync_ttl_out3_state_led)
   );
+*/
 
   ttl_output #(
       .REG_START_ADD(`REGADDOFF__TTLOUT4),
@@ -679,7 +681,6 @@ module Top (
   );
 
 
-
   record_sig_generator #(
       .REG_START_ADD(`REGADDOFF__RECORD_SIG_GENERATOR),
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
@@ -710,25 +711,24 @@ module Top (
       .out_record_en_sig      (signal_business_record_en_sig),
       .out_record_exposure_sig(signal_business_record_exposure_sig)
   );
-  */
-
-
-
-  assign debug_signal_output[0]  = timecode_bnc_in;
-  assign debug_signal_output[1]  = af_delay__timecode_headphone_in;
-  assign debug_signal_output[2]  = timecode_is_detected;
-  assign debug_signal_output[3]  = timecode_is_detected;
-  assign debug_signal_output[4]  = sync_ttl_in1;
-  //   assign debug_signal_output[5]  = af_delay__sync_ttl_in1;
-  //   assign debug_signal_output[6]  = af_delay__sync_ttl_in1;
-  //   assign debug_signal_output[7]  = af_delay__sync_ttl_in1;
-  //   assign debug_signal_output[8]  = af_delay__sync_ttl_in1;
-  //   assign debug_signal_output[9]  = af_delay__genlock_in_vsync;
-  //   assign debug_signal_output[10] = af_delay__timecode_headphone_in;
-  //   assign debug_signal_output[11] = af_delay__timecode_bnc_in;
-  assign debug_signal_output[12] = timecode_out_headphone;
-  assign debug_signal_output[13] = timecode_out_bnc;
-  assign debug_signal_output[15] = 0;
+
+
+
+  assign debug_signal_output[0]  = sys_clk;
+  assign debug_signal_output[1]  = af_delay__sync_ttl_in3;
+  assign debug_signal_output[2]  = af_delay__sync_ttl_in2;
+  assign debug_signal_output[3]  = genlock_in_vsync;
+  assign debug_signal_output[4]  = af_delay__genlock_in_vsync;
+  assign debug_signal_output[5]  = timecode_headphone_in | timecode_bnc_in;
+  assign debug_signal_output[6]  = af_delay__timecode_headphone_in | af_delay__timecode_bnc_in;
+  assign debug_signal_output[7]  = sync_ttl_out1;
+  assign debug_signal_output[8]  = sync_ttl_out2;
+  assign debug_signal_output[9]  = sync_ttl_out3;
+  assign debug_signal_output[10] = sync_ttl_out4;
+  assign debug_signal_output[11] = sync_ttl_in1;
+  assign debug_signal_output[12] = sync_ttl_in2;
+  assign debug_signal_output[13] = sync_ttl_in3;
+  assign debug_signal_output[15] = sync_ttl_in4;
 
 
 endmodule
diff --git a/source/src/zutils/zsimple_pll.v b/source/src/zutils/zsimple_pll.v
index bf74a65..329be95 100644
--- a/source/src/zutils/zsimple_pll.v
+++ b/source/src/zutils/zsimple_pll.v
@@ -3,14 +3,13 @@ module zsimple_pll (
     input rst_n, //!asynchronous reset input, low active
 
     input              insignal,             //!输入信号
-    input              trigger_eage_type,
+    input  wire [31:0] trigger_eage_type,
     input  wire [31:0] freq_detect_bias,     //! 频率偏差计数
     input  wire [31:0] freq_division,
     input  wire [31:0] freq_multiplication,
     input  wire        polarity_ctrl,
     input  wire        cfg_change,
-    output wire        outsignal,
-    output reg         output_trigger_sig
+    output wire        outsignal
 );
 
   //
@@ -27,7 +26,7 @@ module zsimple_pll (
 
   wire insignal_rising_edge;  //! 输入信号上升沿
   wire insignal_falling_edge;  //! 输入信号下降沿
-  reg insignal_trigger_sig;  //! 触发信号
+  reg  insignal_trigger_sig;  //! 触发信号
   wire module_reset;  //! 模块内部复位信号
 
   reg  insignal_division;  //! 输入信号分频后的信号
@@ -46,16 +45,15 @@ module zsimple_pll (
 
   always @(*) begin
     case (trigger_eage_type)
-      0: insignal_trigger_sig <= insignal_rising_edge;
-      1: insignal_trigger_sig <= insignal_rising_edge;
-      2: insignal_trigger_sig <= insignal_rising_edge;
-      default: 
-      insignal_trigger_sig <= insignal_rising_edge;
+      0:       insignal_trigger_sig <= insignal_rising_edge;
+      1:       insignal_trigger_sig <= insignal_falling_edge;
+      2:       insignal_trigger_sig <= insignal_rising_edge | insignal_falling_edge;
+      default: insignal_trigger_sig <= insignal_rising_edge;
     endcase
   end
 
   // assign insignal_trigger_sig = trigger_eage_type ? insignal_rising_edge : insignal_falling_edge;
-  assign module_reset         = !rst_n || cfg_change;
+  assign module_reset = !rst_n || cfg_change;
 
   // 分频
   reg [31:0] insignal_division_cnt;
@@ -101,7 +99,6 @@ module zsimple_pll (
       multiplication_state    <= 0;
       gen_pluse_cnt           <= 0;
       insignal_multiplication <= 0;
-      output_trigger_sig      <= 0;
     end else begin
       case (multiplication_state)
         0: begin
@@ -118,7 +115,6 @@ module zsimple_pll (
             multiplication_state    <= 2;
             gen_pluse_cnt           <= 0;
             insignal_multiplication <= 1;
-            output_trigger_sig      <= 1;
             multiplication_cnt      <= 0;
           end
         end
@@ -126,15 +122,12 @@ module zsimple_pll (
           if (multiplication_cnt < insignal_multiplication_freq_cnt >> 1) begin
             multiplication_cnt      <= multiplication_cnt + freq_multiplication + 1;
             insignal_multiplication <= 1;
-            output_trigger_sig      <= 0;
           end else if ((multiplication_cnt + freq_multiplication + 2) >= insignal_multiplication_freq_cnt) begin
             gen_pluse_cnt           <= gen_pluse_cnt + 1;
             multiplication_cnt      <= 0;
             insignal_multiplication <= 1;
-            output_trigger_sig      <= 1;
             gen_pluse_cnt           <= gen_pluse_cnt + 1;
           end else begin
-            output_trigger_sig <= 0;
             if (gen_pluse_cnt >= freq_multiplication) begin
               multiplication_state    <= 1;
               insignal_multiplication <= 0;
diff --git a/source/src/zutils/zutils_sig_delayer_v2.v b/source/src/zutils/zutils_sig_delayer_v2.v
index 6619e85..04ba89f 100644
--- a/source/src/zutils/zutils_sig_delayer_v2.v
+++ b/source/src/zutils/zutils_sig_delayer_v2.v
@@ -125,6 +125,7 @@ module zutils_sig_delayer_v2 (
 endmodule
 */
 
+// /*
 module zutils_sig_delayer_v2 (
     input clk,
     input rst_n,
@@ -139,3 +140,4 @@ module zutils_sig_delayer_v2 (
   assign out = in;
 
 endmodule
+// */