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xsync_fpge_v2
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V3

master
zhaohe 1 year ago
parent
2a2f0c530f
commit
67d20ba766
11 changed files with 169 additions and 219 deletions
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  1. 6
      led_test.fdc
  2. 118
      led_test.pds
  3. BIN
      rdfile_2024_3_26_21_12_43
  4. 2
      source/src/internal/internal_clock_generator.v
  5. 1
      source/src/output/camera_sync_signal_output.v
  6. 33
      source/src/output/ttl_output.v
  7. 4
      source/src/sys/sys_clock.v
  8. 57
      source/src/sys_signal_delayer.v
  9. 86
      source/src/top.v
  10. 17
      source/src/zutils/zsimple_pll.v
  11. 2
      source/src/zutils/zutils_sig_delayer_v2.v

6
led_test.fdc
View File

@ -573,3 +573,9 @@ define_attribute {p:ex_rst_n} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:ex_rst_n} {PAP_IO_LOC} {C13}
define_attribute {p:ex_rst_n} {PAP_IO_VCCIO} {3.3}
define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:sync_ttl_in1} {PAP_IO_PULLDW} {TRUE}
define_attribute {p:sync_ttl_in2} {PAP_IO_PULLDW} {TRUE}
define_attribute {p:sync_ttl_in3} {PAP_IO_PULLDW} {TRUE}
define_attribute {p:sync_ttl_in4} {PAP_IO_PULLDW} {TRUE}
define_attribute {p:timecode_bnc_in} {PAP_IO_PULLDW} {TRUE}
define_attribute {p:timecode_headphone_in} {PAP_IO_PULLDW} {TRUE}

118
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Mar 26 22:08:39 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Wed Mar 27 16:10:02 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-03-26T22:07:22")
(_timespec "2024-03-27T15:36:20")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -59,7 +59,7 @@
)
(_file "source/src/output/ttl_output.v"
(_format verilog)
(_timespec "2024-03-25T14:05:59")
(_timespec "2024-03-27T16:06:42")
)
(_file "source/src/zutils/zutils_pwm_generator.v"
(_format verilog)
@ -163,7 +163,7 @@
)
(_file "source/src/zutils/zsimple_pll.v"
(_format verilog)
(_timespec "2024-03-26T18:46:59")
(_timespec "2024-03-27T12:48:00")
)
(_file "source/src/zutils/zutils_freq_detector_v2.v"
(_format verilog)
@ -191,7 +191,7 @@
)
(_file "source/src/internal/internal_clock_generator.v"
(_format verilog)
(_timespec "2024-03-23T16:38:57")
(_timespec "2024-03-27T12:08:29")
)
(_file "source/src/internal/internal_genlock_generator.v"
(_format verilog)
@ -203,11 +203,11 @@
)
(_file "source/src/sys/sys_clock.v"
(_format verilog)
(_timespec "2024-03-05T16:10:23")
(_timespec "2024-03-27T12:19:38")
)
(_file "source/src/output/camera_sync_signal_output.v"
(_format verilog)
(_timespec "2024-03-26T16:56:33")
(_timespec "2024-03-27T12:07:13")
)
(_file "source/src/business/record_sig_generator.v"
(_format verilog)
@ -215,7 +215,7 @@
)
(_file "source/src/sys_signal_delayer.v"
(_format verilog)
(_timespec "2024-03-26T21:16:17")
(_timespec "2024-03-27T14:18:37")
)
(_file "source/src/zutils/zutils_sig_delayer.v"
(_format verilog)
@ -223,7 +223,7 @@
)
(_file "source/src/zutils/zutils_sig_delayer_v2.v"
(_format verilog)
(_timespec "2024-03-25T17:37:50")
(_timespec "2024-03-27T15:35:13")
)
(_file "source/src/zutils/zutils_pluse_delayer.v"
(_format verilog)
@ -264,7 +264,7 @@
(_input
(_file "led_test.fdc"
(_format fdc)
(_timespec "2024-02-27T20:28:55")
(_timespec "2024-03-27T14:50:54")
)
)
)
@ -315,17 +315,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-03-26T22:07:42")
(_timespec "2024-03-27T16:07:36")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-03-26T22:07:41")
(_timespec "2024-03-27T16:07:33")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-03-26T22:07:42")
(_timespec "2024-03-27T16:07:36")
)
)
)
@ -341,21 +341,21 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-03-26T22:07:54")
(_timespec "2024-03-27T16:09:41")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-03-26T22:07:54")
(_timespec "2024-03-27T16:09:50")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-03-26T22:07:55")
(_timespec "2024-03-27T16:09:56")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-03-26T22:07:55")
(_timespec "2024-03-27T16:09:56")
)
)
)
@ -376,21 +376,21 @@
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-03-26T22:07:58")
(_timespec "2024-03-27T16:10:02")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-03-26T22:07:57")
(_timespec "2024-03-27T16:09:59")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-03-26T22:07:58")
(_timespec "2024-03-27T16:10:02")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-03-26T22:07:58")
(_timespec "2024-03-27T16:10:02")
)
)
)
@ -399,7 +399,7 @@
(_input
(_file "device_map/led_test.pcf"
(_format pcf)
(_timespec "2024-03-26T22:07:58")
(_timespec "2024-03-27T16:10:02")
)
)
)
@ -409,47 +409,14 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 2))
(_gci_state (_integer 0))
(_option gplace_seed (_integer 8))
(_option seed_step (_integer 4))
(_option saved_outcome (_integer 4))
(_option parallel (_integer 4))
(_option share_router_control_signal (_boolean FALSE))
(_option check_clk_net_route_by_srb (_boolean FALSE))
(_option mode (_string "fast"))
(_option fix_hold_violation_in_route (_boolean FALSE))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-03-26T22:08:18")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-03-26T22:08:18")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-03-26T22:08:17")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-03-26T22:08:17")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-03-26T22:08:04")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-03-26T22:08:18")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-03-26T22:08:19")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -458,24 +425,8 @@
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 2))
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_db_output
(_file "report_timing/Top_rtp.adf"
(_format adif)
(_timespec "2024-03-26T22:08:23")
)
)
(_output
(_file "report_timing/Top.rtr"
(_format text)
(_timespec "2024-03-26T22:08:23")
)
(_file "report_timing/rtr.db"
(_format text)
(_timespec "2024-03-26T22:08:24")
)
)
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
@ -493,25 +444,8 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 2))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-03-26T22:08:38")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-03-26T22:08:38")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-03-26T22:08:38")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-03-26T22:08:39")
)
)
(_gci_state (_integer 0))
(_option unused_io_status (_string "KEEPER"))
)
)
)

BIN
rdfile_2024_3_26_21_12_43
View File

2
source/src/internal/internal_clock_generator.v
View File

@ -45,7 +45,7 @@ module internal_clock_generator #(
if (!rst_n) begin
r1_contrl_mode <= 0;
r2_en <= 1;
r3_setting_cnt <= (32'd1_000_000 - 32'd1);
r3_setting_cnt <= (SYS_CLOCK_FREQ / 100 - 1);
end else begin
if (reg_wr_sig) begin
case (reg_wr_index)

1
source/src/output/camera_sync_signal_output.v
View File

@ -46,6 +46,7 @@ module camera_sync_signal_output #(
.reg1 (reg1_pulse_mode_valid_len),
.reg2 (reg2_timecode_snapshot0),
.reg3 (reg3_timecode_snapshot1),
.reg4 (reg4_sub_frame_cnt),
.reg_wr_sig(reg_wr_sig),
.reg_index (reg_wr_index)
);

33
source/src/output/ttl_output.v
View File

@ -149,15 +149,23 @@ module ttl_output #(
.clk (clk),
.rst_n (rst_n),
.insignal (signal_in_choose),
.trigger_eage_type (reg6_pllout_trigger_edge_select[0]),
.trigger_eage_type (reg6_pllout_trigger_edge_select),
.freq_detect_bias (reg9_freq_detect_bias),
.freq_division (reg3_pllout_freq_division_ctrl),
.freq_multiplication(reg4_pllout_freq_multiplication_ctrl),
.polarity_ctrl (1'd0),
.cfg_change (reg_wr_sig),
// .outsignal (signal_in_af_pll),
.output_trigger_sig (signal_in_af_pll_trigger_sig)
.outsignal (signal_in_af_pll)
// .output_trigger_sig (signal_in_af_pll_trigger_sig)
);
zutils_edge_detecter cs_edge_detecter (
.clk(clk),
.rst_n(rst_n),
.in_signal(signal_in_af_pll),
.in_signal_rising_edge(signal_in_af_pll_trigger_sig)
);
//!脉冲生成
zutils_pluse_generator _pluse_generator (
.clk (clk),
@ -168,7 +176,7 @@ module ttl_output #(
.output_signal(signal_in_af_pll_raw)
);
assign signal_in_af_pll = signal_in_af_pll_raw ^ reg5_pllout_polarity_ctrl[0];
assign signal_in_af_pll_af_pluse_gen = signal_in_af_pll_raw ^ reg5_pllout_polarity_ctrl[0];
//!100HZ测试信号发生器
// zutils_pwm_generator #(
@ -189,7 +197,7 @@ module ttl_output #(
.chooseindex(reg1_signal_process_mode),
.signal0 (1'b0),
.signal1 (1'b1),
.signal2 (signal_in_af_pll),
.signal2 (signal_in_af_pll_af_pluse_gen),
.signal3 (signal_in_af_forward_mode_polarity_ctrl),
.signal4 (1'b0),
.signal5 (1'b0),
@ -198,14 +206,13 @@ module ttl_output #(
.signalout (ttloutput)
);
//
zutils_freq_detector_v2 in_freq_detector (
.clk (clk),
.rst_n (rst_n),
.freq_detect_bias(reg9_freq_detect_bias),
.pluse_input (signal_in_choose),
.pluse_width_cnt (regE_sig_in_freq_detect)
);
// zutils_freq_detector_v2 in_freq_detector (
// .clk (clk),
// .rst_n (rst_n),
// .freq_detect_bias(reg9_freq_detect_bias),
// .pluse_input (signal_in_choose),
// .pluse_width_cnt (regE_sig_in_freq_detect)
// );
zutils_freq_detector_v2 output_freq_detector (
.clk (clk),

4
source/src/sys/sys_clock.v
View File

@ -46,6 +46,7 @@ module sys_clock #(
.reg2 (reg2_freq_division_ctrl),
.reg3 (reg3_freq_multiplication_ctrl),
.reg4 (reg4_freq_detect_bias),
.reg5 (reg5_trigger_edge_select),
.regE (regE_infreq_detect),
.regF (regF_outfreq_detect),
@ -68,6 +69,7 @@ module sys_clock #(
2: reg2_freq_division_ctrl <= wr_data;
3: reg3_freq_multiplication_ctrl <= wr_data;
4: reg4_freq_detect_bias <= wr_data;
5: reg5_trigger_edge_select <= wr_data;
default: begin
end
endcase
@ -87,7 +89,7 @@ module sys_clock #(
.clk (clk),
.rst_n (rst_n),
.insignal (signal_in_choose),
.trigger_eage_type (reg5_trigger_edge_select[0]),
.trigger_eage_type (reg5_trigger_edge_select),
.freq_detect_bias (reg4_freq_detect_bias),
.freq_division (reg2_freq_division_ctrl),
.freq_multiplication(reg3_freq_multiplication_ctrl),

57
source/src/sys_signal_delayer.v
View File

@ -43,50 +43,55 @@ module sys_signal_delayer #(
integer m;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
r1_ctrl_reg_index <= 32'hffff_ffff;
r2_delay_cnt_ctrl <= 0;
r1_ctrl_reg_index <= 0;
r2_delay_cnt_ctrl <= delay_ctrl[r1_ctrl_reg_index][31:0];
for (m = 0; m <= SIG_BUS_WIDTH; m = m + 1) begin
delay_ctrl[m] <= 0;
end
delayer_rst_n_ctrl <= 1;
end else begin
if (reg_wr_sig) begin
case (reg_wr_sig)
0: begin
delayer_rst_n_ctrl <= 1;
// r2_delay_cnt_ctrl <= delay_ctrl[r1_ctrl_reg_index][31:0];
end
1: begin
delayer_rst_n_ctrl <= 0;
case (reg_wr_index)
1: r1_ctrl_reg_index <= wr_data;
2: begin
if (r1_ctrl_reg_index <= SIG_BUS_WIDTH) begin
r2_delay_cnt_ctrl[r1_ctrl_reg_index] <= wr_data;
1: begin
if (wr_data <= SIG_BUS_WIDTH) begin
r1_ctrl_reg_index <= wr_data;
r2_delay_cnt_ctrl <= delay_ctrl[wr_data][31:0];
end
end
default: begin
2: begin
delay_ctrl[r1_ctrl_reg_index][31:0] <= wr_data;
r2_delay_cnt_ctrl <= wr_data;
end
endcase
delayer_rst_n_ctrl <= 0;
end else begin
delayer_rst_n_ctrl <= 1;
end
endcase
end
end
assign delayer_rst_n = delayer_rst_n_ctrl & rst_n;
// genvar i;
// generate
// for (i = 0; i <= SIG_BUS_WIDTH; i = i + 1) begin
// // zutils_sig_delayer_v2 sig_delayer_inst (
// // .clk (clk),
// // .rst_n (delayer_rst_n),
// // .delay_cnt(delay_ctrl[i]),
// // .in (sig_in[i]),
// // .out (sig_out[i])
// // );
genvar i;
generate
for (i = 0; i <= SIG_BUS_WIDTH; i = i + 1) begin
zutils_sig_delayer_v2 sig_delayer_inst (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt(delay_ctrl[i]),
.in (sig_in[i]),
.out (sig_out[i])
);
// assign sig_out[i] = sig_in[i];
// end
// endgenerate
end
endgenerate
assign sig_out = sig_in;
// assign sig_out = sig_in;
endmodule

86
source/src/top.v
View File

@ -280,8 +280,8 @@ module Top (
assign sys_sig_delay_in[3] = sync_ttl_in4; //
assign sys_sig_delay_in[4] = timecode_headphone_in; //
assign sys_sig_delay_in[5] = timecode_bnc_in; //
assign sys_sig_delay_in[6] = genlock_in_hsync; //
assign sys_sig_delay_in[7] = genlock_in_vsync; //
assign sys_sig_delay_in[6] = genlock_in_hsync; //
assign sys_sig_delay_in[8] = genlock_in_fsync; //
assign sys_sig_delay_in[9] = before_delay__sync_ttl_out1; //
assign sys_sig_delay_in[10] = before_delay__sync_ttl_out2; //
@ -297,8 +297,8 @@ module Top (
assign af_delay__sync_ttl_in4 = sys_sig_delay_out[3];
assign af_delay__timecode_headphone_in = sys_sig_delay_out[4];
assign af_delay__timecode_bnc_in = sys_sig_delay_out[5];
assign af_delay__genlock_in_hsync = sys_sig_delay_out[6];
assign af_delay__genlock_in_vsync = sys_sig_delay_out[7];
assign af_delay__genlock_in_hsync = sys_sig_delay_out[6];
assign af_delay__genlock_in_fsync = sys_sig_delay_out[8];
assign sync_ttl_out1 = sys_sig_delay_out[9];
assign sync_ttl_out2 = sys_sig_delay_out[10];
@ -312,7 +312,8 @@ module Top (
sys_signal_delayer #(
.REG_START_ADD (`REGADDOFF__DELAYER),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.SIG_BUS_WIDTH(15)
) sys_signal_delayer_ins (
.clk (sys_clk),
.rst_n(sys_rst_n),
@ -328,6 +329,7 @@ module Top (
internal_sig_generator_en_contrler #(
.REG_START_ADD (`REGADDOFF__INTERNAL_SIG_EN_CONTRLER),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
@ -451,12 +453,9 @@ module Top (
);
//
/*
genlock_input_module #(
.REG_START_ADD (`REGADDOFF__GENLOCK_IN),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
@ -494,6 +493,24 @@ module Top (
.genlock_freq_signal(signal_internal_genlock_freq)
);
sys_genlock #(
.REG_START_ADD (`REGADDOFF__SYS_GENLOCK),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) sys_genlock0 (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr (RegReaderBus_addr),
.wr_data(RegReaderBus_wr_data),
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_sys_genlock),
.internal_genlock_sig(signal_internal_genlock_freq),
.external_genlock_sig(signal_ext_genlock_freq),
.sys_genlock_tigger_sig(signal_sys_genlock_output)
);
internal_clock_generator #(
.REG_START_ADD (`REGADDOFF__INTERNAL_CLOCK),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
@ -542,23 +559,6 @@ module Top (
);
sys_genlock #(
.REG_START_ADD (`REGADDOFF__SYS_GENLOCK),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) sys_genlock0 (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr (RegReaderBus_addr),
.wr_data(RegReaderBus_wr_data),
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_sys_genlock),
.internal_genlock_sig(signal_internal_genlock_freq),
.external_genlock_sig(signal_ext_genlock_freq),
.sys_genlock_tigger_sig(signal_sys_genlock_output)
);
sys_clock #(
.REG_START_ADD (`REGADDOFF__SYS_CLOCK),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
@ -600,8 +600,7 @@ module Top (
.stm32if_record_state_change_sig(before_delay__stm32if_start_signal_out),
.stm32if_timecode_tigger_sig (before_delay__stm32if_timecode_sync_out)
);
// /*
ttl_output #(
.REG_START_ADD(`REGADDOFF__TTLOUT1),
@ -621,7 +620,6 @@ module Top (
.ttloutput (before_delay__sync_ttl_out1),
.ttloutput_state_led(sync_ttl_out1_state_led)
);
ttl_output #(
.REG_START_ADD(`REGADDOFF__TTLOUT2),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
@ -640,6 +638,9 @@ module Top (
.ttloutput (before_delay__sync_ttl_out2),
.ttloutput_state_led(sync_ttl_out2_state_led)
);
/*
ttl_output #(
.REG_START_ADD(`REGADDOFF__TTLOUT3),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
@ -658,6 +659,7 @@ module Top (
.ttloutput (before_delay__sync_ttl_out3),
.ttloutput_state_led(sync_ttl_out3_state_led)
);
*/
ttl_output #(
.REG_START_ADD(`REGADDOFF__TTLOUT4),
@ -679,7 +681,6 @@ module Top (
);
record_sig_generator #(
.REG_START_ADD(`REGADDOFF__RECORD_SIG_GENERATOR),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
@ -710,25 +711,24 @@ module Top (
.out_record_en_sig (signal_business_record_en_sig),
.out_record_exposure_sig(signal_business_record_exposure_sig)
);
*/
assign debug_signal_output[0] = timecode_bnc_in;
assign debug_signal_output[1] = af_delay__timecode_headphone_in;
assign debug_signal_output[2] = timecode_is_detected;
assign debug_signal_output[3] = timecode_is_detected;
assign debug_signal_output[4] = sync_ttl_in1;
// assign debug_signal_output[5] = af_delay__sync_ttl_in1;
// assign debug_signal_output[6] = af_delay__sync_ttl_in1;
// assign debug_signal_output[7] = af_delay__sync_ttl_in1;
// assign debug_signal_output[8] = af_delay__sync_ttl_in1;
// assign debug_signal_output[9] = af_delay__genlock_in_vsync;
// assign debug_signal_output[10] = af_delay__timecode_headphone_in;
// assign debug_signal_output[11] = af_delay__timecode_bnc_in;
assign debug_signal_output[12] = timecode_out_headphone;
assign debug_signal_output[13] = timecode_out_bnc;
assign debug_signal_output[15] = 0;
assign debug_signal_output[0] = sys_clk;
assign debug_signal_output[1] = af_delay__sync_ttl_in3;
assign debug_signal_output[2] = af_delay__sync_ttl_in2;
assign debug_signal_output[3] = genlock_in_vsync;
assign debug_signal_output[4] = af_delay__genlock_in_vsync;
assign debug_signal_output[5] = timecode_headphone_in | timecode_bnc_in;
assign debug_signal_output[6] = af_delay__timecode_headphone_in | af_delay__timecode_bnc_in;
assign debug_signal_output[7] = sync_ttl_out1;
assign debug_signal_output[8] = sync_ttl_out2;
assign debug_signal_output[9] = sync_ttl_out3;
assign debug_signal_output[10] = sync_ttl_out4;
assign debug_signal_output[11] = sync_ttl_in1;
assign debug_signal_output[12] = sync_ttl_in2;
assign debug_signal_output[13] = sync_ttl_in3;
assign debug_signal_output[15] = sync_ttl_in4;
endmodule

17
source/src/zutils/zsimple_pll.v
View File

@ -3,14 +3,13 @@ module zsimple_pll (
input rst_n, //!asynchronous reset input, low active
input insignal, //!输入信号
input trigger_eage_type,
input wire [31:0] trigger_eage_type,
input wire [31:0] freq_detect_bias, //! 频率偏差计数
input wire [31:0] freq_division,
input wire [31:0] freq_multiplication,
input wire polarity_ctrl,
input wire cfg_change,
output wire outsignal,
output reg output_trigger_sig
output wire outsignal
);
//
@ -47,10 +46,9 @@ module zsimple_pll (
always @(*) begin
case (trigger_eage_type)
0: insignal_trigger_sig <= insignal_rising_edge;
1: insignal_trigger_sig <= insignal_rising_edge;
2: insignal_trigger_sig <= insignal_rising_edge;
default:
insignal_trigger_sig <= insignal_rising_edge;
1: insignal_trigger_sig <= insignal_falling_edge;
2: insignal_trigger_sig <= insignal_rising_edge | insignal_falling_edge;
default: insignal_trigger_sig <= insignal_rising_edge;
endcase
end
@ -101,7 +99,6 @@ module zsimple_pll (
multiplication_state <= 0;
gen_pluse_cnt <= 0;
insignal_multiplication <= 0;
output_trigger_sig <= 0;
end else begin
case (multiplication_state)
0: begin
@ -118,7 +115,6 @@ module zsimple_pll (
multiplication_state <= 2;
gen_pluse_cnt <= 0;
insignal_multiplication <= 1;
output_trigger_sig <= 1;
multiplication_cnt <= 0;
end
end
@ -126,15 +122,12 @@ module zsimple_pll (
if (multiplication_cnt < insignal_multiplication_freq_cnt >> 1) begin
multiplication_cnt <= multiplication_cnt + freq_multiplication + 1;
insignal_multiplication <= 1;
output_trigger_sig <= 0;
end else if ((multiplication_cnt + freq_multiplication + 2) >= insignal_multiplication_freq_cnt) begin
gen_pluse_cnt <= gen_pluse_cnt + 1;
multiplication_cnt <= 0;
insignal_multiplication <= 1;
output_trigger_sig <= 1;
gen_pluse_cnt <= gen_pluse_cnt + 1;
end else begin
output_trigger_sig <= 0;
if (gen_pluse_cnt >= freq_multiplication) begin
multiplication_state <= 1;
insignal_multiplication <= 0;

2
source/src/zutils/zutils_sig_delayer_v2.v
View File

@ -125,6 +125,7 @@ module zutils_sig_delayer_v2 (
endmodule
*/
// /*
module zutils_sig_delayer_v2 (
input clk,
input rst_n,
@ -139,3 +140,4 @@ module zutils_sig_delayer_v2 (
assign out = in;
endmodule
// */
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