From 693e7550da5c6f2e14dcd9f73262eda51ba706e7 Mon Sep 17 00:00:00 2001
From: zhaohe <h_zhaohe@163.com>
Date: Tue, 26 Mar 2024 22:14:26 +0800
Subject: [PATCH] update

---
 cfg_verify_result.sbit                            | Bin 0 -> 762416 bytes
 led_test.pds                                      | 102 +----
 source/src/business/record_sig_generator.v        | 113 ++++--
 source/src/config.v                               |   6 +-
 source/src/input/timecode_input.v                 | 132 +++----
 source/src/internal/internal_timecode_generator.v |   3 +-
 source/src/sys_signal_delayer.v                   |  28 +-
 source/src/top.v                                  | 447 ++++++++++++----------
 source/src/zutils/zsimple_pll.v                   |  14 +-
 9 files changed, 435 insertions(+), 410 deletions(-)
 create mode 100644 cfg_verify_result.sbit

diff --git a/cfg_verify_result.sbit b/cfg_verify_result.sbit
new file mode 100644
index 0000000000000000000000000000000000000000..782c53a216b835143a1b6f9fcced5bf2b6def879
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/led_test.pds b/led_test.pds
index 5a7c67d..86ff57d 100644
--- a/led_test.pds
+++ b/led_test.pds
@@ -1,5 +1,5 @@
 (_flow fab_demo "2021.1-SP7"
-    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Mar 25 20:08:45 2024")
+    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Mar 26 21:40:59 2024")
     (_version "1.0.5")
     (_status "initial")
     (_project 
@@ -19,7 +19,7 @@
             (_input
                 (_file "source/src/top.v" + "Top:"
                     (_format verilog)
-                    (_timespec "2024-03-25T17:56:09")
+                    (_timespec "2024-03-26T21:21:35")
                 )
                 (_file "source/src/spi_reg_reader.v"
                     (_format verilog)
@@ -131,7 +131,7 @@
                 )
                 (_file "source/src/input/timecode_input.v"
                     (_format verilog)
-                    (_timespec "2024-03-23T19:37:51")
+                    (_timespec "2024-03-26T21:40:57")
                 )
                 (_file "source/src/timecode/timecode_decoder.v"
                     (_format verilog)
@@ -163,7 +163,7 @@
                 )
                 (_file "source/src/zutils/zsimple_pll.v"
                     (_format verilog)
-                    (_timespec "2024-03-23T20:42:57")
+                    (_timespec "2024-03-26T18:46:59")
                 )
                 (_file "source/src/zutils/zutils_freq_detector_v2.v"
                     (_format verilog)
@@ -179,7 +179,7 @@
                 )
                 (_file "source/src/internal/internal_timecode_generator.v"
                     (_format verilog)
-                    (_timespec "2024-03-23T20:29:33")
+                    (_timespec "2024-03-26T20:23:00")
                 )
                 (_file "source/src/sys/sys_timecode.v"
                     (_format verilog)
@@ -207,15 +207,15 @@
                 )
                 (_file "source/src/output/camera_sync_signal_output.v"
                     (_format verilog)
-                    (_timespec "2024-03-25T17:49:01")
+                    (_timespec "2024-03-26T16:56:33")
                 )
                 (_file "source/src/business/record_sig_generator.v"
                     (_format verilog)
-                    (_timespec "2024-03-06T00:10:36")
+                    (_timespec "2024-03-26T18:42:49")
                 )
                 (_file "source/src/sys_signal_delayer.v"
                     (_format verilog)
-                    (_timespec "2024-03-25T11:41:59")
+                    (_timespec "2024-03-26T21:16:17")
                 )
                 (_file "source/src/zutils/zutils_sig_delayer.v"
                     (_format verilog)
@@ -315,17 +315,17 @@
             (_db_output
                 (_file "compile/Top_comp.adf"
                     (_format adif)
-                    (_timespec "2024-03-25T19:55:01")
+                    (_timespec "2024-03-26T21:40:58")
                 )
             )
             (_output
                 (_file "compile/Top.cmr"
                     (_format verilog)
-                    (_timespec "2024-03-25T19:54:58")
+                    (_timespec "2024-03-26T21:40:57")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2024-03-25T19:55:01")
+                    (_timespec "2024-03-26T21:40:58")
                 )
             )
         )
@@ -335,29 +335,9 @@
     )
     (_task tsk_synthesis
         (_command cmd_synthesize
-            (_gci_state (_integer 2))
+            (_gci_state (_integer 0))
             (_option ads (_switch ON))
             (_option selected_syn_tool_opt (_integer 2))
-            (_db_output
-                (_file "synthesize/Top_syn.adf"
-                    (_format adif)
-                    (_timespec "2024-03-25T19:55:33")
-                )
-            )
-            (_output
-                (_file "synthesize/Top_syn.vm"
-                    (_format structural_verilog)
-                    (_timespec "2024-03-25T19:55:35")
-                )
-                (_file "synthesize/Top.snr"
-                    (_format text)
-                    (_timespec "2024-03-25T19:55:37")
-                )
-                (_file "synthesize/snr.db"
-                    (_format text)
-                    (_timespec "2024-03-25T19:55:37")
-                )
-            )
         )
         (_widget wgt_tech_view
             (_attribute _click_to_run (_switch ON))
@@ -372,34 +352,14 @@
     )
     (_task tsk_devmap
         (_command cmd_devmap
-            (_gci_state (_integer 2))
-            (_db_output
-                (_file "device_map/Top_map.adf"
-                    (_format adif)
-                    (_timespec "2024-03-25T19:55:42")
-                )
-            )
-            (_output
-                (_file "device_map/Top_dmr.prt"
-                    (_format text)
-                    (_timespec "2024-03-25T19:55:39")
-                )
-                (_file "device_map/Top.dmr"
-                    (_format text)
-                    (_timespec "2024-03-25T19:55:42")
-                )
-                (_file "device_map/dmr.db"
-                    (_format text)
-                    (_timespec "2024-03-25T19:55:42")
-                )
-            )
+            (_gci_state (_integer 0))
         )
         (_widget wgt_edit_placement_cons
             (_attribute _click_to_run (_switch ON))
             (_input
                 (_file "device_map/led_test.pcf"
                     (_format pcf)
-                    (_timespec "2024-03-25T19:55:42")
+                    (_timespec "2024-03-26T21:39:24")
                 )
             )
         )
@@ -409,7 +369,7 @@
     )
     (_task tsk_pnr
         (_command cmd_pnr
-            (_gci_state (_integer 2))
+            (_gci_state (_integer 0))
             (_option gplace_seed (_integer 8))
             (_option seed_step (_integer 4))
             (_option saved_outcome (_integer 4))
@@ -418,38 +378,6 @@
             (_option check_clk_net_route_by_srb (_boolean FALSE))
             (_option mode (_string "fast"))
             (_option fix_hold_violation_in_route (_boolean FALSE))
-            (_db_output
-                (_file "place_route/Top_pnr.adf"
-                    (_format adif)
-                    (_timespec "2024-03-25T20:08:43")
-                )
-            )
-            (_output
-                (_file "place_route/Top.prr"
-                    (_format text)
-                    (_timespec "2024-03-25T20:08:44")
-                )
-                (_file "place_route/Top_prr.prt"
-                    (_format text)
-                    (_timespec "2024-03-25T20:08:41")
-                )
-                (_file "place_route/clock_utilization.txt"
-                    (_format text)
-                    (_timespec "2024-03-25T20:08:41")
-                )
-                (_file "place_route/Top_plc.adf"
-                    (_format adif)
-                    (_timespec "2024-03-25T19:56:00")
-                )
-                (_file "place_route/Top_pnr.netlist"
-                    (_format text)
-                    (_timespec "2024-03-25T20:08:44")
-                )
-                (_file "place_route/prr.db"
-                    (_format text)
-                    (_timespec "2024-03-25T20:08:45")
-                )
-            )
         )
         (_widget wgt_power_calculator
             (_attribute _click_to_run (_switch ON))
diff --git a/source/src/business/record_sig_generator.v b/source/src/business/record_sig_generator.v
index 825b35c..e6c7c81 100644
--- a/source/src/business/record_sig_generator.v
+++ b/source/src/business/record_sig_generator.v
@@ -20,26 +20,29 @@ module record_sig_generator #(
     input wire        sys_timecode_tigger_sig,
     input wire [63:0] sys_timecode_data,
 
-    output reg out_record_en_sig,       //!录制使能信号
-    output reg out_record_exposure_sig  //!录制曝光信号
+    output reg  out_record_en_sig,               //!录制使能信号
+    output reg  out_record_exposure_sig,         //!录制曝光信号
+    output wire out_record_en_rsing_edge_sig,    //!使能脉冲信号
+    output wire out_record_en_falling_edge_sig,  //!使能脉冲信号
+    output wire out_record_en_edge_sig           //!使能脉冲信号
 
 );
 
-
-
   reg [31:0] reg1_ctrl_control_mode;  //! 控制模式选择寄存器
 
+  //时码触发启动
   reg [31:0] reg2_timecode_start0;  //! 时码启动寄存器0
   reg [31:0] reg3_timecode_start1;  //! 时码启动寄存器1
   reg [31:0] reg4_timecode_stop0;  //! 时码停止寄存器0
   reg [31:0] reg5_timecode_stop1;  //! 时码停止寄存器1
   reg [31:0] reg6_timecode_control_flag;  //! 使能时码控制启动，使能使能时码控制停止
 
+  //TTL电平触发模式
   reg [31:0] reg7_ttlin_trigger_sig_source;  //! TTL触发信号选择
-  reg [31:0] reg8_ttlin_trigger_level;  //! TTL输入信号极性反转
+  reg [31:0] reg8_ttlin_trigger_level;  //! 
+  //TTL脉冲触发边沿选择
+  reg [31:0] reg9_ttlin_trigger_edge_select;  //! 
 
-  reg [31:0] reg9_exposure_time;  //! 曝光时长
-  reg [31:0] regA_exposure_delay;  //! 曝光信号延迟
 
   reg [31:0] regB_manual_ctrl;  //! 手动控制
   localparam REGA_MANUAL_CTRL_REG_INDEX = 32'd11;
@@ -68,8 +71,7 @@ module record_sig_generator #(
       .reg6(reg6_timecode_control_flag),
       .reg7(reg7_ttlin_trigger_sig_source),
       .reg8(reg8_ttlin_trigger_level),
-      .reg9(reg9_exposure_time),
-      .regA(regA_exposure_delay),
+      .reg9(reg9_ttlin_trigger_edge_select),
 
       .regB(regB_manual_ctrl),
       .regD(regD_timecode_snapshot0),
@@ -90,22 +92,19 @@ module record_sig_generator #(
       reg6_timecode_control_flag    <= 32'hFFFF_FFFF;
       reg7_ttlin_trigger_sig_source <= 1;
       reg8_ttlin_trigger_level      <= 1;
-      reg9_exposure_time            <= 32'd1000;  //100us
-      regA_exposure_delay           <= 0;
       regB_manual_ctrl              <= 0;
     end else begin
       if (reg_wr_sig) begin
         case (reg_wr_index)
-          1:  reg1_ctrl_control_mode <= wr_data;
-          2:  reg2_timecode_start0 <= wr_data;
-          3:  reg3_timecode_start1 <= wr_data;
-          4:  reg4_timecode_stop0 <= wr_data;
-          5:  reg5_timecode_stop1 <= wr_data;
-          6:  reg6_timecode_control_flag <= wr_data;
-          7:  reg7_ttlin_trigger_sig_source <= wr_data;
-          8:  reg8_ttlin_trigger_level <= wr_data;
-          9:  reg9_exposure_time <= wr_data;
-          10: regA_exposure_delay <= wr_data;
+          1: reg1_ctrl_control_mode <= wr_data;
+          2: reg2_timecode_start0 <= wr_data;
+          3: reg3_timecode_start1 <= wr_data;
+          4: reg4_timecode_stop0 <= wr_data;
+          5: reg5_timecode_stop1 <= wr_data;
+          6: reg6_timecode_control_flag <= wr_data;
+          7: reg7_ttlin_trigger_sig_source <= wr_data;
+          8: reg8_ttlin_trigger_level <= wr_data;
+          9: reg9_ttlin_trigger_edge_select <= wr_data;
           default: begin
           end
         endcase
@@ -117,21 +116,44 @@ module record_sig_generator #(
   wire ttl_in_choose;  //! 选中的ttl触发信号，(已经经过电平翻转)
   wire timecode_start_trigger_sig;  //!timecode启动信号
   wire timecode_stop_trigger_sig;  //!timecode停止信号
-  wire record_exposure_sig;  //!曝光信号
-  wire frame_freq_sig_rising_edge;
+  wire frame_freq_sig_rising_edge;  //!
 
 
   zutils_multiplexer_32t1_v2 ttlin_level_trigger_multi (
       .chooseindex(reg7_ttlin_trigger_sig_source),
       //in
-      .in1        (ttlin1_sig ^ (!reg8_ttlin_trigger_level[0])),
-      .in2        (ttlin2_sig ^ (!reg8_ttlin_trigger_level[0])),
-      .in3        (ttlin3_sig ^ (!reg8_ttlin_trigger_level[0])),
-      .in4        (ttlin4_sig ^ (!reg8_ttlin_trigger_level[0])),
+      .in1        (ttlin1_sig),
+      .in2        (ttlin2_sig),
+      .in3        (ttlin3_sig),
+      .in4        (ttlin4_sig),
       //out
       .out        (ttl_in_choose)
   );
 
+
+  zutils_edge_detecter ttltrigger_edge (
+      .clk      (clk),
+      .rst_n    (rst_n),
+      .in_signal(ttl_in_choose),
+
+      .in_signal_rising_edge (ttl_in_choose_rsing_edge_sig),
+      .in_signal_falling_edge(ttl_in_choose_falling_edge_sig),
+      .in_signal_edge        (ttl_in_choose_edge_sig)
+  );
+
+  zutils_multiplexer_32t1_v2 ttltrigger_edge_multiplexer (
+      .chooseindex(reg9_ttlin_trigger_edge_select),
+      //in
+      .in1        (ttl_in_choose_rsing_edge_sig),
+      .in2        (ttl_in_choose_falling_edge_sig),
+      .in3        (ttl_in_choose_edge_sig),
+      //out
+      .out        (ttl_in_choose_trigger_edge)
+  );
+
+
+
+
   /*******************************************************************************
    *                                StartSig输出                                 *
    *******************************************************************************/
@@ -160,14 +182,6 @@ module record_sig_generator #(
       .in_signal_rising_edge(frame_freq_sig_rising_edge)
   );
 
-  zutils_pluse_generator _pluse_generator (
-      .clk          (clk),
-      .rst_n        (rst_n),
-      .pluse_width  (reg9_exposure_time),
-      .pluse_delay  (regA_exposure_delay),
-      .trigger      (frame_freq_sig_rising_edge),
-      .output_signal(record_exposure_sig)
-  );
 
   reg en_state;
   always @(posedge clk or negedge rst_n) begin
@@ -203,12 +217,26 @@ module record_sig_generator #(
 
         3: begin
           //外部电平控制
-          if (ttl_in_choose == 1) begin
+          if (ttl_in_choose ^ (!reg8_ttlin_trigger_level[0])) begin
             en_state <= 1;
           end else begin
             en_state <= 0;
           end
         end
+
+        4: begin
+          //脉冲触发模式
+          if (en_state) begin
+            if (ttl_in_choose_trigger_edge) begin
+              en_state <= 0;
+            end
+          end else begin
+            if (ttl_in_choose_trigger_edge) begin
+              en_state <= 1;
+            end
+          end
+
+        end
         default: begin
         end
       endcase
@@ -244,10 +272,21 @@ module record_sig_generator #(
   end
 
 
+  zutils_edge_detecter en_edge_detecter (
+      .clk      (clk),
+      .rst_n    (rst_n),
+      .in_signal(out_record_en_sig),
+
+      .in_signal_rising_edge (out_record_en_rsing_edge_sig),
+      .in_signal_falling_edge(out_record_en_falling_edge_sig),
+      .in_signal_edge        (out_record_en_edge_sig)
+  );
+
+
   always @(*) begin
     regF_record_state[0]    <= en_state_af_sync;
     out_record_en_sig       <= en_state_af_sync;
-    out_record_exposure_sig <= out_record_en_sig & record_exposure_sig;
+    out_record_exposure_sig <= out_record_en_sig & frame_freq_sig;
   end
 
 endmodule
diff --git a/source/src/config.v b/source/src/config.v
index 85405e4..7095141 100644
--- a/source/src/config.v
+++ b/source/src/config.v
@@ -35,7 +35,11 @@
 `define SIGNAL_SYS_TIMECODE_FREQ_OUTPUT 32'd13
 `define SIGNAL_BUSINESS_RECORD_SIG 32'd14
 `define SIGNAL_BUSINESS_RECORD_EXPOSURE_SIG 32'd15
+`define SIGNAL_BUSINESS_RECORD_EN_RSING_EDGE_SIG 32'd16
+`define SIGNAL_BUSINESS_RECORD_EN_FALLING_EDGE_SIG 32'd17
+`define SIGNAL_BUSINESS_RECORD_EN_EDGE_SIG 32'd18
+
 
 `define TTL_OUTPUT_TRIGGER_MODE_SIG_WIDTH 32'd1000
 `define FREQ_DETECT_BIAS_DEFAULT 32'd10
-`define VERSION 32'd3
\ No newline at end of file
+`define VERSION 32'd3
diff --git a/source/src/input/timecode_input.v b/source/src/input/timecode_input.v
index 58b80bd..cd9f0bb 100644
--- a/source/src/input/timecode_input.v
+++ b/source/src/input/timecode_input.v
@@ -32,18 +32,13 @@ module timecode_input_parser #(
 );
 
 
-  reg  [31:0] r1_timecode_sig_selt;  //信号源选择 0:off,1:bnc,2:headphone
-  reg  [31:0] r2_ch1_timecode_format;  //
-  reg  [31:0] r3_ch1_timecode0;  //
-  reg  [31:0] r4_ch1_timecode1;  //
-  wire [31:0] r5_ch1_freq;  //
-  reg  [31:0] r6_ch2_timecode_format;  //
-  reg  [31:0] r7_ch2_timecode0;  //
-  reg  [31:0] r8_ch2_timecode1;  //
-  wire [31:0] r9_ch2_freq;  //
+  reg  [31:0] r1_timecode_sig_selt;  //信号源选择 0:none,1:bnc,2:headphone
+  reg  [31:0] r2_timecode_format;  //
+  reg  [31:0] r3_timecode0;  //
+  reg  [31:0] r4_timecode1;  //
+  reg  [31:0] r5_freq;  //
   reg  [31:0] rA_freq_bias;  //
 
-
   wire [31:0] reg_wr_index;
   zutils_register_advanced #(
       .REG_START_ADD(REG_START_ADD)
@@ -55,15 +50,12 @@ module timecode_input_parser #(
       .wr_en  (wr_en),
       .rd_data(rd_data),
 
-      .reg1      (r1_timecode_sig_selt),
-      .reg2      (r2_ch1_timecode_format),
-      .reg3      (r3_ch1_timecode0),
-      .reg4      (r4_ch1_timecode1),
-      .reg5      (r5_ch1_freq),
-      .reg6      (r6_ch2_timecode_format),
-      .reg7      (r7_ch2_timecode0),
-      .reg8      (r8_ch2_timecode1),
-      .reg9      (r9_ch2_freq),
+      .reg1(r1_timecode_sig_selt),
+      .reg2(r2_timecode_format),
+      .reg3(r3_timecode0),
+      .reg4(r4_timecode1),
+      .reg5(r5_freq),
+
       .regA      (rA_freq_bias),
       .reg_wr_sig(reg_wr_sig),
       .reg_index (reg_wr_index)
@@ -71,16 +63,10 @@ module timecode_input_parser #(
 
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
-      r1_timecode_sig_selt   <= 1;
-      r2_ch1_timecode_format <= 0;
-      r6_ch2_timecode_format <= 0;
-      rA_freq_bias           <= `FREQ_DETECT_BIAS_DEFAULT;
+      rA_freq_bias <= `FREQ_DETECT_BIAS_DEFAULT;
     end else begin
       if (reg_wr_sig) begin
         case (reg_wr_index)
-          31'h1: r1_timecode_sig_selt <= wr_data;
-          31'h2: r2_ch1_timecode_format <= wr_data;
-          31'h6: r6_ch2_timecode_format <= wr_data;
           31'hA: rA_freq_bias <= wr_data;
           default: begin
           end
@@ -89,16 +75,17 @@ module timecode_input_parser #(
     end
   end
 
-
   wire        ch1_timecode_tigger_sig;
-  wire [31:0] ch1_timecode_format;
   wire [63:0] ch1_timecode_data;
   wire        ch1_timecode_serial_data;
+  wire [31:0] ch1_freq;
+
 
   wire        ch2_timecode_tigger_sig;
-  wire [31:0] ch2_timecode_format;
   wire [63:0] ch2_timecode_data;
   wire        ch2_timecode_serial_data;
+  wire [31:0] ch2_freq;
+
 
   timecode_decoder #(
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
@@ -116,7 +103,7 @@ module timecode_input_parser #(
       .rst_n           (rst_n),
       .freq_detect_bias(rA_freq_bias),
       .pluse_input     (ch1_timecode_tigger_sig),
-      .pluse_width_cnt (r5_ch1_freq)
+      .pluse_width_cnt (ch1_freq)
   );
 
   timecode_decoder #(
@@ -136,53 +123,68 @@ module timecode_input_parser #(
       .rst_n           (rst_n),
       .freq_detect_bias(rA_freq_bias),
       .pluse_input     (ch2_timecode_tigger_sig),
-      .pluse_width_cnt (r9_ch2_freq)
+      .pluse_width_cnt (ch2_freq)
   );
 
-  always @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      r3_ch1_timecode0 <= 0;
-      r4_ch1_timecode1 <= 0;
-      r7_ch2_timecode0 <= 0;
-      r8_ch2_timecode1 <= 0;
-    end else begin
-      if (ch1_timecode_tigger_sig) begin
-        r3_ch1_timecode0 <= ch1_timecode_data[31:0];
-        r4_ch1_timecode1 <= ch1_timecode_data[63:32];
-      end
 
-      if (ch2_timecode_tigger_sig) begin
-        r7_ch2_timecode0 <= ch2_timecode_data[31:0];
-        r8_ch2_timecode1 <= ch2_timecode_data[63:32];
-      end
-    end
-  end
+  reg [ 1:0] state;  //! 0:探测中 1:探测完成
+  reg [31:0] freq_cache;
 
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
-      timecode_tigger_sig  <= 0;
-      timecode_format      <= 32'hF;
-      timecode_data        <= 0;
-      timecode_serial_data <= 0;
+      state                <= 0;
+      r2_timecode_format   <= 32'hFFFF_FFFF;
+      r3_timecode0         <= 0;
+      r4_timecode1         <= 0;
+      r5_freq              <= 0;
+      r1_timecode_sig_selt <= 0;
+      freq_cache           <= 0;
     end else begin
-      case (r1_timecode_sig_selt)
+      case (state)
+        0: begin
+          r2_timecode_format   <= 32'hFFFF_FFFF;
+          r5_freq              <= 0;
+          r1_timecode_sig_selt <= 0;
+          r3_timecode0         <= 0;
+          r4_timecode1         <= 0;
+          timecode_tigger_sig  <= 0;
+
+          if (ch1_freq != 0) begin
+            state      <= 1;
+            freq_cache <= ch1_freq;
+          end else if (ch2_freq != 0) begin
+            state      <= 2;
+            freq_cache <= ch2_freq;
+          end
+
+        end
         1: begin
-          timecode_tigger_sig  <= ch1_timecode_tigger_sig;
-          timecode_format      <= r2_ch1_timecode_format;
-          timecode_data        <= ch1_timecode_data;
-          timecode_serial_data <= ch1_timecode_serial_data;
+          if (freq_cache != ch1_freq) begin
+            state      <= 0;
+            freq_cache <= 0;
+          end else begin
+            r5_freq              <= ch1_freq;
+            r1_timecode_sig_selt <= 1;
+            r3_timecode0         <= ch1_timecode_data[31:0];
+            r4_timecode1         <= ch1_timecode_data[63:32];
+            timecode_tigger_sig  <= ch1_timecode_tigger_sig;
+          end
         end
+
         2: begin
-          timecode_tigger_sig  <= ch2_timecode_tigger_sig;
-          timecode_format      <= r6_ch2_timecode_format;
-          timecode_data        <= ch2_timecode_data;
-          timecode_serial_data <= ch2_timecode_serial_data;
+          if (freq_cache != ch2_freq) begin
+            state      <= 0;
+            freq_cache <= 0;
+          end else begin
+            r5_freq              <= ch2_freq;
+            r1_timecode_sig_selt <= 2;
+            r3_timecode0         <= ch2_timecode_data[31:0];
+            r4_timecode1         <= ch2_timecode_data[63:32];
+            timecode_tigger_sig  <= ch2_timecode_tigger_sig;
+          end
         end
         default: begin
-          timecode_tigger_sig  <= 0;
-          timecode_format      <= 32'hF;
-          timecode_data        <= 0;
-          timecode_serial_data <= 0;
+          state <= 0;
         end
       endcase
     end
diff --git a/source/src/internal/internal_timecode_generator.v b/source/src/internal/internal_timecode_generator.v
index 0fd27e5..f3e07c5 100644
--- a/source/src/internal/internal_timecode_generator.v
+++ b/source/src/internal/internal_timecode_generator.v
@@ -45,6 +45,7 @@ module internal_timecode_generator #(
       .reg2      (reg2_timecode_format),
       .reg3      (reg3_timecode_data0),
       .reg4      (reg4_timecode_data1),
+      .reg5      (reg5_detect_freq),
       .reg_wr_sig(reg_wr_sig),
       .reg_index (reg_wr_index)
   );
@@ -96,7 +97,7 @@ module internal_timecode_generator #(
   zutils_freq_detector_v2 freq_detector1 (
       .clk             (clk),
       .rst_n           (rst_n),
-      .freq_detect_bias(1),
+      .freq_detect_bias(10),
       .pluse_input     (timecode_tigger_sig),
       .pluse_width_cnt (reg5_detect_freq)
   );
diff --git a/source/src/sys_signal_delayer.v b/source/src/sys_signal_delayer.v
index c8bd054..b0f9753 100644
--- a/source/src/sys_signal_delayer.v
+++ b/source/src/sys_signal_delayer.v
@@ -71,18 +71,22 @@ module sys_signal_delayer #(
   end
 
   assign delayer_rst_n = delayer_rst_n_ctrl & rst_n;
-  genvar i;
-  generate
-    for (i = 0; i <= SIG_BUS_WIDTH; i = i + 1) begin
-      zutils_sig_delayer_v2 sig_delayer_inst (
-          .clk      (clk),
-          .rst_n    (delayer_rst_n),
-          .delay_cnt(delay_ctrl[i]),
-          .in       (sig_in[i]),
-          .out      (sig_out[i])
-      );
-    end
-  endgenerate
+  // genvar i;
+  // generate
+  //   for (i = 0; i <= SIG_BUS_WIDTH; i = i + 1) begin
+  //     // zutils_sig_delayer_v2 sig_delayer_inst (
+  //     //     .clk      (clk),
+  //     //     .rst_n    (delayer_rst_n),
+  //     //     .delay_cnt(delay_ctrl[i]),
+  //     //     .in       (sig_in[i]),
+  //     //     .out      (sig_out[i])
+  //     // );
+
+  //     assign sig_out[i] = sig_in[i];
+  //   end
+  // endgenerate
+
+  assign sig_out   = sig_in;
 
 
 endmodule
diff --git a/source/src/top.v b/source/src/top.v
index 2f2e388..0a6ac6e 100644
--- a/source/src/top.v
+++ b/source/src/top.v
@@ -130,6 +130,10 @@ module Top (
   wire        signal_sys_timecode_freq_output;  //! 系统时间码频率输出
   wire        signal_business_record_en_sig;  //! 业务摄影状态信号
   wire        signal_business_record_exposure_sig;  //! 业务摄影拍照曝光信号
+  wire        signal_business_record_en_rsing_edge_sig;  //! 业务摄影状态信号
+  wire        signal_business_record_en_falling_edge_sig;  //! 业务摄影状态信号
+  wire        signal_business_record_en_edge_sig;  //! 业务摄影状态信号
+
 
   wire        internal_timecode_tigger_sig;  //!内部timecode频率信号
   wire [31:0] internal_timecode_format;  //!内部timecode格式
@@ -147,27 +151,31 @@ module Top (
   wire [31:0] sig_src;  // 系统内部信号总线
 
 
-  assign sig_src[`SIGNAL_LOGIC0]                       = signal_logic0;
-  assign sig_src[`SIGNAL_LOGIC1]                       = signal_logic1;
-  assign sig_src[`SIGNAL_TTLIN1]                       = signal_ttlin1;
-  assign sig_src[`SIGNAL_TTLIN2]                       = signal_ttlin2;
-  assign sig_src[`SIGNAL_TTLIN3]                       = signal_ttlin3;
-  assign sig_src[`SIGNAL_TTLIN4]                       = signal_ttlin4;
-  assign sig_src[`SIGNAL_EXT_GENLOCK_FREQ]             = signal_ext_genlock_freq;
-  assign sig_src[`SIGNAL_EXT_TIMECODE_FREQ]            = signal_ext_timecode_freq;
-  assign sig_src[`SIGNAL_INTERNAL_TIMECODE_FREQ]       = signal_internal_timecode_freq;
-  assign sig_src[`SIGNAL_INTERNAL_GENLOCK_FREQ]        = signal_internal_genlock_freq;
-  assign sig_src[`SIGNAL_INTERNAL_CLOCK_SIG]           = signal_internal_clk_sig;
-  assign sig_src[`SIGNAL_SYS_CLK_OUTPUT]               = signal_sys_clk_output;
-  assign sig_src[`SIGNAL_SYS_GENLOCK_OUTPUT]           = signal_sys_genlock_output;
-  assign sig_src[`SIGNAL_SYS_TIMECODE_FREQ_OUTPUT]     = signal_sys_timecode_freq_output;
-  assign sig_src[`SIGNAL_BUSINESS_RECORD_SIG]          = signal_business_record_en_sig;
-  assign sig_src[`SIGNAL_BUSINESS_RECORD_EXPOSURE_SIG] = signal_business_record_exposure_sig;
-
-  assign signal_logic0                                 = 1'b0;
-  assign signal_logic1                                 = 1'b1;
-  assign signal_internal_timecode_freq                 = internal_timecode_serial_data;
-  assign signal_sys_timecode_freq_output               = sys_timecode_tigger_sig;
+  assign sig_src[`SIGNAL_LOGIC0]                              = signal_logic0;
+  assign sig_src[`SIGNAL_LOGIC1]                              = signal_logic1;
+  assign sig_src[`SIGNAL_TTLIN1]                              = signal_ttlin1;
+  assign sig_src[`SIGNAL_TTLIN2]                              = signal_ttlin2;
+  assign sig_src[`SIGNAL_TTLIN3]                              = signal_ttlin3;
+  assign sig_src[`SIGNAL_TTLIN4]                              = signal_ttlin4;
+  assign sig_src[`SIGNAL_EXT_GENLOCK_FREQ]                    = signal_ext_genlock_freq;
+  assign sig_src[`SIGNAL_EXT_TIMECODE_FREQ]                   = signal_ext_timecode_freq;
+  assign sig_src[`SIGNAL_INTERNAL_TIMECODE_FREQ]              = signal_internal_timecode_freq;
+  assign sig_src[`SIGNAL_INTERNAL_GENLOCK_FREQ]               = signal_internal_genlock_freq;
+  assign sig_src[`SIGNAL_INTERNAL_CLOCK_SIG]                  = signal_internal_clk_sig;
+  assign sig_src[`SIGNAL_SYS_CLK_OUTPUT]                      = signal_sys_clk_output;
+  assign sig_src[`SIGNAL_SYS_GENLOCK_OUTPUT]                  = signal_sys_genlock_output;
+  assign sig_src[`SIGNAL_SYS_TIMECODE_FREQ_OUTPUT]            = signal_sys_timecode_freq_output;
+  assign sig_src[`SIGNAL_BUSINESS_RECORD_SIG]                 = signal_business_record_en_sig;
+  assign sig_src[`SIGNAL_BUSINESS_RECORD_EXPOSURE_SIG]        = signal_business_record_exposure_sig;
+  assign sig_src[`SIGNAL_BUSINESS_RECORD_EN_RSING_EDGE_SIG]   = signal_business_record_en_rsing_edge_sig;
+  assign sig_src[`SIGNAL_BUSINESS_RECORD_EN_FALLING_EDGE_SIG] = signal_business_record_en_falling_edge_sig;
+  assign sig_src[`SIGNAL_BUSINESS_RECORD_EN_EDGE_SIG]         = signal_business_record_en_edge_sig;
+
+
+  assign signal_logic0                                        = 1'b0;
+  assign signal_logic1                                        = 1'b1;
+  assign signal_internal_timecode_freq                        = internal_timecode_serial_data;
+  assign signal_sys_timecode_freq_output                      = sys_timecode_tigger_sig;
 
 
   //系统时钟源
@@ -216,9 +224,7 @@ module Top (
   );
 
 
-  /*******************************************************************************
-   *                                  FPGA_INFO                                  *
-   *******************************************************************************/
+
   zutils_register16 #(
       .REG_START_ADD(`REGADDOFF__FPGA_INFO),
       .REG0_INIT(`VERSION),
@@ -246,6 +252,64 @@ module Top (
       .rd_data(rd_data_module_fpga_info)
   );
 
+  wire [15:0] sys_sig_delay_in;
+  wire [15:0] sys_sig_delay_out;
+
+  wire        before_delay__sync_ttl_out1;
+  wire        before_delay__sync_ttl_out2;
+  wire        before_delay__sync_ttl_out3;
+  wire        before_delay__sync_ttl_out4;
+  wire        before_delay__stm32if_start_signal_out;
+  wire        before_delay__stm32if_camera_sync_out;
+  wire        before_delay__stm32if_timecode_sync_out;
+
+  wire        af_delay__sync_ttl_in1;
+  wire        af_delay__sync_ttl_in2;
+  wire        af_delay__sync_ttl_in3;
+  wire        af_delay__sync_ttl_in4;
+  wire        af_delay__timecode_headphone_in;
+  wire        af_delay__timecode_bnc_in;
+  wire        af_delay__genlock_in_hsync;
+  wire        af_delay__genlock_in_vsync;
+  wire        af_delay__genlock_in_fsync;
+
+
+  assign sys_sig_delay_in[0]             = sync_ttl_in1;  //
+  assign sys_sig_delay_in[1]             = sync_ttl_in2;  //
+  assign sys_sig_delay_in[2]             = sync_ttl_in3;  //
+  assign sys_sig_delay_in[3]             = sync_ttl_in4;  //
+  assign sys_sig_delay_in[4]             = timecode_headphone_in;  //
+  assign sys_sig_delay_in[5]             = timecode_bnc_in;  //
+  assign sys_sig_delay_in[6]             = genlock_in_hsync;  //
+  assign sys_sig_delay_in[7]             = genlock_in_vsync;  //
+  assign sys_sig_delay_in[8]             = genlock_in_fsync;  //
+  assign sys_sig_delay_in[9]             = before_delay__sync_ttl_out1;  //
+  assign sys_sig_delay_in[10]            = before_delay__sync_ttl_out2;  //
+  assign sys_sig_delay_in[11]            = before_delay__sync_ttl_out3;  //
+  assign sys_sig_delay_in[12]            = before_delay__sync_ttl_out4;  //
+  assign sys_sig_delay_in[13]            = before_delay__stm32if_start_signal_out;  //
+  assign sys_sig_delay_in[14]            = before_delay__stm32if_camera_sync_out;  //
+  assign sys_sig_delay_in[15]            = before_delay__stm32if_timecode_sync_out;  //
+
+  assign af_delay__sync_ttl_in1          = sys_sig_delay_out[0];
+  assign af_delay__sync_ttl_in2          = sys_sig_delay_out[1];
+  assign af_delay__sync_ttl_in3          = sys_sig_delay_out[2];
+  assign af_delay__sync_ttl_in4          = sys_sig_delay_out[3];
+  assign af_delay__timecode_headphone_in = sys_sig_delay_out[4];
+  assign af_delay__timecode_bnc_in       = sys_sig_delay_out[5];
+  assign af_delay__genlock_in_hsync      = sys_sig_delay_out[6];
+  assign af_delay__genlock_in_vsync      = sys_sig_delay_out[7];
+  assign af_delay__genlock_in_fsync      = sys_sig_delay_out[8];
+  assign sync_ttl_out1                   = sys_sig_delay_out[9];
+  assign sync_ttl_out2                   = sys_sig_delay_out[10];
+  assign sync_ttl_out3                   = sys_sig_delay_out[11];
+  assign sync_ttl_out4                   = sys_sig_delay_out[12];
+  assign stm32if_start_signal_out        = sys_sig_delay_out[13];
+  assign stm32if_camera_sync_out         = sys_sig_delay_out[14];
+  assign stm32if_timecode_sync_out       = sys_sig_delay_out[15];
+
+
+
   sys_signal_delayer #(
       .REG_START_ADD (`REGADDOFF__DELAYER),
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
@@ -258,80 +322,79 @@ module Top (
       .wr_en  (RegReaderBus_wr_en),
       .rd_data(rd_data_module_sys_signal_delayer),
 
-      .sig_in({
-        sync_ttl_in1,  //0
-        sync_ttl_in2,  //1
-        sync_ttl_in3,  //2
-        sync_ttl_in4,  //3
-        timecode_headphone_in,  //4
-        timecode_bnc_in,  //5
-        genlock_in_hsync,  //6
-        genlock_in_vsync,  //7
-        genlock_in_fsync,  //8
-
-        before_delay__sync_ttl_out1,  //9
-        before_delay__sync_ttl_out2,  //10
-        before_delay__sync_ttl_out3,  //11
-        before_delay__sync_ttl_out4,  //12
-        before_delay__stm32if_start_signal_out,  //13
-        before_delay__stm32if_camera_sync_out,  //14
-        before_delay__stm32if_timecode_sync_out  //15
-      }),
-      .sig_out({
-        af_delay__sync_ttl_in1,  //0
-        af_delay__sync_ttl_in2,  //1
-        af_delay__sync_ttl_in3,  //2
-        af_delay__sync_ttl_in4,  //3
-        af_delay__timecode_headphone_in,  //4
-        af_delay__timecode_bnc_in,  //5
-        af_delay__genlock_in_hsync,  //6
-        af_delay__genlock_in_vsync,  //7
-        af_delay__genlock_in_fsync,  //8
-        sync_ttl_out1,  //9
-        sync_ttl_out2,  //10
-        sync_ttl_out3,  //11
-        sync_ttl_out4,  //12
-        stm32if_start_signal_out,  //13
-        stm32if_camera_sync_out,  //14
-        stm32if_timecode_sync_out  //15
-      })
+      .sig_in (sys_sig_delay_in),
+      .sig_out(sys_sig_delay_out)
   );
 
 
-  /*******************************************************************************
-   *                                 TTL输入模块                                 *
-   *******************************************************************************/
 
-  ttl_input #(
-      .REG_START_ADD (`REGADDOFF__TTLIN),
+  internal_sig_generator_en_contrler #(
+      .REG_START_ADD (`REGADDOFF__INTERNAL_SIG_EN_CONTRLER),
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
-  ) ttl_inputr_ins (
+  ) internal_sig_generator_en_contrler0 (
       .clk  (sys_clk),
       .rst_n(sys_rst_n),
 
       .addr   (RegReaderBus_addr),
       .wr_data(RegReaderBus_wr_data),
       .wr_en  (RegReaderBus_wr_en),
-      .rd_data(rd_data_module_ttlin),
+      .rd_data(rd_data_module_internal_sig_en_contrler),
 
-      .ttlin1_raw(af_delay__sync_ttl_in1),
-      .ttlin2_raw(af_delay__sync_ttl_in2),
-      .ttlin3_raw(af_delay__sync_ttl_in3),
-      .ttlin4_raw(!af_delay__sync_ttl_in4), //in4电路上进行了反向
+      .en0(en0),
+      .en1(en1),
+      .en2(en2)
+  );
 
-      //指示灯
-      .ttlin1_state_led(sync_ttl_in1_state_led),
-      .ttlin2_state_led(sync_ttl_in2_state_led),
-      .ttlin3_state_led(sync_ttl_in3_state_led),
-      .ttlin4_state_led(sync_ttl_in4_state_led),
 
-      //原始信号
-      .sig_ttlin1(signal_ttlin1),
-      .sig_ttlin2(signal_ttlin2),
-      .sig_ttlin3(signal_ttlin3),
-      .sig_ttlin4(signal_ttlin4)
+
+  internal_timecode_generator #(
+      .REG_START_ADD(`REGADDOFF__INTERNAL_TIMECODE),
+      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
+      .ID(1)
+  ) internal_timecode_generator0 (
+      .clk  (sys_clk),
+      .rst_n(sys_rst_n),
+
+      .addr   (RegReaderBus_addr),
+      .wr_data(RegReaderBus_wr_data),
+      .wr_en  (RegReaderBus_wr_en),
+      .rd_data(rd_data_module_internal_timecode),
+
+      .en(en0),
+
+      .timecode_tigger_sig (internal_timecode_tigger_sig),
+      .timecode_format     (internal_timecode_format),
+      .timecode_data       (internal_timecode_data),
+      .timecode_serial_data(internal_timecode_serial_data)
   );
 
+  sys_timecode #(
+      .REG_START_ADD (`REGADDOFF__SYS_TIMECODE),
+      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
+  ) sys_timecode_ins (
+      .clk  (sys_clk),
+      .rst_n(sys_rst_n),
+
+      .addr   (RegReaderBus_addr),
+      .wr_data(RegReaderBus_wr_data),
+      .wr_en  (RegReaderBus_wr_en),
+      .rd_data(rd_data_module_sys_timecode),
+
+      .internal_timecode_tigger_sig (internal_timecode_tigger_sig),
+      .internal_timecode_format     (internal_timecode_format),
+      .internal_timecode_data       (internal_timecode_data),
+      .internal_timecode_serial_data(internal_timecode_serial_data),
+
+      .external_timecode_tigger_sig (ext_timecode_tigger_sig),
+      .external_timecode_format     (ext_timecode_format),
+      .external_timecode_data       (ext_timecode_data),
+      .external_timecode_serial_data(ext_timecode_serial_data),
+
+      .sys_timecode_tigger_sig (sys_timecode_tigger_sig),
+      .sys_timecode_format     (sys_timecode_format),
+      .sys_timecode_data       (sys_timecode_data),
+      .sys_timecode_serial_data(sys_timecode_serial_data)
+  );
 
   timecode_input_parser #(
       .REG_START_ADD (`REGADDOFF__TIMECODE_IN),
@@ -358,71 +421,62 @@ module Top (
       .timecode_bnc_in_state_led      (timecode_bnc_in_state_led)
   );
 
-  genlock_input_module #(
-      .REG_START_ADD (`REGADDOFF__GENLOCK_IN),
+  timecode_output #(
+      .REG_START_ADD (`REGADDOFF__TIMECODE_OUT),
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
-  ) genlock_input (
+  ) timecode_output_inst (
+
       .clk  (sys_clk),
       .rst_n(sys_rst_n),
 
       .addr   (RegReaderBus_addr),
       .wr_data(RegReaderBus_wr_data),
       .wr_en  (RegReaderBus_wr_en),
-      .rd_data(rd_data_module_genlock_in),
+      .rd_data(rd_data_module_timecode_out),
 
-      .genlock_in_hsync(af_delay__genlock_in_hsync),
-      .genlock_in_vsync(af_delay__genlock_in_vsync),
-      .genlock_in_fsync(af_delay__genlock_in_fsync),
+      .in_timecode_tigger_sig (sys_timecode_tigger_sig),
+      .in_timecode_format     (sys_timecode_format),
+      .in_timecode_data       (sys_timecode_data),
+      .in_timecode_serial_data(sys_timecode_serial_data),
+
+      .timecode_out_bnc          (timecode_out_bnc),
+      .timecode_out_bnc_select   (timecode_out_bnc_select),
+      .timecode_out_bnc_state_led(timecode_out_bnc_state_led),
+
+      .timecode_out_headphone          (timecode_out_headphone),
+      .timecode_out_headphone_select   (timecode_out_headphone_select),
+      .timecode_out_headphone_state_led(timecode_out_headphone_state_led)
 
-      .genlock_freq_signal (signal_ext_genlock_freq),
-      .genlock_in_state_led(genlock_in_state_led)
   );
 
+
   //    
 
-  /*******************************************************************************
-   *                                 内部信号源                                  *
-   *******************************************************************************/
 
-  internal_sig_generator_en_contrler #(
-      .REG_START_ADD (`REGADDOFF__INTERNAL_SIG_EN_CONTRLER),
-      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
-  ) internal_sig_generator_en_contrler0 (
-      .clk  (sys_clk),
-      .rst_n(sys_rst_n),
 
-      .addr   (RegReaderBus_addr),
-      .wr_data(RegReaderBus_wr_data),
-      .wr_en  (RegReaderBus_wr_en),
-      .rd_data(rd_data_module_internal_sig_en_contrler),
-
-      .en0(en0),
-      .en1(en1),
-      .en2(en2)
-  );
 
-  internal_timecode_generator #(
-      .REG_START_ADD(`REGADDOFF__INTERNAL_TIMECODE),
-      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
-      .ID(1)
-  ) internal_timecode_generator0 (
+  /*
+  genlock_input_module #(
+      .REG_START_ADD (`REGADDOFF__GENLOCK_IN),
+      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
+  ) genlock_input (
       .clk  (sys_clk),
       .rst_n(sys_rst_n),
 
       .addr   (RegReaderBus_addr),
       .wr_data(RegReaderBus_wr_data),
       .wr_en  (RegReaderBus_wr_en),
-      .rd_data(rd_data_module_internal_timecode),
+      .rd_data(rd_data_module_genlock_in),
 
-      .en(en0),
+      .genlock_in_hsync(af_delay__genlock_in_hsync),
+      .genlock_in_vsync(af_delay__genlock_in_vsync),
+      .genlock_in_fsync(af_delay__genlock_in_fsync),
 
-      .timecode_tigger_sig (internal_timecode_tigger_sig),
-      .timecode_format     (internal_timecode_format),
-      .timecode_data       (internal_timecode_data),
-      .timecode_serial_data(internal_timecode_serial_data)
+      .genlock_freq_signal (signal_ext_genlock_freq),
+      .genlock_in_state_led(genlock_in_state_led)
   );
 
-  internal_genlock_generator #(
+    internal_genlock_generator #(
       .REG_START_ADD (`REGADDOFF__INTERNAL_GENLOCK),
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
   ) internal_genlock_generator0 (
@@ -456,36 +510,34 @@ module Top (
       .clk_output(signal_internal_clk_sig)
   );
 
-  /*******************************************************************************
-   *                                     SYS                                     *
-   *******************************************************************************/
-
-  sys_timecode #(
-      .REG_START_ADD (`REGADDOFF__SYS_TIMECODE),
+  ttl_input #(
+      .REG_START_ADD (`REGADDOFF__TTLIN),
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
-  ) sys_timecode_ins (
+  ) ttl_inputr_ins (
       .clk  (sys_clk),
       .rst_n(sys_rst_n),
 
       .addr   (RegReaderBus_addr),
       .wr_data(RegReaderBus_wr_data),
       .wr_en  (RegReaderBus_wr_en),
-      .rd_data(rd_data_module_sys_timecode),
+      .rd_data(rd_data_module_ttlin),
 
-      .internal_timecode_tigger_sig (internal_timecode_tigger_sig),
-      .internal_timecode_format     (internal_timecode_format),
-      .internal_timecode_data       (internal_timecode_data),
-      .internal_timecode_serial_data(internal_timecode_serial_data),
+      .ttlin1_raw(af_delay__sync_ttl_in1),
+      .ttlin2_raw(af_delay__sync_ttl_in2),
+      .ttlin3_raw(af_delay__sync_ttl_in3),
+      .ttlin4_raw(!af_delay__sync_ttl_in4), //in4电路上进行了反向
 
-      .external_timecode_tigger_sig (ext_timecode_tigger_sig),
-      .external_timecode_format     (ext_timecode_format),
-      .external_timecode_data       (ext_timecode_data),
-      .external_timecode_serial_data(ext_timecode_serial_data),
+      //指示灯
+      .ttlin1_state_led(sync_ttl_in1_state_led),
+      .ttlin2_state_led(sync_ttl_in2_state_led),
+      .ttlin3_state_led(sync_ttl_in3_state_led),
+      .ttlin4_state_led(sync_ttl_in4_state_led),
 
-      .sys_timecode_tigger_sig (sys_timecode_tigger_sig),
-      .sys_timecode_format     (sys_timecode_format),
-      .sys_timecode_data       (sys_timecode_data),
-      .sys_timecode_serial_data(sys_timecode_serial_data)
+      //原始信号
+      .sig_ttlin1(signal_ttlin1),
+      .sig_ttlin2(signal_ttlin2),
+      .sig_ttlin3(signal_ttlin3),
+      .sig_ttlin4(signal_ttlin4)
   );
 
 
@@ -506,7 +558,6 @@ module Top (
 
       .sys_genlock_tigger_sig(signal_sys_genlock_output)
   );
-
   sys_clock #(
       .REG_START_ADD (`REGADDOFF__SYS_CLOCK),
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
@@ -523,9 +574,33 @@ module Top (
       .sys_clock(signal_sys_clk_output)
   );
 
-  /*******************************************************************************
-  *                                 TTL_OUTPUT                                  *
-  *******************************************************************************/
+  camera_sync_signal_output #(
+    .REG_START_ADD (`REGADDOFF__CAMERA_SYNC_OUT),
+    .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
+) camera_sync_signal_output0 (
+    .clk  (sys_clk),
+    .rst_n(sys_rst_n),
+
+    .addr   (RegReaderBus_addr),
+    .wr_data(RegReaderBus_wr_data),
+    .wr_en  (RegReaderBus_wr_en),
+    .rd_data(rd_data_module_camera_sync_out),
+
+    .in_timecode_tigger_sig (sys_timecode_tigger_sig),
+    .in_timecode_format     (sys_timecode_format),
+    .in_timecode_data       (sys_timecode_data),
+    .in_timecode_serial_data(sys_timecode_serial_data),
+
+    .frame_sig    (signal_sys_clk_output),
+    .record_en_sig(signal_business_record_en_sig),
+
+
+    .stm32if_camera_sync_out        (before_delay__stm32if_camera_sync_out),
+    .stm32if_record_state_change_sig(before_delay__stm32if_start_signal_out),
+    .stm32if_timecode_tigger_sig    (before_delay__stm32if_timecode_sync_out)
+);
+
+
 
   ttl_output #(
       .REG_START_ADD(`REGADDOFF__TTLOUT1),
@@ -602,33 +677,7 @@ module Top (
       .ttloutput_state_led(sync_ttl_out4_state_led)
   );
 
-  timecode_output #(
-      .REG_START_ADD (`REGADDOFF__TIMECODE_OUT),
-      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
-  ) timecode_output_inst (
-
-      .clk  (sys_clk),
-      .rst_n(sys_rst_n),
-
-      .addr   (RegReaderBus_addr),
-      .wr_data(RegReaderBus_wr_data),
-      .wr_en  (RegReaderBus_wr_en),
-      .rd_data(rd_data_module_timecode_out),
-
-      .in_timecode_tigger_sig (sys_timecode_tigger_sig),
-      .in_timecode_format     (sys_timecode_format),
-      .in_timecode_data       (sys_timecode_data),
-      .in_timecode_serial_data(sys_timecode_serial_data),
-
-      .timecode_out_bnc          (timecode_out_bnc),
-      .timecode_out_bnc_select   (timecode_out_bnc_select),
-      .timecode_out_bnc_state_led(timecode_out_bnc_state_led),
 
-      .timecode_out_headphone          (timecode_out_headphone),
-      .timecode_out_headphone_select   (timecode_out_headphone_select),
-      .timecode_out_headphone_state_led(timecode_out_headphone_state_led)
-
-  );
 
   record_sig_generator #(
       .REG_START_ADD(`REGADDOFF__RECORD_SIG_GENERATOR),
@@ -648,46 +697,34 @@ module Top (
       .ttlin3_sig(signal_ttlin3),
       .ttlin4_sig(signal_ttlin4),
 
-      .frame_freq_sig         (signal_sys_clk_output),
+      .frame_freq_sig(signal_sys_clk_output),
+
+      .out_record_en_rsing_edge_sig  (signal_business_record_en_rsing_edge_sig),
+      .out_record_en_falling_edge_sig(signal_business_record_en_falling_edge_sig),
+      .out_record_en_edge_sig        (signal_business_record_en_edge_sig),
+
       .sys_timecode_tigger_sig(sys_timecode_tigger_sig),
       .sys_timecode_data      (sys_timecode_data),
 
       .out_record_en_sig      (signal_business_record_en_sig),
       .out_record_exposure_sig(signal_business_record_exposure_sig)
   );
-
-  camera_sync_signal_output #(
-      .REG_START_ADD (`REGADDOFF__CAMERA_SYNC_OUT),
-      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
-  ) camera_sync_signal_output0 (
-      .clk  (sys_clk),
-      .rst_n(sys_rst_n),
-
-      .addr   (RegReaderBus_addr),
-      .wr_data(RegReaderBus_wr_data),
-      .wr_en  (RegReaderBus_wr_en),
-      .rd_data(rd_data_module_camera_sync_out),
-
-      .frame_sig    (signal_sys_clk_output),
-      .record_en_sig(signal_business_record_en_sig),
-
-      .stm32if_camera_sync_out        (before_delay__stm32if_camera_sync_out),
-      .stm32if_record_state_change_sig(before_delay__stm32if_start_signal_out),
-      .stm32if_timecode_tigger_sig(before_delay__stm32if_timecode_sync_out)
-  );
-
-  assign debug_signal_output[0]  = sys_clk;
-  assign debug_signal_output[1]  = sync_ttl_in1;
-  assign debug_signal_output[2]  = af_delay__sync_ttl_in1;
-  assign debug_signal_output[3]  = sync_ttl_in3;
-  assign debug_signal_output[4]  = sync_ttl_in4;
-  assign debug_signal_output[5]  = sync_ttl_out1;
-  assign debug_signal_output[6]  = sync_ttl_out2;
-  assign debug_signal_output[7]  = sync_ttl_out3;
-  assign debug_signal_output[8]  = sync_ttl_out4;
-  assign debug_signal_output[9]  = genlock_in_fsync;
-  assign debug_signal_output[10] = timecode_headphone_in;
-  assign debug_signal_output[11] = timecode_bnc_in;
+  */
+
+
+
+  assign debug_signal_output[0]  = timecode_bnc_in;
+  assign debug_signal_output[1]  = af_delay__timecode_headphone_in;
+  assign debug_signal_output[2]  = timecode_headphone_in;
+  assign debug_signal_output[3]  = sync_ttl_in1;
+  assign debug_signal_output[4]  = sync_ttl_in1;
+  //   assign debug_signal_output[5]  = af_delay__sync_ttl_in1;
+  //   assign debug_signal_output[6]  = af_delay__sync_ttl_in1;
+  //   assign debug_signal_output[7]  = af_delay__sync_ttl_in1;
+  //   assign debug_signal_output[8]  = af_delay__sync_ttl_in1;
+  //   assign debug_signal_output[9]  = af_delay__genlock_in_vsync;
+  //   assign debug_signal_output[10] = af_delay__timecode_headphone_in;
+  //   assign debug_signal_output[11] = af_delay__timecode_bnc_in;
   assign debug_signal_output[12] = timecode_out_headphone;
   assign debug_signal_output[13] = timecode_out_bnc;
   assign debug_signal_output[15] = 0;
diff --git a/source/src/zutils/zsimple_pll.v b/source/src/zutils/zsimple_pll.v
index d622add..bf74a65 100644
--- a/source/src/zutils/zsimple_pll.v
+++ b/source/src/zutils/zsimple_pll.v
@@ -27,7 +27,7 @@ module zsimple_pll (
 
   wire insignal_rising_edge;  //! 输入信号上升沿
   wire insignal_falling_edge;  //! 输入信号下降沿
-  wire insignal_trigger_sig;  //! 触发信号
+  reg insignal_trigger_sig;  //! 触发信号
   wire module_reset;  //! 模块内部复位信号
 
   reg  insignal_division;  //! 输入信号分频后的信号
@@ -44,7 +44,17 @@ module zsimple_pll (
   );
 
 
-  assign insignal_trigger_sig = trigger_eage_type ? insignal_rising_edge : insignal_falling_edge;
+  always @(*) begin
+    case (trigger_eage_type)
+      0: insignal_trigger_sig <= insignal_rising_edge;
+      1: insignal_trigger_sig <= insignal_rising_edge;
+      2: insignal_trigger_sig <= insignal_rising_edge;
+      default: 
+      insignal_trigger_sig <= insignal_rising_edge;
+    endcase
+  end
+
+  // assign insignal_trigger_sig = trigger_eage_type ? insignal_rising_edge : insignal_falling_edge;
   assign module_reset         = !rst_n || cfg_change;
 
   // 分频