update

.vscode/settings.json

@@ -1,6 +1,19 @@
 {
     "files.associations": {
         "*.hpp": "cpp",
-        "xtree": "cpp"
+        "xtree": "cpp",
+        "list": "cpp",
+        "system_error": "cpp",
+        "xlocale": "cpp",
+        "ostream": "cpp",
+        "xstring": "cpp",
+        "vector": "cpp",
+        "functional": "cpp",
+        "type_traits": "cpp",
+        "xlocmon": "cpp",
+        "xtr1common": "cpp",
+        "xutility": "cpp",
+        "iosfwd": "cpp",
+        "xiosbase": "cpp"
     }
 }

constraint_check/constraint_check.ccr

@@ -1,4 +1,4 @@
-##### Written on 2024/08/25 21:01:31 ###############################
+##### Written on 2024/08/25 22:23:43 ###############################
 
 
 ##### INFO ##################################################
@@ -14,12 +14,39 @@ Constraint File(s) :
 
 ##### SUMMARY ######################################################
 
-Found 0 error(s), 0 critical warning(s), 41 warning(s), out of 17 constraint(s)
+Found 0 error(s), 9 critical warning(s), 15 warning(s), out of 292 constraint(s)
 
 
 Inapplicable constraints(except overwritten constraints):
 ********************************************
 
+define_attribute {p:genlock_in_hsync} {PAP_IO_LOC} {M15}
+	C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 12)] | Port genlock_in_hsync has been placed at location M15, whose type is share pin.
+
+define_attribute {p:genlock_in_vsync} {PAP_IO_LOC} {M16}
+	C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 16)] | Port genlock_in_vsync has been placed at location M16, whose type is share pin.
+
+define_attribute {p:genlock_in_fsync} {PAP_IO_LOC} {L16}
+	C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 20)] | Port genlock_in_fsync has been placed at location L16, whose type is share pin.
+
+define_attribute {p:sync_ttl_in3} {PAP_IO_LOC} {M13}
+	C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 92)] | Port sync_ttl_in3 has been placed at location M13, whose type is share pin.
+
+define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {L13}
+	C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 96)] | Port sync_ttl_in4 has been placed at location L13, whose type is share pin.
+
+define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {L15}
+	C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 124)] | Port timecode_headphone_in has been placed at location L15, whose type is share pin.
+
+define_attribute {p:timecode_bnc_in} {PAP_IO_LOC} {L14}
+	C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 128)] | Port timecode_bnc_in has been placed at location L14, whose type is share pin.
+
+define_attribute {p:stm32if_camera_sync_out} {PAP_IO_LOC} {Y22}
+	C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 162)] | Port stm32if_camera_sync_out has been placed at location Y22, whose type is share pin.
+
+define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_LOC} {AB20}
+	C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 168)] | Port stm32if_timecode_sync_out has been placed at location AB20, whose type is share pin.
+
 
 Constraints with issues:
 ********************************************
@@ -32,46 +59,20 @@ Issues without commands:
 Unconstrained ports:
 ********************************************
 
-W: ConstraintEditor-4019: Port Bus 'debug_signal_output' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port Bus 'genlock_out_dac' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'genlock_in_fsync' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'genlock_in_hsync' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'genlock_in_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'genlock_in_vsync' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'genlock_out_dac_clk' unspecified I/O constraint.
+W: ConstraintEditor-4019: Port 'genlock_out_dac[9]' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'genlock_out_dac_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'spi1_clk_pin' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'spi1_cs_pin' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'spi1_rx_pin' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'spi1_tx_pin' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'stm32if_camera_sync_out' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'stm32if_start_signal_out' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'stm32if_timecode_sync_out' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'sync_ttl_in1' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'sync_ttl_in1_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'sync_ttl_in2' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'sync_ttl_in2_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'sync_ttl_in3' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'sync_ttl_in3_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'sync_ttl_in4' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'sync_ttl_in4_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'sync_ttl_out1' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'sync_ttl_out1_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'sync_ttl_out2' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'sync_ttl_out2_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'sync_ttl_out3' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'sync_ttl_out3_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'sync_ttl_out4' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'sync_ttl_out4_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'timecode_bnc_in' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'timecode_bnc_in_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'timecode_headphone_in' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'timecode_headphone_in_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'timecode_out_bnc' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'timecode_out_bnc_select' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'timecode_out_bnc_state_led' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'timecode_out_headphone' unspecified I/O constraint.
-W: ConstraintEditor-4019: Port 'timecode_out_headphone_select' unspecified I/O constraint.
 W: ConstraintEditor-4019: Port 'timecode_out_headphone_state_led' unspecified I/O constraint.
 
 Constraints with matching wildcard expressions:

multiseed_summary.csv

@@ -3,7 +3,7 @@ project name,xsync.pds
 
 Single Seed:
 Seed,State,Convergence,Setup(Slow),Setup(Fast),Hold(Slow),Hold(Fast),Recovery(Slow),Recovery(Fast),Removal(Slow),Removal(Fast),PBM-GP,PBM-PreGP,PBM-PostGP,LP,Total Placement Cpu Time,Detailed routing,Total Routing Cpu Time,Wire Length After Post-GP,Wire Length After LP,Wire Length After DP,Routing Arc Length,Worst Slack After GP Timing,Worst Slack After LP Timing,Worst Slack Before RP,Worst Slack Before DP,Worst Slack After DP,Worst Slack After Placement,Worst Slack After TA By Preroute,TNS After DP,TNS Before Route,Setup(Slow) Total Failing TNS,Setup(Slow) Total Failing Endpoints,Hold(Slow) Total Failing THS,Hold(Slow) Total Failing Endpoints,Power
-single,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,0.00,1.41,0.02,2.11,NA,NA,NA,672,NA,NA,997904,997904,997904,997904,NA,0,0,NA,NA,NA,NA,NA
+single,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,0.05,3.50,0.03,4.64,NA,NA,NA,665,NA,NA,997980,997980,997980,997980,NA,0,0,NA,NA,NA,NA,NA
 Pass Rate/Convergence Rate,0.00%,0.00%
 
 Synthesize:

pango_tools/fdc_generator.cpp

@@ -9,7 +9,7 @@
 using namespace iflytop;
 using namespace std;
 #define TAG "Main"
-
+#if 0
 /**
  * @brief
  *
@@ -52,8 +52,7 @@ int _main() {
   file.open(outputfilename, ios::out | ios::trunc);
 
   set<string> pins;
-
-  for (uint32_t i = 1; i < maxRow - 1; i++) {
+  for (uint32_t i = 1; i < maxRow; i++) {
     string pin       = zcsv->getdata(i + 1, 1);
     string name      = zcsv->getdata(i + 1, 2);
     string direction = zcsv->getdata(i + 1, 3);
@@ -97,3 +96,102 @@ int main(int argc, char const *argv[]) {
     Sleep(5000);
   }
 }
+#endif
+
+#define TRY_INSERT_DEFALUT_VALUE(key, value)                                                 \
+  if (zcsv->getData(key, i).empty() || zcsv->getData(key, i) == "NA") {                      \
+    file << "define_attribute {p:" << name << "} {" << key << "} {" << value << "}" << endl; \
+  }
+
+char inputfile[128] = {0};
+
+int domain(int argc, char const* argv[]) {
+  if (argc < 2) {
+    // 请输入文件名
+    cout << "please input file name" << endl;
+    cin >> inputfile;
+  } else {
+    strcpy(inputfile, argv[1]);
+  }
+
+  ZLOGI(TAG, "input file:%s", inputfile);
+  shared_ptr<ZCSV> zcsv = make_shared<ZCSV>();
+  bool             suc  = zcsv->parseCSV(inputfile);
+  if (!suc) {
+    ZLOGE(TAG, "parse csv failed");
+    return -1;
+  }
+
+  // 去掉.,获取文件名
+  string outputfilename;
+  string inputfilename = inputfile;
+  size_t pos           = inputfilename.find_last_of(".");
+  if (pos == string::npos) {
+    outputfilename = inputfilename;
+  } else {
+    outputfilename = inputfilename.substr(0, pos);
+  }
+
+  outputfilename += ".fdc";
+  map<string, int> colNum;
+
+  auto keys = zcsv->getRowKeys();
+
+  ofstream file;
+  file.open(outputfilename, ios::out | ios::trunc);
+  int maxRow = zcsv->maxRowNum();
+
+  for (uint32_t i = 1; i <= maxRow; i++) {
+    // 检查必要数值
+    string name             = zcsv->getData("NAME", i);
+    string PAP_IO_LOC       = zcsv->getData("PAP_IO_LOC", i);
+    string PAP_IO_DIRECTION = zcsv->getData("PAP_IO_DIRECTION", i);
+
+    if (name.empty() || name == "NA") {
+      ZLOGE(TAG, "line %d name is empty, skip", i + 1);
+      continue;
+    }
+    if (PAP_IO_LOC.empty() || PAP_IO_LOC == "NA") {
+      ZLOGE(TAG, "line %d PAP_IO_LOC is empty, skip", i + 1);
+      continue;
+    }
+
+    if (PAP_IO_DIRECTION.empty()) {
+      ZLOGE(TAG, "error!!!,line %d PAP_IO_DIRECTION is empty", i + 1);
+      return -1;
+    }
+
+    // 插入数值
+    vector<string> keys = zcsv->getRowKeys();
+    for (auto& key : keys) {
+      if (key == "NAME") continue;
+      if (zcsv->getData(key, i).empty()) continue;
+      if (zcsv->getData(key, i) == "NA") continue;
+      file << "define_attribute {p:" << name << "} {" << key << "} {" << zcsv->getData(key, i) << "}" << endl;
+    }
+
+    // // 尝试插入默认值
+    if (PAP_IO_DIRECTION == "INPUT") {
+      TRY_INSERT_DEFALUT_VALUE("PAP_IO_VCCIO", "3.3");
+      TRY_INSERT_DEFALUT_VALUE("PAP_IO_STANDARD", "LVTTL33");
+    } else if (PAP_IO_DIRECTION == "OUTPUT") {
+      TRY_INSERT_DEFALUT_VALUE("PAP_IO_VCCIO", "3.3");
+      TRY_INSERT_DEFALUT_VALUE("PAP_IO_STANDARD", "LVCMOS33");
+      TRY_INSERT_DEFALUT_VALUE("PAP_IO_DRIVE", "4");
+      TRY_INSERT_DEFALUT_VALUE("PAP_IO_SLEW", "SLOW");
+    } else {
+      ZLOGE(TAG, "error!!!,line %d PAP_IO_DIRECTION (%s) is error", i + 1, PAP_IO_DIRECTION.c_str());
+      return -1;
+    }
+  }
+  file.close();
+  ZLOGI(TAG, "generator %s success", outputfilename.c_str());
+  return 0;
+}
+
+int main(int argc, char const* argv[]) {
+  domain(argc, argv);
+  while (true) {
+    Sleep(5000);
+  }
+}

pango_tools/zcsv.cpp

@@ -14,14 +14,14 @@ bool ZCSV::parseCSV(string filename) {
     return false;
   }
 
-  int rowNum = 0;
+  int rowNum = -1;
   while (getline(file, line)) {
     rowNum = rowNum + 1;
     stringstream linestream(line);
     string       cell;
     ZCSVCell     csvCell;
     csvCell.rowNum = rowNum;
-    int colNum     = 0;
+    int colNum     = -1;
 
     while (getline(linestream, cell, ',')) {
       colNum         = colNum + 1;
@@ -34,7 +34,7 @@ bool ZCSV::parseCSV(string filename) {
   }
 
   // 找到最大行数
-  int maxRowNum = 0;
+  int maxRowNum = -1;
   for (list<ZCSVCell>::iterator it = csvData.begin(); it != csvData.end(); it++) {
     if (it->rowNum > maxRowNum) {
       maxRowNum = it->rowNum;
@@ -42,7 +42,7 @@ bool ZCSV::parseCSV(string filename) {
   }
 
   // 找到最大列数
-  int maxColNum = 0;
+  int maxColNum = -1;
   for (list<ZCSVCell>::iterator it = csvData.begin(); it != csvData.end(); it++) {
     if (it->colNum > maxColNum) {
       maxColNum = it->colNum;
@@ -92,36 +92,39 @@ string ZCSV::getdata(int rowNum, int colNum) {
     return "";
   }
 }
-
-void ZCSV::dumpCSV(string filename) {
-  ofstream file;
-  file.open(filename, ios::out | ios::trunc);
-
-  // 找到最大行数
-  int maxRowNum = 0;
-  for (list<ZCSVCell>::iterator it = csvData.begin(); it != csvData.end(); it++) {
-    if (it->rowNum > maxRowNum) {
-      maxRowNum = it->rowNum;
+int ZCSV::findCol(string key) {
+  int colNum = -1;
+  for (int i = 0; i <= m_maxColNum; i++) {
+    ZCSVCell* cell = findCell(0, i);
+    if (cell != NULL && cell->data == key) {
+      colNum = i;
+      break;
     }
   }
+  return colNum;
+}
 
-  // 找到最大列数
-  int maxColNum = 0;
-  for (list<ZCSVCell>::iterator it = csvData.begin(); it != csvData.end(); it++) {
-    if (it->colNum > maxColNum) {
-      maxColNum = it->colNum;
-    }
+bool ZCSV::isColExist(string key) {
+  int colNum = findCol(key);
+  if (colNum != -1) {
+    return true;
   }
-
-  // 足个点插入数据
-  for (int i = 1; i <= maxRowNum; i++) {
-    for (int j = 1; j <= maxColNum; j++) {
-      ZCSVCell* cell = findCell(i, j);
-      if (cell != NULL) {
-        file << cell->data;
-      }
-      file << ",";
+  return false;
+}
+string ZCSV::getData(string key, int rowNum) {
+  int colNum = findCol(key);
+  if (colNum == -1) {
+    return "";
+  }
+  return getdata(rowNum, colNum);
+}
+vector<string> ZCSV::getRowKeys() {
+  vector<string> keys;
+  for (int i = 0; i <= m_maxColNum; i++) {
+    ZCSVCell* cell = findCell(0, i);
+    if (cell != NULL) {
+      keys.push_back(cell->data);
     }
-    file << endl;
   }
+  return keys;
 }

pango_tools/zcsv.hpp

@@ -38,7 +38,11 @@ class ZCSV {
   int maxRowNum() { return m_maxRowNum; }
   int maxColNum() { return m_maxColNum; }
 
-  void dumpCSV(string filename);
+  bool   isColExist(string key);
+  int    findCol(string key);
+  string getData(string key, int rowNum);
+
+  vector<string> getRowKeys();
 
  private:
   ZCSVCell* findCell(int rowNum, int colNum);

pin.csv

@@ -1,68 +0,0 @@
-xsync.fdc,,
-R4,ex_clk,INPUT
-U7,ex_rst_n,INPUT
-M15,genlock_in_hsync,INPUT
-M16,genlock_in_vsync,INPUT
-L16,genlock_in_fsync,INPUT
-N/A,genlock_in_state_led,OUTPUT
-E14,genlock_out_dac[0],OUTPUT
-E13,genlock_out_dac[1],OUTPUT
-F14,genlock_out_dac[2],OUTPUT
-F13,genlock_out_dac[3],OUTPUT
-C22,genlock_out_dac[4],OUTPUT
-B22,genlock_out_dac[5],OUTPUT
-C20,genlock_out_dac[6],OUTPUT
-D20,genlock_out_dac[7],OUTPUT
-C19,genlock_out_dac[8],OUTPUT
-C18,genlock_out_dac_clk,OUTPUT
-,genlock_out_dac_state_led,OUTPUT
-K18,sync_ttl_in1,INPUT
-,sync_ttl_in1_state_led,OUTPUT
-K19,sync_ttl_in2,INPUT
-,sync_ttl_in2_state_led,OUTPUT
-M13,sync_ttl_in3,INPUT
-,sync_ttl_in3_state_led,OUTPUT
-L13,sync_ttl_in4,INPUT
-,sync_ttl_in4_state_led,OUTPUT
-AA8,sync_ttl_out1,OUTPUT
-,sync_ttl_out1_state_led,OUTPUT
-V9,sync_ttl_out2,OUTPUT
-,sync_ttl_out2_state_led,OUTPUT
-V8,sync_ttl_out3,OUTPUT
-,sync_ttl_out3_state_led,OUTPUT
-T6,sync_ttl_out4,OUTPUT
-,sync_ttl_out4_state_led,OUTPUT
-L15,timecode_headphone_in,INPUT
-,timecode_headphone_in_state_led,OUTPUT
-L14,timecode_bnc_in,INPUT
-,timecode_bnc_in_state_led,OUTPUT
-W9,timecode_out_bnc,OUTPUT
-R6,timecode_out_bnc_select,OUTPUT
-,timecode_out_bnc_state_led,OUTPUT
-Y9,timecode_out_headphone,OUTPUT
-T3,timecode_out_headphone_select,OUTPUT
-,timecode_out_headphone_state_led,OUTPUT
-Y21,stm32if_start_signal_out,OUTPUT
-Y22,stm32if_camera_sync_out,OUTPUT
-AB20,stm32if_timecode_sync_out,OUTPUT
-W7,spi1_cs_pin,INPUT
-V7,spi1_clk_pin,INPUT
-Y7,spi1_rx_pin,INPUT
-Y8,spi1_tx_pin,OUTPUT
-Y11,debug_signal_output[0],OUTPUT
-Y12,debug_signal_output[1],OUTPUT
-AA10,debug_signal_output[2],OUTPUT
-AA11,debug_signal_output[3],OUTPUT
-AB11,debug_signal_output[4],OUTPUT
-AB12,debug_signal_output[5],OUTPUT
-W11,debug_signal_output[6],OUTPUT
-W12,debug_signal_output[7],OUTPUT
-AA13,debug_signal_output[8],OUTPUT
-AB13,debug_signal_output[9],OUTPUT
-Y13,debug_signal_output[10],OUTPUT
-AA14,debug_signal_output[11],OUTPUT
-AA15,debug_signal_output[12],OUTPUT
-AB15,debug_signal_output[13],OUTPUT
-Y16,debug_signal_output[14],OUTPUT
-AA16,debug_signal_output[15],OUTPUT
-W5,core_board_debug_led,OUTPUT

xsync.csv

@@ -0,0 +1,68 @@
+NAME,PAP_IO_DIRECTION,PAP_IO_LOC,PAP_IO_VCCIO,PAP_IO_STANDARD,PAP_IO_NONE
+ex_clk,INPUT,R4,3.3,LVCMOS15,TRUE
+ex_rst_n,INPUT,U7,NA,NA,TRUE
+genlock_in_hsync,INPUT,M15,NA,NA,NA
+genlock_in_vsync,INPUT,M16,NA,NA,NA
+genlock_in_fsync,INPUT,L16,NA,NA,NA
+genlock_in_state_led,OUTPUT,NA,NA,NA,NA
+genlock_out_dac[0],OUTPUT,E14,NA,NA,NA
+genlock_out_dac[1],OUTPUT,E13,NA,NA,NA
+genlock_out_dac[2],OUTPUT,F14,NA,NA,NA
+genlock_out_dac[3],OUTPUT,F13,NA,NA,NA
+genlock_out_dac[4],OUTPUT,C22,NA,NA,NA
+genlock_out_dac[5],OUTPUT,B22,NA,NA,NA
+genlock_out_dac[6],OUTPUT,C20,NA,NA,NA
+genlock_out_dac[7],OUTPUT,D20,NA,NA,NA
+genlock_out_dac[8],OUTPUT,C19,NA,NA,NA
+genlock_out_dac_clk,OUTPUT,C18,NA,NA,NA
+genlock_out_dac_state_led,OUTPUT,NA,NA,NA,NA
+sync_ttl_in1,INPUT,K18,NA,NA,NA
+sync_ttl_in1_state_led,OUTPUT,NA,NA,NA,NA
+sync_ttl_in2,INPUT,K19,NA,NA,NA
+sync_ttl_in2_state_led,OUTPUT,NA,NA,NA,NA
+sync_ttl_in3,INPUT,M13,NA,NA,NA
+sync_ttl_in3_state_led,OUTPUT,NA,NA,NA,NA
+sync_ttl_in4,INPUT,L13,NA,NA,NA
+sync_ttl_in4_state_led,OUTPUT,NA,NA,NA,NA
+sync_ttl_out1,OUTPUT,AA8,NA,NA,NA
+sync_ttl_out1_state_led,OUTPUT,NA,NA,NA,NA
+sync_ttl_out2,OUTPUT,V9,NA,NA,NA
+sync_ttl_out2_state_led,OUTPUT,NA,NA,NA,NA
+sync_ttl_out3,OUTPUT,V8,NA,NA,NA
+sync_ttl_out3_state_led,OUTPUT,NA,NA,NA,NA
+sync_ttl_out4,OUTPUT,T6,NA,NA,NA
+sync_ttl_out4_state_led,OUTPUT,NA,NA,NA,NA
+timecode_headphone_in,INPUT,L15,NA,NA,NA
+timecode_headphone_in_state_led,OUTPUT,NA,NA,NA,NA
+timecode_bnc_in,INPUT,L14,NA,NA,NA
+timecode_bnc_in_state_led,OUTPUT,NA,NA,NA,NA
+timecode_out_bnc,OUTPUT,W9,NA,NA,NA
+timecode_out_bnc_select,OUTPUT,R6,NA,NA,NA
+timecode_out_bnc_state_led,OUTPUT,NA,NA,NA,NA
+timecode_out_headphone,OUTPUT,Y9,NA,NA,NA
+timecode_out_headphone_select,OUTPUT,T3,NA,NA,NA
+timecode_out_headphone_state_led,OUTPUT,NA,NA,NA,NA
+stm32if_start_signal_out,OUTPUT,Y21,NA,NA,NA
+stm32if_camera_sync_out,OUTPUT,Y22,NA,NA,NA
+stm32if_timecode_sync_out,OUTPUT,AB20,NA,NA,NA
+spi1_cs_pin,INPUT,W7,NA,NA,NA
+spi1_clk_pin,INPUT,V7,NA,NA,NA
+spi1_rx_pin,INPUT,Y7,NA,NA,NA
+spi1_tx_pin,OUTPUT,Y8,NA,NA,NA
+debug_signal_output[0],OUTPUT,Y11,NA,NA,NA
+debug_signal_output[1],OUTPUT,Y12,NA,NA,NA
+debug_signal_output[2],OUTPUT,AA10,NA,NA,NA
+debug_signal_output[3],OUTPUT,AA11,NA,NA,NA
+debug_signal_output[4],OUTPUT,AB11,NA,NA,NA
+debug_signal_output[5],OUTPUT,AB12,NA,NA,NA
+debug_signal_output[6],OUTPUT,W11,NA,NA,NA
+debug_signal_output[7],OUTPUT,W12,NA,NA,NA
+debug_signal_output[8],OUTPUT,AA13,NA,NA,NA
+debug_signal_output[9],OUTPUT,AB13,NA,NA,NA
+debug_signal_output[10],OUTPUT,Y13,NA,NA,NA
+debug_signal_output[11],OUTPUT,AA14,NA,NA,NA
+debug_signal_output[12],OUTPUT,AA15,NA,NA,NA
+debug_signal_output[13],OUTPUT,AB15,NA,NA,NA
+debug_signal_output[14],OUTPUT,Y16,NA,NA,NA
+debug_signal_output[15],OUTPUT,AA16,NA,NA,NA
+core_board_debug_led,OUTPUT,W5,NA,NA,NA

xsync.fdc

@@ -1,17 +1,292 @@
-define_attribute {p:core_board_debug_led} {PAP_IO_DIRECTION} {OUTPUT}
-define_attribute {p:core_board_debug_led} {PAP_IO_LOC} {W5}
-define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {1.5}
-define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS15}
-define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {8}
-define_attribute {p:core_board_debug_led} {PAP_IO_UNUSED} {TRUE}
-define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {FAST}
 define_attribute {p:ex_clk} {PAP_IO_DIRECTION} {INPUT}
 define_attribute {p:ex_clk} {PAP_IO_LOC} {R4}
-define_attribute {p:ex_clk} {PAP_IO_VCCIO} {1.5}
+define_attribute {p:ex_clk} {PAP_IO_VCCIO} {3.3}
 define_attribute {p:ex_clk} {PAP_IO_STANDARD} {LVCMOS15}
 define_attribute {p:ex_clk} {PAP_IO_NONE} {TRUE}
 define_attribute {p:ex_rst_n} {PAP_IO_DIRECTION} {INPUT}
 define_attribute {p:ex_rst_n} {PAP_IO_LOC} {U7}
-define_attribute {p:ex_rst_n} {PAP_IO_VCCIO} {1.5}
-define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVCMOS15}
 define_attribute {p:ex_rst_n} {PAP_IO_NONE} {TRUE}
+define_attribute {p:ex_rst_n} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:genlock_in_hsync} {PAP_IO_DIRECTION} {INPUT}
+define_attribute {p:genlock_in_hsync} {PAP_IO_LOC} {M15}
+define_attribute {p:genlock_in_hsync} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_in_hsync} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:genlock_in_vsync} {PAP_IO_DIRECTION} {INPUT}
+define_attribute {p:genlock_in_vsync} {PAP_IO_LOC} {M16}
+define_attribute {p:genlock_in_vsync} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_in_vsync} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:genlock_in_fsync} {PAP_IO_DIRECTION} {INPUT}
+define_attribute {p:genlock_in_fsync} {PAP_IO_LOC} {L16}
+define_attribute {p:genlock_in_fsync} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_in_fsync} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:genlock_out_dac[0]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:genlock_out_dac[0]} {PAP_IO_LOC} {E14}
+define_attribute {p:genlock_out_dac[0]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_out_dac[0]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:genlock_out_dac[0]} {PAP_IO_DRIVE} {4}
+define_attribute {p:genlock_out_dac[0]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:genlock_out_dac[1]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:genlock_out_dac[1]} {PAP_IO_LOC} {E13}
+define_attribute {p:genlock_out_dac[1]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_out_dac[1]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:genlock_out_dac[1]} {PAP_IO_DRIVE} {4}
+define_attribute {p:genlock_out_dac[1]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:genlock_out_dac[2]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:genlock_out_dac[2]} {PAP_IO_LOC} {F14}
+define_attribute {p:genlock_out_dac[2]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_out_dac[2]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:genlock_out_dac[2]} {PAP_IO_DRIVE} {4}
+define_attribute {p:genlock_out_dac[2]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:genlock_out_dac[3]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:genlock_out_dac[3]} {PAP_IO_LOC} {F13}
+define_attribute {p:genlock_out_dac[3]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_out_dac[3]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:genlock_out_dac[3]} {PAP_IO_DRIVE} {4}
+define_attribute {p:genlock_out_dac[3]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:genlock_out_dac[4]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:genlock_out_dac[4]} {PAP_IO_LOC} {C22}
+define_attribute {p:genlock_out_dac[4]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_out_dac[4]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:genlock_out_dac[4]} {PAP_IO_DRIVE} {4}
+define_attribute {p:genlock_out_dac[4]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:genlock_out_dac[5]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:genlock_out_dac[5]} {PAP_IO_LOC} {B22}
+define_attribute {p:genlock_out_dac[5]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_out_dac[5]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:genlock_out_dac[5]} {PAP_IO_DRIVE} {4}
+define_attribute {p:genlock_out_dac[5]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:genlock_out_dac[6]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:genlock_out_dac[6]} {PAP_IO_LOC} {C20}
+define_attribute {p:genlock_out_dac[6]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_out_dac[6]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:genlock_out_dac[6]} {PAP_IO_DRIVE} {4}
+define_attribute {p:genlock_out_dac[6]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:genlock_out_dac[7]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:genlock_out_dac[7]} {PAP_IO_LOC} {D20}
+define_attribute {p:genlock_out_dac[7]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_out_dac[7]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:genlock_out_dac[7]} {PAP_IO_DRIVE} {4}
+define_attribute {p:genlock_out_dac[7]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:genlock_out_dac[8]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:genlock_out_dac[8]} {PAP_IO_LOC} {C19}
+define_attribute {p:genlock_out_dac[8]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_out_dac[8]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:genlock_out_dac[8]} {PAP_IO_DRIVE} {4}
+define_attribute {p:genlock_out_dac[8]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:genlock_out_dac_clk} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:genlock_out_dac_clk} {PAP_IO_LOC} {C18}
+define_attribute {p:genlock_out_dac_clk} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:genlock_out_dac_clk} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:genlock_out_dac_clk} {PAP_IO_DRIVE} {4}
+define_attribute {p:genlock_out_dac_clk} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:sync_ttl_in1} {PAP_IO_DIRECTION} {INPUT}
+define_attribute {p:sync_ttl_in1} {PAP_IO_LOC} {K18}
+define_attribute {p:sync_ttl_in1} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:sync_ttl_in1} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:sync_ttl_in2} {PAP_IO_DIRECTION} {INPUT}
+define_attribute {p:sync_ttl_in2} {PAP_IO_LOC} {K19}
+define_attribute {p:sync_ttl_in2} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:sync_ttl_in2} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:sync_ttl_in3} {PAP_IO_DIRECTION} {INPUT}
+define_attribute {p:sync_ttl_in3} {PAP_IO_LOC} {M13}
+define_attribute {p:sync_ttl_in3} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:sync_ttl_in3} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:sync_ttl_in4} {PAP_IO_DIRECTION} {INPUT}
+define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {L13}
+define_attribute {p:sync_ttl_in4} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:sync_ttl_in4} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:sync_ttl_out1} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {AA8}
+define_attribute {p:sync_ttl_out1} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:sync_ttl_out1} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:sync_ttl_out1} {PAP_IO_DRIVE} {4}
+define_attribute {p:sync_ttl_out1} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:sync_ttl_out2} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:sync_ttl_out2} {PAP_IO_LOC} {V9}
+define_attribute {p:sync_ttl_out2} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:sync_ttl_out2} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:sync_ttl_out2} {PAP_IO_DRIVE} {4}
+define_attribute {p:sync_ttl_out2} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:sync_ttl_out3} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:sync_ttl_out3} {PAP_IO_LOC} {V8}
+define_attribute {p:sync_ttl_out3} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:sync_ttl_out3} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:sync_ttl_out3} {PAP_IO_DRIVE} {4}
+define_attribute {p:sync_ttl_out3} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:sync_ttl_out4} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {T6}
+define_attribute {p:sync_ttl_out4} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:sync_ttl_out4} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:sync_ttl_out4} {PAP_IO_DRIVE} {4}
+define_attribute {p:sync_ttl_out4} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:timecode_headphone_in} {PAP_IO_DIRECTION} {INPUT}
+define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {L15}
+define_attribute {p:timecode_headphone_in} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:timecode_headphone_in} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:timecode_bnc_in} {PAP_IO_DIRECTION} {INPUT}
+define_attribute {p:timecode_bnc_in} {PAP_IO_LOC} {L14}
+define_attribute {p:timecode_bnc_in} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:timecode_bnc_in} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:timecode_out_bnc} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:timecode_out_bnc} {PAP_IO_LOC} {W9}
+define_attribute {p:timecode_out_bnc} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:timecode_out_bnc} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:timecode_out_bnc} {PAP_IO_DRIVE} {4}
+define_attribute {p:timecode_out_bnc} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:timecode_out_bnc_select} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:timecode_out_bnc_select} {PAP_IO_LOC} {R6}
+define_attribute {p:timecode_out_bnc_select} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:timecode_out_bnc_select} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:timecode_out_bnc_select} {PAP_IO_DRIVE} {4}
+define_attribute {p:timecode_out_bnc_select} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:timecode_out_headphone} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:timecode_out_headphone} {PAP_IO_LOC} {Y9}
+define_attribute {p:timecode_out_headphone} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:timecode_out_headphone} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:timecode_out_headphone} {PAP_IO_DRIVE} {4}
+define_attribute {p:timecode_out_headphone} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:timecode_out_headphone_select} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:timecode_out_headphone_select} {PAP_IO_LOC} {T3}
+define_attribute {p:timecode_out_headphone_select} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:timecode_out_headphone_select} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:timecode_out_headphone_select} {PAP_IO_DRIVE} {4}
+define_attribute {p:timecode_out_headphone_select} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:stm32if_start_signal_out} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:stm32if_start_signal_out} {PAP_IO_LOC} {Y21}
+define_attribute {p:stm32if_start_signal_out} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:stm32if_start_signal_out} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:stm32if_start_signal_out} {PAP_IO_DRIVE} {4}
+define_attribute {p:stm32if_start_signal_out} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:stm32if_camera_sync_out} {PAP_IO_LOC} {Y22}
+define_attribute {p:stm32if_camera_sync_out} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:stm32if_camera_sync_out} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DRIVE} {4}
+define_attribute {p:stm32if_camera_sync_out} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_LOC} {AB20}
+define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DRIVE} {4}
+define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT}
+define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {W7}
+define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT}
+define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {V7}
+define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT}
+define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {Y7}
+define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVTTL33}
+define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {Y8}
+define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4}
+define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[0]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[0]} {PAP_IO_LOC} {Y11}
+define_attribute {p:debug_signal_output[0]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[0]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[0]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[0]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[1]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[1]} {PAP_IO_LOC} {Y12}
+define_attribute {p:debug_signal_output[1]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[1]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[1]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[1]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[2]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[2]} {PAP_IO_LOC} {AA10}
+define_attribute {p:debug_signal_output[2]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[2]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[2]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[2]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[3]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[3]} {PAP_IO_LOC} {AA11}
+define_attribute {p:debug_signal_output[3]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[3]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[3]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[3]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[4]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[4]} {PAP_IO_LOC} {AB11}
+define_attribute {p:debug_signal_output[4]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[4]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[4]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[4]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[5]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[5]} {PAP_IO_LOC} {AB12}
+define_attribute {p:debug_signal_output[5]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[5]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[5]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[5]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[6]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[6]} {PAP_IO_LOC} {W11}
+define_attribute {p:debug_signal_output[6]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[6]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[6]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[6]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[7]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[7]} {PAP_IO_LOC} {W12}
+define_attribute {p:debug_signal_output[7]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[7]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[7]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[7]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[8]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[8]} {PAP_IO_LOC} {AA13}
+define_attribute {p:debug_signal_output[8]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[8]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[8]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[8]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[9]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[9]} {PAP_IO_LOC} {AB13}
+define_attribute {p:debug_signal_output[9]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[9]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[9]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[9]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[10]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[10]} {PAP_IO_LOC} {Y13}
+define_attribute {p:debug_signal_output[10]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[10]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[10]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[10]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[11]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[11]} {PAP_IO_LOC} {AA14}
+define_attribute {p:debug_signal_output[11]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[11]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[11]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[11]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[12]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[12]} {PAP_IO_LOC} {AA15}
+define_attribute {p:debug_signal_output[12]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[12]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[12]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[12]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[13]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[13]} {PAP_IO_LOC} {AB15}
+define_attribute {p:debug_signal_output[13]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[13]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[13]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[13]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[14]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[14]} {PAP_IO_LOC} {Y16}
+define_attribute {p:debug_signal_output[14]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[14]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[14]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[14]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:debug_signal_output[15]} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:debug_signal_output[15]} {PAP_IO_LOC} {AA16}
+define_attribute {p:debug_signal_output[15]} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:debug_signal_output[15]} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:debug_signal_output[15]} {PAP_IO_DRIVE} {4}
+define_attribute {p:debug_signal_output[15]} {PAP_IO_SLEW} {SLOW}
+define_attribute {p:core_board_debug_led} {PAP_IO_DIRECTION} {OUTPUT}
+define_attribute {p:core_board_debug_led} {PAP_IO_LOC} {W5}
+define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {3.3}
+define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS33}
+define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {4}
+define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {SLOW}

xsync.pds

@@ -1,5 +1,5 @@
 (_flow fab_demo "2022.2-SP4.2"
-    (_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Sun Aug 25 21:02:11 2024")
+    (_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Sun Aug 25 22:25:16 2024")
     (_version "1.1.0")
     (_status "initial")
     (_project 
@@ -263,7 +263,7 @@
             (_input
                 (_file "xsync.fdc"
                     (_format fdc)
-                    (_timespec "2024-08-25T21:00:42")
+                    (_timespec "2024-08-25T22:23:28")
                 )
             )
         )
@@ -314,17 +314,17 @@
             (_db_output
                 (_file "compile/Top_comp.adf"
                     (_format adif)
-                    (_timespec "2024-08-25T21:01:25")
+                    (_timespec "2024-08-25T22:15:26")
                 )
             )
             (_output
                 (_file "compile/Top.cmr"
                     (_format verilog)
-                    (_timespec "2024-08-25T21:01:25")
+                    (_timespec "2024-08-25T22:15:26")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2024-08-25T21:01:25")
+                    (_timespec "2024-08-25T22:15:26")
                 )
             )
         )
@@ -339,25 +339,25 @@
             (_db_output
                 (_file "synthesize/Top_syn.adf"
                     (_format adif)
-                    (_timespec "2024-08-25T21:01:32")
+                    (_timespec "2024-08-25T22:23:43")
                 )
             )
             (_output
                 (_file "synthesize/Top_syn.vm"
                     (_format structural_verilog)
-                    (_timespec "2024-08-25T21:01:32")
+                    (_timespec "2024-08-25T22:23:43")
                 )
                 (_file "synthesize/Top_controlsets.txt"
                     (_format text)
-                    (_timespec "2024-08-25T21:01:32")
+                    (_timespec "2024-08-25T22:23:43")
                 )
                 (_file "synthesize/snr.db"
                     (_format text)
-                    (_timespec "2024-08-25T21:01:32")
+                    (_timespec "2024-08-25T22:23:44")
                 )
                 (_file "synthesize/Top.snr"
                     (_format text)
-                    (_timespec "2024-08-25T21:01:32")
+                    (_timespec "2024-08-25T22:23:44")
                 )
             )
         )
@@ -378,21 +378,21 @@
             (_db_output
                 (_file "device_map/Top_map.adf"
                     (_format adif)
-                    (_timespec "2024-08-25T21:01:41")
+                    (_timespec "2024-08-25T22:24:00")
                 )
             )
             (_output
                 (_file "device_map/Top_dmr.prt"
                     (_format text)
-                    (_timespec "2024-08-25T21:01:41")
+                    (_timespec "2024-08-25T22:24:00")
                 )
                 (_file "device_map/Top.dmr"
                     (_format text)
-                    (_timespec "2024-08-25T21:01:42")
+                    (_timespec "2024-08-25T22:24:00")
                 )
                 (_file "device_map/dmr.db"
                     (_format text)
-                    (_timespec "2024-08-25T21:01:42")
+                    (_timespec "2024-08-25T22:24:00")
                 )
             )
         )
@@ -401,7 +401,7 @@
             (_input
                 (_file "device_map/xsync.pcf"
                     (_format pcf)
-                    (_timespec "2024-08-25T21:01:41")
+                    (_timespec "2024-08-25T22:24:00")
                 )
             )
         )
@@ -422,33 +422,33 @@
             (_db_output
                 (_file "place_route/Top_pnr.adf"
                     (_format adif)
-                    (_timespec "2024-08-25T21:01:59")
+                    (_timespec "2024-08-25T22:24:52")
                 )
             )
             (_output
                 (_file "place_route/clock_utilization.txt"
                     (_format text)
-                    (_timespec "2024-08-25T21:01:59")
+                    (_timespec "2024-08-25T22:24:51")
                 )
                 (_file "place_route/Top_plc.adf"
                     (_format adif)
-                    (_timespec "2024-08-25T21:01:54")
+                    (_timespec "2024-08-25T22:24:30")
                 )
                 (_file "place_route/Top.prr"
                     (_format text)
-                    (_timespec "2024-08-25T21:01:59")
+                    (_timespec "2024-08-25T22:24:52")
                 )
                 (_file "place_route/Top_prr.prt"
                     (_format text)
-                    (_timespec "2024-08-25T21:01:59")
+                    (_timespec "2024-08-25T22:24:51")
                 )
                 (_file "place_route/Top_pnr.netlist"
                     (_format text)
-                    (_timespec "2024-08-25T21:01:59")
+                    (_timespec "2024-08-25T22:24:52")
                 )
                 (_file "place_route/prr.db"
                     (_format text)
-                    (_timespec "2024-08-25T21:01:59")
+                    (_timespec "2024-08-25T22:24:52")
                 )
             )
         )
@@ -484,19 +484,19 @@
             (_output
                 (_file "generate_bitstream/Top.sbit"
                     (_format text)
-                    (_timespec "2024-08-25T21:02:10")
+                    (_timespec "2024-08-25T22:25:13")
                 )
                 (_file "generate_bitstream/Top.smsk"
                     (_format text)
-                    (_timespec "2024-08-25T21:02:10")
+                    (_timespec "2024-08-25T22:25:13")
                 )
                 (_file "generate_bitstream/bgr.db"
                     (_format text)
-                    (_timespec "2024-08-25T21:02:11")
+                    (_timespec "2024-08-25T22:25:16")
                 )
                 (_file "generate_bitstream/Top.bgr"
                     (_format text)
-                    (_timespec "2024-08-25T21:02:11")
+                    (_timespec "2024-08-25T22:25:16")
                 )
             )
         )