reformat timecode decoder

source/src/timecode/timecode_decoder.v

@@ -11,18 +11,18 @@ module timecode_decoder #(
     /*******************************************************************************
      *                                TIMECODE输出                                 *
      *******************************************************************************/
-    output reg timecode_tigger_sig,
+    output reg        timecode_tigger_sig,
     output reg [63:0] timecode_data,
     // output [31:0] timecode_format,
-    output timecode_serial_data
+    output            timecode_serial_data
 );
 
-  // Rate      1/2Fe     1Fe
-  // 23.98 F/s 260.7 us 521.4 us
-  // 24.00 F/s 260.4 us 520.8 us
-  // 25.00 F/s 250.0 us 500.0 us 
-  // 29.97 F/s 208.5 us 417.1 us
-  // 30.00 F/s 208.3 us 416.7 us 
+  // Rate        us        1/2Fe     1Fe       1/2CNT      1CNT
+  // 23.98 F/s  41,701     260.7 us 521.4 us    2607       5214  
+  // 24.00 F/s  41,666     260.4 us 520.8 us    2604       5208
+  // 25.00 F/s  40,000     250.0 us 500.0 us    2500       5000
+  // 29.97 F/s  33,366     208.5 us 417.1 us    2085       4171
+  // 30.00 F/s  33,333     208.3 us 416.7 us    2083       4167
 
   // 260->520 -->130  
   // 208->416 -->104   
@@ -34,24 +34,26 @@ module timecode_decoder #(
 
   // 原始数据输出
   assign timecode_serial_data = timecode_in;
-  assign timecode_in_state = timecode_in;
+  assign timecode_in_state    = timecode_in;
 
   wire timecode_sample_sig_generator_rest_sig;
   wire timecode_in_edge;
   assign timecode_sample_sig_generator_rest_sig = !timecode_in_edge & rst_n;
+
   zutils_edge_detecter _signal_in (
-      .clk(clk),
-      .rst_n(rst_n),
-      .in_signal(timecode_in),
+      .clk           (clk),
+      .rst_n         (rst_n),
+      .in_signal     (timecode_in),
       .in_signal_edge(timecode_in_edge)
   );
+
   wire sample_sig;
   timecode_sample_sig_generator #(
       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
       .SAMPLE_RATE(854700)
   ) timecode_sample_sig_generator (
-      .clk(clk),
-      .rst_n(timecode_sample_sig_generator_rest_sig),
+      .clk       (clk),
+      .rst_n     (timecode_sample_sig_generator_rest_sig),
       .sample_sig(sample_sig)
   );
 
@@ -63,7 +65,7 @@ module timecode_decoder #(
       timecode_data_cache <= 0;
     end else begin
       if (sample_sig) begin
-        timecode_data_cache <= {timecode_in,timecode_data_cache[159:1]};
+        timecode_data_cache <= {timecode_in, timecode_data_cache[159:1]};
       end else begin
         timecode_data_cache <= timecode_data_cache;
       end
@@ -162,32 +164,33 @@ module timecode_decoder #(
 
   // 识别信号捕获
   wire [15:0] synccode;
-  assign synccode = timecode_bit_cache[79:64];
+  assign synccode         = timecode_bit_cache[79:64];
   assign detect_sync_code = (synccode == 16'b1011_1111_1111_1100);
 
 
   wire detect_sync_code_sig;
   zutils_edge_detecter detect_sync_code_detect (
-      .clk(clk),
-      .rst_n(rst_n),
-      .in_signal(detect_sync_code),
+      .clk                  (clk),
+      .rst_n                (rst_n),
+      .in_signal            (detect_sync_code),
       .in_signal_rising_edge(detect_sync_code_sig)
   );
 
   //输出时码识别信号
-
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
       timecode_tigger_sig <= 0;
-      timecode_data <= 0;
+      timecode_data       <= 0;
     end else begin
       if (detect_sync_code_sig) begin
         timecode_tigger_sig <= 1;
-        timecode_data <= timecode_bit_cache[63:0];
+        timecode_data       <= timecode_bit_cache[63:0];
       end else begin
         timecode_tigger_sig <= 0;
       end
     end
   end
 
+
+
 endmodule