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@ -17,12 +17,12 @@ module timecode_decoder #( |
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output timecode_serial_data |
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output timecode_serial_data |
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); |
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); |
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// Rate 1/2Fe 1Fe |
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// 23.98 F/s 260.7 us 521.4 us |
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// 24.00 F/s 260.4 us 520.8 us |
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// 25.00 F/s 250.0 us 500.0 us |
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// 29.97 F/s 208.5 us 417.1 us |
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// 30.00 F/s 208.3 us 416.7 us |
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// Rate us 1/2Fe 1Fe 1/2CNT 1CNT |
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// 23.98 F/s 41,701 260.7 us 521.4 us 2607 5214 |
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// 24.00 F/s 41,666 260.4 us 520.8 us 2604 5208 |
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// 25.00 F/s 40,000 250.0 us 500.0 us 2500 5000 |
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// 29.97 F/s 33,366 208.5 us 417.1 us 2085 4171 |
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// 30.00 F/s 33,333 208.3 us 416.7 us 2083 4167 |
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// 260->520 -->130 |
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// 260->520 -->130 |
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// 208->416 -->104 |
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// 208->416 -->104 |
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@ -39,19 +39,21 @@ module timecode_decoder #( |
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wire timecode_sample_sig_generator_rest_sig; |
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wire timecode_sample_sig_generator_rest_sig; |
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wire timecode_in_edge; |
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wire timecode_in_edge; |
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assign timecode_sample_sig_generator_rest_sig = !timecode_in_edge & rst_n; |
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assign timecode_sample_sig_generator_rest_sig = !timecode_in_edge & rst_n; |
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zutils_edge_detecter _signal_in ( |
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zutils_edge_detecter _signal_in ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.in_signal(timecode_in), |
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.clk (clk), |
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.rst_n (rst_n), |
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.in_signal (timecode_in), |
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.in_signal_edge(timecode_in_edge) |
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.in_signal_edge(timecode_in_edge) |
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); |
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); |
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wire sample_sig; |
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wire sample_sig; |
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timecode_sample_sig_generator #( |
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timecode_sample_sig_generator #( |
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
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.SAMPLE_RATE(854700) |
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.SAMPLE_RATE(854700) |
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) timecode_sample_sig_generator ( |
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) timecode_sample_sig_generator ( |
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.clk(clk), |
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.rst_n(timecode_sample_sig_generator_rest_sig), |
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.clk (clk), |
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.rst_n (timecode_sample_sig_generator_rest_sig), |
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.sample_sig(sample_sig) |
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.sample_sig(sample_sig) |
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); |
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); |
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@ -63,7 +65,7 @@ module timecode_decoder #( |
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timecode_data_cache <= 0; |
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timecode_data_cache <= 0; |
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end else begin |
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end else begin |
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if (sample_sig) begin |
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if (sample_sig) begin |
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timecode_data_cache <= {timecode_in,timecode_data_cache[159:1]}; |
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timecode_data_cache <= {timecode_in, timecode_data_cache[159:1]}; |
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end else begin |
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end else begin |
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timecode_data_cache <= timecode_data_cache; |
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timecode_data_cache <= timecode_data_cache; |
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end |
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end |
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@ -168,14 +170,13 @@ module timecode_decoder #( |
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wire detect_sync_code_sig; |
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wire detect_sync_code_sig; |
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zutils_edge_detecter detect_sync_code_detect ( |
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zutils_edge_detecter detect_sync_code_detect ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.in_signal(detect_sync_code), |
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.clk (clk), |
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.rst_n (rst_n), |
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.in_signal (detect_sync_code), |
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.in_signal_rising_edge(detect_sync_code_sig) |
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.in_signal_rising_edge(detect_sync_code_sig) |
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); |
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); |
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//输出时码识别信号 |
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//输出时码识别信号 |
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always @(posedge clk or negedge rst_n) begin |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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if (!rst_n) begin |
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timecode_tigger_sig <= 0; |
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timecode_tigger_sig <= 0; |
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@ -190,4 +191,6 @@ module timecode_decoder #( |
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end |
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end |
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end |
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end |
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endmodule |
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endmodule |
