diff --git a/led_test.pds b/led_test.pds index 815de4e..2d9f469 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Tue Mar 5 19:20:17 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Tue Mar 5 19:27:36 2024") (_version "1.0.5") (_status "initial") (_project @@ -369,8 +369,40 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) (_option mode (_string "fast")) + (_db_output + (_file "place_route/Top_pnr.adf" + (_format adif) + (_timespec "2024-03-05T19:26:10") + ) + ) + (_output + (_file "place_route/Top.prr" + (_format text) + (_timespec "2024-03-05T19:26:10") + ) + (_file "place_route/Top_prr.prt" + (_format text) + (_timespec "2024-03-05T19:26:08") + ) + (_file "place_route/clock_utilization.txt" + (_format text) + (_timespec "2024-03-05T19:26:08") + ) + (_file "place_route/Top_plc.adf" + (_format adif) + (_timespec "2024-03-05T19:21:27") + ) + (_file "place_route/Top_pnr.netlist" + (_format text) + (_timespec "2024-03-05T19:26:10") + ) + (_file "place_route/prr.db" + (_format text) + (_timespec "2024-03-05T19:26:12") + ) + ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -399,7 +431,25 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_output + (_file "generate_bitstream/Top.sbit" + (_format text) + (_timespec "2024-03-05T19:27:34") + ) + (_file "generate_bitstream/Top.smsk" + (_format text) + (_timespec "2024-03-05T19:27:34") + ) + (_file "generate_bitstream/Top.bgr" + (_format text) + (_timespec "2024-03-05T19:27:34") + ) + (_file "generate_bitstream/bgr.db" + (_format text) + (_timespec "2024-03-05T19:27:36") + ) + ) ) ) ) diff --git a/source/src/output/camera_sync_signal_output.v b/source/src/output/camera_sync_signal_output.v index 9e627f6..2451a70 100644 --- a/source/src/output/camera_sync_signal_output.v +++ b/source/src/output/camera_sync_signal_output.v @@ -1,10 +1,3 @@ -// -// @功能: -// 1. 功能:同步输出,脉冲输出 -// 2. 输出脉冲 -// 3. 输出脉冲时长可调 -// 4. 输出极性可调 -// module camera_sync_signal_output #( parameter REG_START_ADD = 0, parameter SYS_CLOCK_FREQ = 10000000 @@ -18,86 +11,73 @@ module camera_sync_signal_output #( input wr_en, output wire [31:0] rd_data, - input internal_genlock_sig, - input ext_genlock_sig, - input test_100hz_sig, + input frame_sig, + input record_en_sig, - output stm32if_camera_sync_out //ttl输出信号 + output stm32if_camera_sync_out, //ttl输出信号 + output stm32if_record_sync_out // ); - /******************************************************************************* * 寄存器列表 * *******************************************************************************/ - // - // 输入信号选择器 - // 0: 关闭 - // 1: 内部genlock - // 2: 外部genlock - // 31: 100HZ测试信号 - // - - wire [31:0] reg_input_signal_select; - // - // 脉冲模式-有效电平长度: - // 0~0xffffffff - // - wire [31:0] reg_pulse_mode_valid_len; // 脉冲模式-有效电平长度: 0~0xffffffff + reg [31:0] reg1_pulse_mode_valid_len; + wire [31:0] reg_wr_index; - zutils_register16 #( - .REG_START_ADD(REG_START_ADD), - .REG0_INIT(0), - .REG1_INIT(SYS_CLOCK_FREQ / 10000) //1ms + zutils_register_advanced #( + .REG_START_ADD(REG_START_ADD) ) _register ( - .clk(clk), - .rst_n(rst_n), - .addr(addr), - .wr_data(wr_data), - .wr_en(wr_en), - .rd_data(rd_data), - .reg0(reg_input_signal_select), - .reg1(reg_pulse_mode_valid_len) + .clk (clk), + .rst_n (rst_n), + .addr (addr), + .wr_data (wr_data), + .wr_en (wr_en), + .rd_data (rd_data), + .reg1 (reg1_pulse_mode_valid_len), + .reg_wr_sig(reg_wr_sig), + .reg_index (reg_wr_index) ); + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + reg1_pulse_mode_valid_len <= 0; + end else begin + if (reg_wr_sig) begin + case (reg_wr_index) + 1: reg1_pulse_mode_valid_len <= wr_data; + default: begin + end + endcase + end + end + end + /******************************************************************************* * 内部信号 * *******************************************************************************/ - wire in_signal_rising_edge; - wire signal_in_choose; - wire signal_pluse_output; - + wire frame_sig_rising_edge; + wire frame_sig_fa_process; - wire [31:0] signal_in; - assign signal_in[0] = 0; - assign signal_in[1] = internal_genlock_sig; - assign signal_in[2] = ext_genlock_sig; - assign signal_in[31] = test_100hz_sig; - - - zutils_multiplexer_32t1 _signal_select ( - .chooseindex(reg_input_signal_select), - .signal(signal_in), - .signalout(signal_in_choose) - ); // 边沿检测 zutils_edge_detecter _signal_in ( - .clk(clk), - .rst_n(rst_n), - .in_signal(signal_in_choose), - .in_signal_rising_edge(in_signal_rising_edge) + .clk (clk), + .rst_n (rst_n), + .in_signal (frame_sig), + .in_signal_rising_edge(frame_sig_rising_edge) ); // 短脉冲，触发生成，长脉冲 zutils_pluse_generator _pluse_generator ( - .clk(clk), - .rst_n(rst_n), - .pluse_width(reg_pulse_mode_valid_len), - .pluse_delay(0), - .trigger(in_signal_rising_edge), - .output_signal(signal_pluse_output) + .clk (clk), + .rst_n (rst_n), + .pluse_width (SYS_CLOCK_FREQ / 1000), //100us + .pluse_delay (0), + .trigger (frame_sig_rising_edge), + .output_signal(frame_sig_fa_process) ); - assign stm32if_camera_sync_out = signal_pluse_output; + assign stm32if_camera_sync_out = frame_sig_fa_process; + assign stm32if_record_sync_out = record_en_sig; endmodule