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@ -1,10 +1,3 @@ |
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// |
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// @功能: |
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// 1. 功能:同步输出,脉冲输出 |
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// 2. 输出脉冲 |
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// 3. 输出脉冲时长可调 |
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// 4. 输出极性可调 |
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// |
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module camera_sync_signal_output #( |
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module camera_sync_signal_output #( |
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parameter REG_START_ADD = 0, |
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parameter REG_START_ADD = 0, |
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parameter SYS_CLOCK_FREQ = 10000000 |
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parameter SYS_CLOCK_FREQ = 10000000 |
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@ -18,86 +11,73 @@ module camera_sync_signal_output #( |
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input wr_en, |
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input wr_en, |
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output wire [31:0] rd_data, |
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output wire [31:0] rd_data, |
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input internal_genlock_sig, |
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input ext_genlock_sig, |
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input test_100hz_sig, |
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input frame_sig, |
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input record_en_sig, |
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output stm32if_camera_sync_out //ttl输出信号 |
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output stm32if_camera_sync_out, //ttl输出信号 |
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output stm32if_record_sync_out // |
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); |
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); |
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/******************************************************************************* |
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/******************************************************************************* |
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* 寄存器列表 * |
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* 寄存器列表 * |
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*******************************************************************************/ |
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*******************************************************************************/ |
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// |
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// 输入信号选择器 |
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// 0: 关闭 |
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// 1: 内部genlock |
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// 2: 外部genlock |
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// 31: 100HZ测试信号 |
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// |
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wire [31:0] reg_input_signal_select; |
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// |
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// 脉冲模式-有效电平长度: |
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// 0~0xffffffff |
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// |
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wire [31:0] reg_pulse_mode_valid_len; // 脉冲模式-有效电平长度: 0~0xffffffff |
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reg [31:0] reg1_pulse_mode_valid_len; |
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wire [31:0] reg_wr_index; |
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zutils_register16 #( |
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.REG_START_ADD(REG_START_ADD), |
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.REG0_INIT(0), |
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.REG1_INIT(SYS_CLOCK_FREQ / 10000) //1ms |
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zutils_register_advanced #( |
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.REG_START_ADD(REG_START_ADD) |
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) _register ( |
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) _register ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.addr(addr), |
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.wr_data(wr_data), |
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.wr_en(wr_en), |
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.rd_data(rd_data), |
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.reg0(reg_input_signal_select), |
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.reg1(reg_pulse_mode_valid_len) |
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.clk (clk), |
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.rst_n (rst_n), |
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.addr (addr), |
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.wr_data (wr_data), |
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.wr_en (wr_en), |
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.rd_data (rd_data), |
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.reg1 (reg1_pulse_mode_valid_len), |
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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); |
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); |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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reg1_pulse_mode_valid_len <= 0; |
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end else begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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1: reg1_pulse_mode_valid_len <= wr_data; |
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default: begin |
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end |
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endcase |
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end |
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end |
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end |
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/******************************************************************************* |
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/******************************************************************************* |
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* 内部信号 * |
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* 内部信号 * |
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*******************************************************************************/ |
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*******************************************************************************/ |
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wire in_signal_rising_edge; |
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wire signal_in_choose; |
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wire signal_pluse_output; |
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wire frame_sig_rising_edge; |
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wire frame_sig_fa_process; |
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wire [31:0] signal_in; |
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assign signal_in[0] = 0; |
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assign signal_in[1] = internal_genlock_sig; |
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assign signal_in[2] = ext_genlock_sig; |
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assign signal_in[31] = test_100hz_sig; |
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zutils_multiplexer_32t1 _signal_select ( |
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.chooseindex(reg_input_signal_select), |
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.signal(signal_in), |
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.signalout(signal_in_choose) |
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); |
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// 边沿检测 |
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// 边沿检测 |
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zutils_edge_detecter _signal_in ( |
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zutils_edge_detecter _signal_in ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.in_signal(signal_in_choose), |
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.in_signal_rising_edge(in_signal_rising_edge) |
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.clk (clk), |
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.rst_n (rst_n), |
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.in_signal (frame_sig), |
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.in_signal_rising_edge(frame_sig_rising_edge) |
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); |
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); |
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// 短脉冲，触发生成，长脉冲 |
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// 短脉冲，触发生成，长脉冲 |
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zutils_pluse_generator _pluse_generator ( |
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zutils_pluse_generator _pluse_generator ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.pluse_width(reg_pulse_mode_valid_len), |
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.pluse_delay(0), |
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.trigger(in_signal_rising_edge), |
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.output_signal(signal_pluse_output) |
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.clk (clk), |
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.rst_n (rst_n), |
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.pluse_width (SYS_CLOCK_FREQ / 1000), //100us |
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.pluse_delay (0), |
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.trigger (frame_sig_rising_edge), |
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.output_signal(frame_sig_fa_process) |
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); |
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); |
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assign stm32if_camera_sync_out = signal_pluse_output; |
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assign stm32if_camera_sync_out = frame_sig_fa_process; |
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assign stm32if_record_sync_out = record_en_sig; |
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endmodule |
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endmodule |
