From 9ae890b2cfe3540a0e0075b7bc2585d97d7806cd Mon Sep 17 00:00:00 2001 From: zhaohe Date: Tue, 5 Mar 2024 19:12:46 +0800 Subject: [PATCH] update --- led_test.pds | 58 +++++++++++------------ source/src/config.v | 19 +++++++- source/src/input/genlock_input_module.v | 8 ++-- source/src/internal/internal_clock_generator.v | 2 +- source/src/sys/sys_clock.v | 2 +- source/src/top.v | 65 +++++++++++++++++--------- 6 files changed, 97 insertions(+), 57 deletions(-) diff --git a/led_test.pds b/led_test.pds index 1ea9f50..ef40965 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Tue Mar 5 13:00:07 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Tue Mar 5 18:16:08 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-03-05T12:38:35") + (_timespec "2024-03-05T16:15:17") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -187,11 +187,11 @@ ) (_file "source/src/input/genlock_input_module.v" (_format verilog) - (_timespec "2024-03-05T12:23:00") + (_timespec "2024-03-05T16:12:36") ) (_file "source/src/internal/internal_clock_generator.v" (_format verilog) - (_timespec "2024-03-05T12:36:42") + (_timespec "2024-03-05T18:04:44") ) (_file "source/src/internal/internal_genlock_generator.v" (_format verilog) @@ -199,11 +199,11 @@ ) (_file "source/src/sys/sys_genlock.v" (_format verilog) - (_timespec "2024-03-05T12:23:28") + (_timespec "2024-03-05T16:10:48") ) (_file "source/src/sys/sys_clock.v" (_format verilog) - (_timespec "2024-03-05T12:37:42") + (_timespec "2024-03-05T16:10:23") ) ) ) @@ -275,17 +275,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-03-05T12:58:02") + (_timespec "2024-03-05T18:04:58") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-03-05T12:58:00") + (_timespec "2024-03-05T18:04:55") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-03-05T12:58:02") + (_timespec "2024-03-05T18:04:58") ) ) ) @@ -301,21 +301,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-03-05T12:58:28") + (_timespec "2024-03-05T18:07:21") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-03-05T12:58:29") + (_timespec "2024-03-05T18:07:32") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-03-05T12:58:31") + (_timespec "2024-03-05T18:07:39") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-03-05T12:58:31") + (_timespec "2024-03-05T18:07:40") ) ) ) @@ -336,21 +336,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-03-05T12:58:37") + (_timespec "2024-03-05T18:07:55") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-03-05T12:58:35") + (_timespec "2024-03-05T18:07:43") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-03-05T12:58:37") + (_timespec "2024-03-05T18:07:55") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-03-05T12:58:38") + (_timespec "2024-03-05T18:07:55") ) ) ) @@ -359,7 +359,7 @@ (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-03-05T12:58:37") + (_timespec "2024-03-05T18:07:55") ) ) ) @@ -374,33 +374,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-03-05T12:59:48") + (_timespec "2024-03-05T18:14:38") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-03-05T12:59:48") + (_timespec "2024-03-05T18:14:38") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-03-05T12:59:48") + (_timespec "2024-03-05T18:14:36") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-03-05T12:59:48") + (_timespec "2024-03-05T18:14:36") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-03-05T12:58:52") + (_timespec "2024-03-05T18:09:05") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-03-05T12:59:48") + (_timespec "2024-03-05T18:14:38") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-03-05T12:59:49") + (_timespec "2024-03-05T18:14:40") ) ) ) @@ -435,19 +435,19 @@ (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-03-05T13:00:07") + (_timespec "2024-03-05T18:16:06") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-03-05T13:00:07") + (_timespec "2024-03-05T18:16:06") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-03-05T13:00:07") + (_timespec "2024-03-05T18:16:06") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-03-05T13:00:07") + (_timespec "2024-03-05T18:16:08") ) ) ) diff --git a/source/src/config.v b/source/src/config.v index 53011b3..98ba679 100644 --- a/source/src/config.v +++ b/source/src/config.v @@ -18,4 +18,21 @@ `define REGADDOFF__RECORD_SIG_GENERATOR 16'h0500 -`define FREQ_DETECT_BIAS_DEFAULT 32'd10 \ No newline at end of file +`define FREQ_DETECT_BIAS_DEFAULT 32'd10 + +`define SIGNAL_LOGIC0 32'd0 +`define SIGNAL_LOGIC1 32'd1 +`define SIGNAL_TTLIN1 32'd2 +`define SIGNAL_TTLIN2 32'd3 +`define SIGNAL_TTLIN3 32'd4 +`define SIGNAL_TTLIN4 32'd5 +`define SIGNAL_EXT_GENLOCK_FREQ 32'd6 +`define SIGNAL_EXT_TIMECODE_FREQ 32'd7 +`define SIGNAL_INTERNAL_TIMECODE_FREQ 32'd8 +`define SIGNAL_INTERNAL_GENLOCK_FREQ 32'd9 +`define SIGNAL_INTERNAL_CLOCK_SIG 32'd10 +`define SIGNAL_SYS_CLK_OUTPUT 32'd11 +`define SIGNAL_SYS_GENLOCK_OUTPUT 32'd12 +`define SIGNAL_SYS_TIMECODE_FREQ_OUTPUT 32'd13 +`define SIGNAL_BUSINESS_RECORD_SIG 32'd14 +`define SIGNAL_BUSINESS_RECORD_EXPOSURE_SIG 32'd15 diff --git a/source/src/input/genlock_input_module.v b/source/src/input/genlock_input_module.v index 14551de..89d95f8 100644 --- a/source/src/input/genlock_input_module.v +++ b/source/src/input/genlock_input_module.v @@ -16,14 +16,14 @@ module genlock_input_module #( input genlock_in_vsync, //! genlock vsync input genlock_in_fsync, //! genlock fsync - output genlock_freq_signal, //! genlock freq signal - output genlock_in_state_led + output genlock_freq_signal, //! genlock freq signal + output genlock_in_state_led ); reg [31:0] r1_genlock_freq_detect_bias; - reg [31:0] r2_genlock_freq; + wire [31:0] r2_genlock_freq; wire [31:0] reg_wr_index; zutils_register_advanced #( @@ -59,7 +59,7 @@ module genlock_input_module #( .clk (clk), .rst_n (rst_n), .freq_detect_bias(r1_genlock_freq_detect_bias), - .pluse_input (ttlin1_sig_af_filter), + .pluse_input (genlock_in_vsync), .pluse_width_cnt (r2_genlock_freq) ); diff --git a/source/src/internal/internal_clock_generator.v b/source/src/internal/internal_clock_generator.v index d69d207..bae3a0b 100644 --- a/source/src/internal/internal_clock_generator.v +++ b/source/src/internal/internal_clock_generator.v @@ -43,7 +43,7 @@ module internal_clock_generator #( if (!rst_n) begin r1_contrl_mode <= 0; r2_en <= 1; - r3_setting_cnt <= 0; + r3_setting_cnt <= (32'd1_000_000 - 32'd1); end else begin if (reg_wr_sig) begin case (reg_wr_index) diff --git a/source/src/sys/sys_clock.v b/source/src/sys/sys_clock.v index 3e5980f..595703a 100644 --- a/source/src/sys/sys_clock.v +++ b/source/src/sys/sys_clock.v @@ -57,7 +57,7 @@ module sys_clock #( always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - reg1_sig_src <= 0; + reg1_sig_src <= `SIGNAL_INTERNAL_CLOCK_SIG; //!默认为内部时钟 reg2_freq_division_ctrl <= 0; reg3_freq_multiplication_ctrl <= 0; reg4_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; diff --git a/source/src/top.v b/source/src/top.v index dc897a0..c461578 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -142,27 +142,28 @@ module Top ( wire [31:0] sig_src; // 系统内部信号总线 - assign sig_src[0] = signal_logic0; - assign sig_src[1] = signal_logic1; - assign sig_src[2] = signal_ttlin1; - assign sig_src[3] = signal_ttlin2; - assign sig_src[4] = signal_ttlin3; - assign sig_src[5] = signal_ttlin4; - assign sig_src[6] = signal_ext_genlock_freq; - assign sig_src[7] = signal_ext_timecode_freq; - assign sig_src[8] = signal_internal_timecode_freq; - assign sig_src[9] = signal_internal_genlock_freq; - assign sig_src[10] = signal_internal_clk_sig; - assign sig_src[11] = signal_sys_clk_output; - assign sig_src[12] = signal_sys_genlock_output; - assign sig_src[13] = signal_sys_timecode_freq_output; - assign sig_src[14] = signal_business_record_sig; - assign sig_src[15] = signal_business_record_exposure_sig; - - assign signal_logic0 = 1'b0; - assign signal_logic1 = 1'b1; - assign signal_internal_timecode_freq = internal_timecode_serial_data; - assign signal_sys_timecode_freq_output = sys_timecode_tigger_sig; + + assign sig_src[`SIGNAL_LOGIC0] = signal_logic0; + assign sig_src[`SIGNAL_LOGIC1] = signal_logic1; + assign sig_src[`SIGNAL_TTLIN1] = signal_ttlin1; + assign sig_src[`SIGNAL_TTLIN2] = signal_ttlin2; + assign sig_src[`SIGNAL_TTLIN3] = signal_ttlin3; + assign sig_src[`SIGNAL_TTLIN4] = signal_ttlin4; + assign sig_src[`SIGNAL_EXT_GENLOCK_FREQ] = signal_ext_genlock_freq; + assign sig_src[`SIGNAL_EXT_TIMECODE_FREQ] = signal_ext_timecode_freq; + assign sig_src[`SIGNAL_INTERNAL_TIMECODE_FREQ] = signal_internal_timecode_freq; + assign sig_src[`SIGNAL_INTERNAL_GENLOCK_FREQ] = signal_internal_genlock_freq; + assign sig_src[`SIGNAL_INTERNAL_CLOCK_SIG] = signal_internal_clk_sig; + assign sig_src[`SIGNAL_SYS_CLK_OUTPUT] = signal_sys_clk_output; + assign sig_src[`SIGNAL_SYS_GENLOCK_OUTPUT] = signal_sys_genlock_output; + assign sig_src[`SIGNAL_SYS_TIMECODE_FREQ_OUTPUT] = signal_sys_timecode_freq_output; + assign sig_src[`SIGNAL_BUSINESS_RECORD_SIG] = signal_business_record_sig; + assign sig_src[`SIGNAL_BUSINESS_RECORD_EXPOSURE_SIG] = signal_business_record_exposure_sig; + + assign signal_logic0 = 1'b0; + assign signal_logic1 = 1'b1; + assign signal_internal_timecode_freq = internal_timecode_serial_data; + assign signal_sys_timecode_freq_output = sys_timecode_tigger_sig; //系统时钟源 @@ -299,6 +300,28 @@ module Top ( .timecode_bnc_in_state_led (timecode_bnc_in_state_led) ); + genlock_input_module #( + .REG_START_ADD (`REGADDOFF__GENLOCK_IN), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) genlock_input ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_genlock_in), + + .genlock_in_hsync(genlock_in_hsync), + .genlock_in_vsync(genlock_in_vsync), + .genlock_in_fsync(genlock_in_fsync), + + .genlock_freq_signal (signal_ext_genlock_freq), + .genlock_in_state_led(genlock_in_state_led) + ); + + // + /******************************************************************************* * 内部信号源 * *******************************************************************************/