diff --git a/constraint_check/constraint_check.ccr b/constraint_check/constraint_check.ccr
index 0e31ee8..979d644 100644
--- a/constraint_check/constraint_check.ccr
+++ b/constraint_check/constraint_check.ccr
@@ -1,4 +1,4 @@
-##### Written on 2024/08/28 18:19:19 ###############################
+##### Written on 2024/08/28 18:35:47 ###############################
##### INFO ##################################################
diff --git a/ipcore/SPLL/.last_generated b/ipcore/SPLL/.last_generated
index dfaddc2..b839fe9 100644
--- a/ipcore/SPLL/.last_generated
+++ b/ipcore/SPLL/.last_generated
@@ -1,2 +1,2 @@
-2024-08-23 14:44
+2024-08-28 18:24
rev_1
\ No newline at end of file
diff --git a/ipcore/SPLL/SPLL.idf b/ipcore/SPLL/SPLL.idf
index 8d047fa..9f49870 100644
--- a/ipcore/SPLL/SPLL.idf
+++ b/ipcore/SPLL/SPLL.idf
@@ -5,13 +5,13 @@
041001
PLL
28nm PLL
- 1.2
+ 1.3
SPLL
Logos2
PG2L100H
FBG484
-6
- IP Compiler
+ IP Compiler
@@ -1422,6 +1422,7 @@
diff --git a/ipcore/SPLL/SPLL.v b/ipcore/SPLL/SPLL.v
index 0a3c7e5..167055a 100644
--- a/ipcore/SPLL/SPLL.v
+++ b/ipcore/SPLL/SPLL.v
@@ -1,5 +1,3 @@
-// Created by IP Generator (Version 2021.1-SP7 build 86875)
-
//////////////////////////////////////////////////////////////////////////////
//
@@ -301,7 +299,6 @@ module SPLL (
.INTERNAL_FB (INTERNAL_FB ),
.EXTERNAL_FB (EXTERNAL_FB ),
-
.BANDWIDTH (BANDWIDTH )
) u_gpll (
diff --git a/ipcore/SPLL/SPLL_tb.v b/ipcore/SPLL/SPLL_tb.v
index a69c74e..4abecfc 100644
--- a/ipcore/SPLL/SPLL_tb.v
+++ b/ipcore/SPLL/SPLL_tb.v
@@ -1,5 +1,3 @@
-// Created by IP Generator (Version 2021.1-SP7 build 86875)
-
//////////////////////////////////////////////////////////////////////////////
@@ -172,7 +170,7 @@ SPLL U_SPLL(
-//******************Results Cheching************************
+//******************Results Checking************************
reg lock_ff1 = 1'b0;
reg lock_ff2 = 1'b0;
reg lock_ff3 = 1'b0;
diff --git a/ipcore/SPLL/SPLL_tmpl.v b/ipcore/SPLL/SPLL_tmpl.v
index 5fcf6e0..5dbb140 100644
--- a/ipcore/SPLL/SPLL_tmpl.v
+++ b/ipcore/SPLL/SPLL_tmpl.v
@@ -1,4 +1,4 @@
-// Created by IP Generator (Version 2021.1-SP7 build 86875)
+// Created by IP Generator (Version 2022.2-SP4.2 build 132111)
// Instantiation Template
//
// Insert the following codes into your Verilog file.
diff --git a/ipcore/SPLL/SPLL_tmpl.vhdl b/ipcore/SPLL/SPLL_tmpl.vhdl
index 56fe060..aedfbfb 100644
--- a/ipcore/SPLL/SPLL_tmpl.vhdl
+++ b/ipcore/SPLL/SPLL_tmpl.vhdl
@@ -1,4 +1,4 @@
--- Created by IP Generator (Version 2021.1-SP7 build 86875)
+-- Created by IP Generator (Version 2022.2-SP4.2 build 132111)
-- Instantiation Template
--
-- Insert the following codes into your VHDL file.
diff --git a/ipcore/SPLL/generate.log b/ipcore/SPLL/generate.log
index 8dabeda..c937209 100644
--- a/ipcore/SPLL/generate.log
+++ b/ipcore/SPLL/generate.log
@@ -1,8 +1,8 @@
-IP Generator (Version 2021.1-SP7 build 86875)
+IP Generator (Version 2022.2-SP4.2 build 132111)
Check out license ...
-Start generating at 2024-08-23 14:44
+Start generating at 2024-08-28 18:24
Instance: SPLL (D:\workspace\p_lusterinc_xsync\xsync_fpge_v2\ipcore\SPLL\SPLL.idf)
-IP: PLL (1.2)
+IP: Pango PLL (1.3)
Part: Logos2-PG2L100H-FBG484--6
Create directory 'rtl' ...
Copy 'ipm2l_pll_wrapper_v1_1.v.xml' ...
diff --git a/multiseed_summary.csv b/multiseed_summary.csv
index 6131ab0..99e5f73 100644
--- a/multiseed_summary.csv
+++ b/multiseed_summary.csv
@@ -3,11 +3,11 @@ project name,xsync.pds
Single Seed:
Seed,State,Convergence,Setup(Slow),Setup(Fast),Hold(Slow),Hold(Fast),Recovery(Slow),Recovery(Fast),Removal(Slow),Removal(Fast),PBM-GP,PBM-PreGP,PBM-PostGP,LP,Total Placement Cpu Time,Detailed routing,Total Routing Cpu Time,Wire Length After Post-GP,Wire Length After LP,Wire Length After DP,Routing Arc Length,Worst Slack After GP Timing,Worst Slack After LP Timing,Worst Slack Before RP,Worst Slack Before DP,Worst Slack After DP,Worst Slack After Placement,Worst Slack After TA By Preroute,TNS After DP,TNS Before Route,Setup(Slow) Total Failing TNS,Setup(Slow) Total Failing Endpoints,Hold(Slow) Total Failing THS,Hold(Slow) Total Failing Endpoints,Power
-single,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,0.03,4.62,1.14,5.58,NA,NA,NA,10319,NA,NA,995944,995944,995944,995944,NA,0,0,NA,NA,NA,NA,NA
+single,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA
Pass Rate/Convergence Rate,0.00%,0.00%
Synthesize:
-control_set,38
+control_set,37
Synthesize Performance Summary:
slack category,Synthesize Setup WNS,Synthesize Setup TNS,Synthesize Recovery WNS,Synthesize Recovery TNS
slack value,995.809,0.000,NA,NA
@@ -16,10 +16,10 @@ Synthesize Process Cpu Time,0h:0m:3s
Device Map:
Device Map Resource Usage Summary:
Logic Utilization,LUT,FF,DRM,APM,Distributed RAM,HSSTHP,USCM,HCKB,RCKB
-Used,561,744,0,0,0,NA,2,0,0
-Available,66600,133200,155,240,19900,NA,32,96,24
-Utilization(%),1%,1%,0%,0%,0%,NA,7%,0%,0%
-Device Map Process Cpu Time,0h:0m:2s
+Used,NA,NA,NA,NA,NA,NA,NA,NA,NA
+Available,NA,NA,NA,NA,NA,NA,NA,NA,NA
+Utilization(%),NA,NA,NA,NA,NA,NA,NA,NA,NA
+Device Map Process Cpu Time,NA
Project Configurations:
top module,Top
diff --git a/source/src/top.v b/source/src/top.v
index f6b714b..27b0312 100644
--- a/source/src/top.v
+++ b/source/src/top.v
@@ -65,7 +65,7 @@ module Top (
output [15:0] debug_signal_output,
- output core_board_debug_led
+ output core_board_debug_led
);
/***********************************************************************************************************************
@@ -85,15 +85,14 @@ module Top (
.clkout2(sys_clk_5m)
);
assign sys_clk = sys_clk_10m;
- assign sys_rst_n = ex_rst_n & pll_lock;
-
+ assign sys_rst_n = pll_lock;
/***********************************************************************************************************************
* 调试指示灯 *
***********************************************************************************************************************/
breathing_lamp breathing_lamp_ins (
- .clk (ex_clk),
- .rst_n (ex_rst_n),
+ .clk (sys_clk),
+ .rst_n (sys_rst_n),
.lampio(core_board_debug_led)
);
/***********************************************************************************************************************
diff --git a/source/src/zutils/breathing_lamp.v b/source/src/zutils/breathing_lamp.v
index c5fac09..cf363e3 100644
--- a/source/src/zutils/breathing_lamp.v
+++ b/source/src/zutils/breathing_lamp.v
@@ -9,9 +9,9 @@ module breathing_lamp (
* 呼吸灯输出 *
***********************************************************************************************************************/
//parameter define
- parameter CNT_2US_MAX = 7'd100;
- parameter CNT_2MS_MAX = 10'd1000;
- parameter CNT_2S_MAX = 10'd1000;
+ parameter CNT_2US_MAX = 7'd20;
+ parameter CNT_2MS_MAX = 10'd200;
+ parameter CNT_2S_MAX = 10'd200;
//reg define
reg [6:0] cnt_2us;
diff --git a/xsync.pds b/xsync.pds
index e8139da..1b4de29 100644
--- a/xsync.pds
+++ b/xsync.pds
@@ -1,5 +1,5 @@
(_flow fab_demo "2022.2-SP4.2"
- (_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2) at Wed Aug 28 18:21:09 2024")
+ (_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2) at Wed Aug 28 18:35:49 2024")
(_version "1.1.0")
(_status "initial")
(_project
@@ -21,7 +21,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
- (_timespec "2024-08-28T18:03:33")
+ (_timespec "2024-08-28T18:33:07")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@@ -237,7 +237,7 @@
)
(_file "source/src/zutils/breathing_lamp.v"
(_format verilog)
- (_timespec "2024-08-28T18:00:19")
+ (_timespec "2024-08-28T18:35:30")
)
)
)
@@ -256,9 +256,9 @@
)
)
(_ip "ipcore/SPLL/SPLL.idf"
- (_timespec "2024-08-23T14:44:49")
+ (_timespec "2024-08-28T18:24:17")
(_ip_source_item "ipcore/SPLL/SPLL.v"
- (_timespec "2024-08-23T14:44:49")
+ (_timespec "2024-08-28T18:24:17")
)
)
)
@@ -318,17 +318,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
- (_timespec "2024-08-28T18:19:12")
+ (_timespec "2024-08-28T18:35:41")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
- (_timespec "2024-08-28T18:19:12")
+ (_timespec "2024-08-28T18:35:41")
)
(_file "compile/cmr.db"
(_format text)
- (_timespec "2024-08-28T18:19:13")
+ (_timespec "2024-08-28T18:35:41")
)
)
)
@@ -343,25 +343,25 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
- (_timespec "2024-08-28T18:19:20")
+ (_timespec "2024-08-28T18:35:49")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
- (_timespec "2024-08-28T18:19:20")
+ (_timespec "2024-08-28T18:35:49")
)
(_file "synthesize/Top_controlsets.txt"
(_format text)
- (_timespec "2024-08-28T18:19:20")
+ (_timespec "2024-08-28T18:35:48")
)
(_file "synthesize/snr.db"
(_format text)
- (_timespec "2024-08-28T18:19:21")
+ (_timespec "2024-08-28T18:35:49")
)
(_file "synthesize/Top.snr"
(_format text)
- (_timespec "2024-08-28T18:19:21")
+ (_timespec "2024-08-28T18:35:49")
)
)
)
@@ -378,34 +378,14 @@
)
(_task tsk_devmap
(_command cmd_devmap
- (_gci_state (_integer 2))
- (_db_output
- (_file "device_map/Top_map.adf"
- (_format adif)
- (_timespec "2024-08-28T18:19:29")
- )
- )
- (_output
- (_file "device_map/Top_dmr.prt"
- (_format text)
- (_timespec "2024-08-28T18:19:28")
- )
- (_file "device_map/Top.dmr"
- (_format text)
- (_timespec "2024-08-28T18:19:29")
- )
- (_file "device_map/dmr.db"
- (_format text)
- (_timespec "2024-08-28T18:19:29")
- )
- )
+ (_gci_state (_integer 0))
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/xsync.pcf"
(_format pcf)
- (_timespec "2024-08-28T18:19:29")
+ (_timespec "2024-08-28T18:33:27")
)
)
)
@@ -415,7 +395,7 @@
)
(_task tsk_pnr
(_command cmd_pnr
- (_gci_state (_integer 2))
+ (_gci_state (_integer 0))
(_option gplace_seed (_integer 8))
(_option seed_step (_integer 4))
(_option saved_outcome (_integer 4))
@@ -423,38 +403,6 @@
(_option share_router_control_signal (_boolean FALSE))
(_option check_clk_net_route_by_srb (_boolean FALSE))
(_option fix_hold_violation_in_route (_boolean FALSE))
- (_db_output
- (_file "place_route/Top_pnr.adf"
- (_format adif)
- (_timespec "2024-08-28T18:20:40")
- )
- )
- (_output
- (_file "place_route/clock_utilization.txt"
- (_format text)
- (_timespec "2024-08-28T18:20:36")
- )
- (_file "place_route/Top_plc.adf"
- (_format adif)
- (_timespec "2024-08-28T18:20:11")
- )
- (_file "place_route/Top.prr"
- (_format text)
- (_timespec "2024-08-28T18:20:40")
- )
- (_file "place_route/Top_prr.prt"
- (_format text)
- (_timespec "2024-08-28T18:20:36")
- )
- (_file "place_route/Top_pnr.netlist"
- (_format text)
- (_timespec "2024-08-28T18:20:40")
- )
- (_file "place_route/prr.db"
- (_format text)
- (_timespec "2024-08-28T18:20:40")
- )
- )
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@@ -483,26 +431,8 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
- (_gci_state (_integer 2))
+ (_gci_state (_integer 0))
(_option unused_io_status (_string "KEEPER"))
- (_output
- (_file "generate_bitstream/Top.sbit"
- (_format text)
- (_timespec "2024-08-28T18:21:06")
- )
- (_file "generate_bitstream/Top.smsk"
- (_format text)
- (_timespec "2024-08-28T18:21:06")
- )
- (_file "generate_bitstream/bgr.db"
- (_format text)
- (_timespec "2024-08-28T18:21:09")
- )
- (_file "generate_bitstream/Top.bgr"
- (_format text)
- (_timespec "2024-08-28T18:21:09")
- )
- )
)
)
)