From a5cb5390ef7e86ac2c3a09d4daf09eb37dca4309 Mon Sep 17 00:00:00 2001 From: zhaohe Date: Sat, 2 Mar 2024 22:25:19 +0800 Subject: [PATCH] update --- led_test.pds | 60 +++++------ source/src/input/ttl_input.v | 16 ++- source/src/output/ttl_output.v | 148 ++++++++++------------------ source/src/zutils/zsimple_pll.v | 115 +++++++++------------ source/src/zutils/zutils_freq_detector_v2.v | 105 ++++++++++++++++++++ 5 files changed, 250 insertions(+), 194 deletions(-) create mode 100644 source/src/zutils/zutils_freq_detector_v2.v diff --git a/led_test.pds b/led_test.pds index 0f16148..687cd1c 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sat Mar 2 18:19:24 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sat Mar 2 22:23:23 2024") (_version "1.0.5") (_status "initial") (_project @@ -59,7 +59,7 @@ ) (_file "source/src/output/ttl_output.v" (_format verilog) - (_timespec "2024-03-02T18:19:22") + (_timespec "2024-03-02T22:23:06") ) (_file "source/src/zutils/zutils_pwm_generator.v" (_format verilog) @@ -147,7 +147,7 @@ ) (_file "source/src/input/ttl_input.v" (_format verilog) - (_timespec "2024-03-02T17:48:39") + (_timespec "2024-03-02T22:21:29") ) (_file "source/src/zutils/ztuils_sig_devide.v" (_format verilog) @@ -167,7 +167,11 @@ ) (_file "source/src/zutils/zsimple_pll.v" (_format verilog) - (_timespec "2024-03-02T16:28:23") + (_timespec "2024-03-02T22:20:29") + ) + (_file "source/src/zutils/zutils_freq_detector_v2.v" + (_format verilog) + (_timespec "2024-03-02T22:20:27") ) ) ) @@ -239,17 +243,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-03-02T18:16:20") + (_timespec "2024-03-02T22:22:37") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-03-02T18:16:19") + (_timespec "2024-03-02T22:22:36") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-03-02T18:16:20") + (_timespec "2024-03-02T22:22:37") ) ) ) @@ -265,21 +269,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-03-02T18:16:47") + (_timespec "2024-03-02T22:22:46") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-03-02T18:16:49") + (_timespec "2024-03-02T22:22:46") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-03-02T18:16:51") + (_timespec "2024-03-02T22:22:47") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-03-02T18:16:52") + (_timespec "2024-03-02T22:22:47") ) ) ) @@ -300,21 +304,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-03-02T18:16:55") + (_timespec "2024-03-02T22:22:50") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-03-02T18:16:54") + (_timespec "2024-03-02T22:22:49") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-03-02T18:16:55") + (_timespec "2024-03-02T22:22:50") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-03-02T18:16:55") + (_timespec "2024-03-02T22:22:50") ) ) ) @@ -323,7 +327,7 @@ (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-03-02T18:16:55") + (_timespec "2024-03-02T22:22:50") ) ) ) @@ -338,33 +342,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-03-02T18:17:42") + (_timespec "2024-03-02T22:23:05") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-03-02T18:17:42") + (_timespec "2024-03-02T22:23:05") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-03-02T18:17:41") + (_timespec "2024-03-02T22:23:05") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-03-02T18:17:41") + (_timespec "2024-03-02T22:23:05") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-03-02T18:17:09") + (_timespec "2024-03-02T22:22:56") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-03-02T18:17:42") + (_timespec "2024-03-02T22:23:05") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-03-02T18:17:43") + (_timespec "2024-03-02T22:23:05") ) ) ) @@ -395,23 +399,23 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-03-02T18:18:14") + (_timespec "2024-03-02T22:23:21") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-03-02T18:18:14") + (_timespec "2024-03-02T22:23:21") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-03-02T18:18:14") + (_timespec "2024-03-02T22:23:21") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-03-02T18:18:16") + (_timespec "2024-03-02T22:23:23") ) ) ) diff --git a/source/src/input/ttl_input.v b/source/src/input/ttl_input.v index 87e0b17..e18151d 100644 --- a/source/src/input/ttl_input.v +++ b/source/src/input/ttl_input.v @@ -44,6 +44,7 @@ module ttl_input #( reg [31:0] r6_ttlin2_filter_factor; // !滤波 reg [31:0] r7_ttlin3_filter_factor; // !滤波 reg [31:0] r8_ttlin4_filter_factor; // !滤波 + reg [31:0] r9_freq_detect_bias; // !频率探测偏差 wire ttlin1_af_en; // !使能信号过滤后的信号1 @@ -88,6 +89,7 @@ module ttl_input #( r6_ttlin2_filter_factor <= 32'd02; r7_ttlin3_filter_factor <= 32'd02; r8_ttlin4_filter_factor <= 32'd02; + r9_freq_detect_bias <= 32'd10; end else begin if (reg_wr_sig) begin @@ -102,6 +104,8 @@ module ttl_input #( r7_ttlin3_filter_factor <= wr_data; 8: r8_ttlin4_filter_factor <= wr_data; + 9: + r9_freq_detect_bias <= wr_data; default: begin end endcase @@ -146,32 +150,36 @@ module ttl_input #( - zutils_freq_detector + zutils_freq_detector_v2 freq_detector1 ( .clk(clk), .rst_n(rst_n), + .freq_detect_bias(r9_freq_detect_bias), .pluse_input(ttlin1_sig_af_filter), .pluse_width_cnt(r1_ttlin1_freq_detector) ); - zutils_freq_detector + zutils_freq_detector_v2 freq_detector2 ( .clk(clk), .rst_n(rst_n), + .freq_detect_bias(r9_freq_detect_bias), .pluse_input(ttlin2_sig_af_filter), .pluse_width_cnt(r2_ttlin2_freq_detector) ); - zutils_freq_detector + zutils_freq_detector_v2 freq_detector3 ( .clk(clk), .rst_n(rst_n), + .freq_detect_bias(r9_freq_detect_bias), .pluse_input(ttlin3_sig_af_filter), .pluse_width_cnt(r3_ttlin3_freq_detector) ); - zutils_freq_detector + zutils_freq_detector_v2 freq_detector4 ( .clk(clk), .rst_n(rst_n), + .freq_detect_bias(r9_freq_detect_bias), .pluse_input(ttlin4_sig_af_filter), .pluse_width_cnt(r4_ttlin4_freq_detector) ); diff --git a/source/src/output/ttl_output.v b/source/src/output/ttl_output.v index 7046115..af88491 100644 --- a/source/src/output/ttl_output.v +++ b/source/src/output/ttl_output.v @@ -1,7 +1,6 @@ module ttl_output #( parameter REG_START_ADD = 0, parameter SYS_CLOCK_FREQ = 10000000, - // parameter TEST = 0, parameter ID = 1 ) ( input clk, //clock input @@ -39,21 +38,34 @@ module ttl_output #( reg [31:0] reg_input_polarity_ctrl; //!TTLOUT_触发信号边沿类型 reg [31:0] reg_input_trigger_edge_select; + //!输出脉冲宽度 + reg [31:0] output_pluse_width; + // !频率探测偏差 + reg [31:0] freq_detect_bias; + //!输出脉冲延迟 + reg [31:0] output_pluse_delay; //!输入信号频率探测 read only reg [31:0] reg_sig_in_freq_detect; //!输出信号频率探测 read only reg [31:0] reg_sig_out_freq_detect; - //!寄存器写入时相对地址 - wire [31:0] reg_wr_index; - - wire signal_in_choose; //!原始信号 - wire signal_in_multiplication;//!倍频后的信号 + wire [31:0] reg_wr_index;//!寄存器写入时相对地址 + reg signal_in_choose; //!原始信号 + wire signal_in_pll;//!倍频后的信号 wire signal_in_polarity_ctrl;//!极性翻转后的信号 + //信号流转图 + // + // signal_in[] + // ---> signal_in_choose + // ---> + // + // + + //!TTLOUT_寄存器自动赋值选择器 zutils_register_advanced #( .REG_START_ADD(REG_START_ADD) @@ -69,9 +81,12 @@ module ttl_output #( .reg2(reg_input_freq_division), .reg3(reg_input_freq_multiplication), .reg4(reg_input_polarity_ctrl), - .reg5(reg_sig_in_freq_detect), - .reg6(reg_sig_out_freq_detect), - .reg7(reg_input_trigger_edge_select), + .reg5(reg_input_trigger_edge_select), + .reg6(output_pluse_width), + .reg7(output_pluse_delay), + .reg8(freq_detect_bias), + .regE(reg_sig_in_freq_detect), + .regF(reg_sig_out_freq_detect), .reg_wr_sig(reg_wr_sig), .reg_index(reg_wr_index) ); @@ -84,9 +99,10 @@ module ttl_output #( reg_input_freq_division<=0; reg_input_freq_multiplication<=0; reg_input_polarity_ctrl<=0; - reg_input_trigger_edge_select<=1; - // reg_sig_in_freq_detect<=0; - // reg_sig_out_freq_detect<=0; + reg_input_trigger_edge_select<=1; //上升沿触发 + output_pluse_width<= 1000; // 100us + output_pluse_delay<=0; + freq_detect_bias<= 32'd10; end else begin if (reg_wr_sig) begin @@ -101,10 +117,14 @@ module ttl_output #( reg_input_freq_multiplication <= wr_data; 4: reg_input_polarity_ctrl <= wr_data; - // 5: - // reg_sig_in_freq_detect <= wr_data; - // 6: - // reg_sig_out_freq_detect <= wr_data; + 5: + reg_input_trigger_edge_select <= wr_data; + 6: + output_pluse_width <= wr_data; + 7: + output_pluse_delay <= wr_data; + 8: + freq_detect_bias <= wr_data; default: begin end endcase @@ -112,96 +132,32 @@ module ttl_output #( end end - assign signal_in_choose = signal_in[2]; + //!信号选择器 + always @(*) begin + if(reg_input_signal_select <= 31) begin + signal_in_choose <= signal_in[reg_input_signal_select]; + end + else begin + signal_in_choose <= 0; + end + end + zsimple_pll _simple_pll ( .clk(clk), .rst_n(rst_n), - .insignal(signal_in_choose), + .insignal(signal_in[2]), .trigger_eage_type(reg_input_trigger_edge_select[0]), - .freq_division(32'd2), - .freq_multiplication(32'd3), + .freq_detect_bias(freq_detect_bias), + .freq_division(reg_input_freq_division), + .freq_multiplication(3), .cfg_change(reg_wr_sig), - .outsignal(signal_in_multiplication) + .outsignal(signal_in_pll) ); assign ttloutput_state_led = 1; - assign ttloutput = signal_in_multiplication; - + assign ttloutput = signal_in_pll; - /******************************************************************************* - * 内部信号 * - *******************************************************************************/ - // //脉冲输出 - // wire pluse_output; - // // 输入信号上升沿事件 - // wire in_signal_rising_edge; - // // 输入信号下降沿事件 - // wire in_signal_falling_edge; - // // 输入信号上升沿或下降沿事件 - // wire in_signal_edge; - // // 输出的脉冲触发信号的触发信号 - // wire signal_src_trigger; - - // assign signal_src_trigger = (pluse_input_trigger_signal==0) ? (in_signal_rising_edge) : (in_signal_falling_edge); - - // wire signal_in_choose; - // zutils_multiplexer_32t1 _signal_select ( - // .chooseindex(reg_input_signal_select), - // .signal(signal_in), - // .signalout(signal_in_choose) - // ); - - - // // 边沿检测 - // zutils_edge_detecter _signal_in ( - // .clk(clk), - // .rst_n(rst_n), - // .in_signal(signal_in_choose), - // .in_signal_rising_edge(in_signal_rising_edge), - // .in_signal_falling_edge(in_signal_falling_edge), - // .in_signal_edge(in_signal_edge) - // ); - - // // 短脉冲，触发生成，长脉冲 - // zutils_pluse_generator _pluse_generator ( - // .clk(clk), - // .rst_n(rst_n), - // .pluse_width(reg_pulse_mode_valid_len), - // .pluse_delay(reg_pulse_mode_trigger_delay), - // .trigger(signal_src_trigger), - // .output_signal(ttl_after_process_output) - // ); - - // zutils_pwm_generator #( - // .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - // .OUTPUT_FREQ(1000 * ID) - // ) _test_signal_generator ( - // .clk(clk), - // .rst_n(rst_n), - // .output_signal(test_signal_output) - // ); - - - - // wire [15:0] signal_output_select_in; - // assign signal_output_select_in[0] = 1'b0; - // assign signal_output_select_in[1] = 1'b1; - // assign signal_output_select_in[2] = test_signal_output; - // assign signal_output_select_in[3] = signal_in_choose; - // assign signal_output_select_in[4] = !signal_in_choose; - // assign signal_output_select_in[5] = ttl_after_process_output; - // assign signal_output_select_in[6] = !ttl_after_process_output; - // assign signal_output_select_in[7] = 1'b0; - // assign signal_output_select_in[15:8] = 8'b0; - - // zutils_multiplexer_16t1 _signal_output_select ( - // .chooseindex(reg_output_signal_select), - // .signal(signal_output_select_in), - - // .signalout(ttloutput) - // ); - // // assign ttloutput_state_led = !ttloutput; endmodule diff --git a/source/src/zutils/zsimple_pll.v b/source/src/zutils/zsimple_pll.v index 27ca809..76fd5d5 100644 --- a/source/src/zutils/zsimple_pll.v +++ b/source/src/zutils/zsimple_pll.v @@ -4,6 +4,7 @@ module zsimple_pll ( input insignal, //!输入信号 input trigger_eage_type, + input wire [31:0] freq_detect_bias, //! 频率偏差计数 input wire [31:0] freq_division, input wire [31:0] freq_multiplication, input wire cfg_change, @@ -29,6 +30,7 @@ module zsimple_pll ( reg insignal_division; //! 输入信号分频后的信号 reg insignal_multiplication;//! 输入信号倍频后的信号 + reg insignal_pluse_width_modulation;//! 输入信号脉宽调制后的信号 zutils_edge_detecter edge_detecter ( @@ -66,92 +68,72 @@ module zsimple_pll ( end end - // 倍频 - // - // 触发计数 - // 更新计数 - // - // - // 计数器 - reg [31:0] freq_cnt_cache; - reg [31:0] freq_cnt; - always @(posedge clk or posedge module_reset) begin - if (module_reset) begin - freq_cnt <= 0; - freq_cnt_cache <= 32'hffff_ffff; - end - else begin - if (insignal_division) begin - if(freq_cnt == 0) begin - freq_cnt_cache <= 32'hffff_ffff; - end - else begin - freq_cnt_cache <= freq_cnt; - end - freq_cnt <= 0; - end - else begin - freq_cnt <= freq_cnt + 1; - if(freq_cnt >= 32'hffff_ffff) begin - freq_cnt_cache <= 32'hffff_ffff; - freq_cnt <= 0; - end - end - end - end + wire [31:0] insignal_multiplication_freq_cnt; + wire pluse_width_cnt_lock; + zutils_freq_detector_v2 + freq_detector ( + .clk(clk), + .rst_n(rst_n), + .freq_detect_bias(freq_detect_bias), + .pluse_input(insignal_division), + .pluse_width_cnt(insignal_multiplication_freq_cnt), + .pluse_width_cnt_lock(pluse_width_cnt_lock) + ); + - reg [31:0] multiplication_state; reg [31:0] multiplication_cnt; - reg [31:0] append_pluse_cnt; + reg [31:0] multiplication_state; + reg [31:0] gen_pluse_cnt; always @(posedge clk or posedge module_reset) begin - if (module_reset) begin + if (module_reset || !pluse_width_cnt_lock) begin multiplication_cnt <= 0; - insignal_multiplication <= 0; - append_pluse_cnt <= 0; multiplication_state <= 0; + gen_pluse_cnt <= 0; + insignal_multiplication <= 0; end else begin case (multiplication_state) - 0 : begin // !默认状态 - if(insignal_division) begin + 0 : begin + gen_pluse_cnt <= 0; + multiplication_cnt <= 0; + insignal_multiplication <= 0; - //触发一次脉冲 - insignal_multiplication <= 1; - - if(freq_multiplication >= 1 && freq_cnt_cache != 32'hffff_ffff) begin - // 进入额外脉冲状态 - multiplication_state <= 1; - append_pluse_cnt <= 0; - multiplication_cnt <= 0; - end - end - else begin - insignal_multiplication <= 0; + if(pluse_width_cnt_lock) begin + multiplication_state <= 1; end end 1 : begin - - if(append_pluse_cnt < freq_multiplication && freq_cnt_cache != 32'hffff_ffff && freq_multiplication > 0) begin - - if(multiplication_cnt < freq_cnt_cache) begin - multiplication_cnt <= multiplication_cnt + freq_multiplication + 1; + if(insignal_division) begin + multiplication_state <= 2; + gen_pluse_cnt <= 0; + multiplication_cnt <= 0; + end + end + 2: begin + if(multiplication_cnt < insignal_multiplication_freq_cnt>>1) begin + multiplication_cnt <= multiplication_cnt + freq_multiplication + 1; + insignal_multiplication <= 1; + end + else if(multiplication_cnt >= insignal_multiplication_freq_cnt) begin + gen_pluse_cnt <= gen_pluse_cnt + 1; + insignal_multiplication <= 1; + multiplication_cnt <= 0; + gen_pluse_cnt <= gen_pluse_cnt + 1; + end + else begin + if(gen_pluse_cnt >= freq_multiplication ) begin + multiplication_state <= 1; insignal_multiplication <= 0; + multiplication_cnt <= 0; end else begin - insignal_multiplication <= 1; - multiplication_cnt <= 0; - append_pluse_cnt <= append_pluse_cnt + 1; + multiplication_cnt <= multiplication_cnt + freq_multiplication + 1; + insignal_multiplication <= 0; end - - end - else begin - multiplication_state <= 0; - insignal_multiplication <= 0; end - end default: begin multiplication_state <= 0; @@ -160,5 +142,6 @@ module zsimple_pll ( end end + assign outsignal = insignal_multiplication; endmodule diff --git a/source/src/zutils/zutils_freq_detector_v2.v b/source/src/zutils/zutils_freq_detector_v2.v new file mode 100644 index 0000000..c830ef7 --- /dev/null +++ b/source/src/zutils/zutils_freq_detector_v2.v @@ -0,0 +1,105 @@ +// +// @功能: +// 1. 滤波(add later) +// 2. 频率探测 +// 3. 输出灯光控制 +// +module zutils_freq_detector_v2 + ( + input clk, //! 时钟输入 + input rst_n, //! 复位输入 + input pluse_input, //! 输入信号1 + input wire [31:0] freq_detect_bias, //! 频率偏差计数 + output reg [31:0]pluse_width_cnt, //! 输出捕获到的脉冲宽度 + output wire pluse_width_cnt_lock //! 输出捕获到的脉冲宽度锁定信号 + ); + + + reg in_signal_last; + reg in_signal_rising_edge; //! 上升沿 + reg [31:0] state; //! 频率捕获状态 + reg [31:0] freq_detect; //! 探测到频率cache1 + reg [31:0] freq_detect_cnt;//! 实时频率探测计数 + + + //!in_signal_last 捕获 + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + in_signal_last <= 0; + end + else begin + in_signal_last <= pluse_input; + end + end + + //!边沿捕获 + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + in_signal_rising_edge <= 0; + end + else begin + if (in_signal_last == 0 && pluse_input == 1) begin + in_signal_rising_edge <= 1; + end + else if (in_signal_last == 1 && pluse_input == 0) begin + in_signal_rising_edge <= 0; + end + else begin + in_signal_rising_edge <= 0; + end + end + end + + + + assign freq_detect_stable = (freq_detect <= freq_detect_cnt + freq_detect_bias + 1 && freq_detect >= freq_detect_cnt - freq_detect_bias - 1); + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + state <= 0; + freq_detect <=0; + pluse_width_cnt <= 32'hffff_ffff; + end + else begin + case (state) + 0: begin + // 频率探测中 + if(in_signal_rising_edge) begin + freq_detect <= freq_detect_cnt; + freq_detect_cnt <= 0; + if(freq_detect_stable) begin + state <= 1; + pluse_width_cnt <= freq_detect; + end + else begin + pluse_width_cnt <= 32'hffff_ffff; + end + end + else begin + freq_detect_cnt <= freq_detect_cnt + 1; + end + end + 1: begin + // 判断频率是否发生变化，如果频率发生变化，则重新探测 + if(in_signal_rising_edge || freq_detect_cnt> freq_detect+ 1) begin + freq_detect_cnt <= 0; + if(!freq_detect_stable) begin + state <= 0; + pluse_width_cnt <= 32'hffff_ffff; + end + end + else begin + freq_detect_cnt <= freq_detect_cnt + 1; + end + + end + default: begin + state <= 0; + end + endcase + end + end + + assign pluse_width_cnt_lock = (state == 1); + +endmodule