forked from p_lusterinc_xsync/xsync_fpge
5 changed files with 250 additions and 194 deletions
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60led_test.pds
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16source/src/input/ttl_input.v
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148source/src/output/ttl_output.v
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115source/src/zutils/zsimple_pll.v
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105source/src/zutils/zutils_freq_detector_v2.v
@ -0,0 +1,105 @@ |
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// |
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// @功能: |
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// 1. 滤波(add later) |
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// 2. 频率探测 |
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// 3. 输出灯光控制 |
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// |
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module zutils_freq_detector_v2 |
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( |
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input clk, //! 时钟输入 |
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input rst_n, //! 复位输入 |
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input pluse_input, //! 输入信号1 |
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input wire [31:0] freq_detect_bias, //! 频率偏差计数 |
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output reg [31:0]pluse_width_cnt, //! 输出捕获到的脉冲宽度 |
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output wire pluse_width_cnt_lock //! 输出捕获到的脉冲宽度锁定信号 |
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); |
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reg in_signal_last; |
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reg in_signal_rising_edge; //! 上升沿 |
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reg [31:0] state; //! 频率捕获状态 |
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reg [31:0] freq_detect; //! 探测到频率cache1 |
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reg [31:0] freq_detect_cnt;//! 实时频率探测计数 |
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//!in_signal_last 捕获 |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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in_signal_last <= 0; |
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end |
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else begin |
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in_signal_last <= pluse_input; |
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end |
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end |
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//!边沿捕获 |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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in_signal_rising_edge <= 0; |
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end |
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else begin |
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if (in_signal_last == 0 && pluse_input == 1) begin |
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in_signal_rising_edge <= 1; |
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end |
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else if (in_signal_last == 1 && pluse_input == 0) begin |
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in_signal_rising_edge <= 0; |
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end |
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else begin |
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in_signal_rising_edge <= 0; |
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end |
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end |
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end |
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assign freq_detect_stable = (freq_detect <= freq_detect_cnt + freq_detect_bias + 1 && freq_detect >= freq_detect_cnt - freq_detect_bias - 1); |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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state <= 0; |
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freq_detect <=0; |
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pluse_width_cnt <= 32'hffff_ffff; |
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end |
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else begin |
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case (state) |
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0: begin |
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// 频率探测中 |
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if(in_signal_rising_edge) begin |
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freq_detect <= freq_detect_cnt; |
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freq_detect_cnt <= 0; |
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if(freq_detect_stable) begin |
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state <= 1; |
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pluse_width_cnt <= freq_detect; |
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end |
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else begin |
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pluse_width_cnt <= 32'hffff_ffff; |
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end |
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end |
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else begin |
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freq_detect_cnt <= freq_detect_cnt + 1; |
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end |
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end |
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1: begin |
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// 判断频率是否发生变化，如果频率发生变化，则重新探测 |
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if(in_signal_rising_edge || freq_detect_cnt> freq_detect+ 1) begin |
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freq_detect_cnt <= 0; |
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if(!freq_detect_stable) begin |
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state <= 0; |
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pluse_width_cnt <= 32'hffff_ffff; |
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end |
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end |
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else begin |
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freq_detect_cnt <= freq_detect_cnt + 1; |
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end |
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end |
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default: begin |
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state <= 0; |
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end |
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endcase |
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end |
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end |
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assign pluse_width_cnt_lock = (state == 1); |
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endmodule |
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