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xsync_fpge_v2
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内部信号源支持使能控制模块

master
zhaohe 1 year ago
parent
030eb27861
commit
ac0195313c
8 changed files with 153 additions and 130 deletions
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  1. 110
      led_test.pds
  2. 1
      source/src/config.v
  3. 6
      source/src/internal/internal_clock_generator.v
  4. 3
      source/src/internal/internal_genlock_generator.v
  5. 57
      source/src/internal/internal_sig_generator_en_contrler.v
  6. 4
      source/src/internal/internal_timecode_generator.v
  7. 40
      source/src/spi_reg_bus.v
  8. 62
      source/src/top.v

110
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Mar 22 22:10:41 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sat Mar 23 17:15:21 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-03-22T22:10:39")
(_timespec "2024-03-23T17:11:42")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -175,11 +175,11 @@
)
(_file "source/src/spi_reg_bus.v"
(_format verilog)
(_timespec "2024-03-21T15:13:16")
(_timespec "2024-03-23T17:00:10")
)
(_file "source/src/internal/internal_timecode_generator.v"
(_format verilog)
(_timespec "2024-03-04T22:26:01")
(_timespec "2024-03-23T16:37:37")
)
(_file "source/src/sys/sys_timecode.v"
(_format verilog)
@ -191,11 +191,11 @@
)
(_file "source/src/internal/internal_clock_generator.v"
(_format verilog)
(_timespec "2024-03-05T18:04:44")
(_timespec "2024-03-23T16:38:57")
)
(_file "source/src/internal/internal_genlock_generator.v"
(_format verilog)
(_timespec "2024-03-05T12:36:20")
(_timespec "2024-03-23T16:38:08")
)
(_file "source/src/sys/sys_genlock.v"
(_format verilog)
@ -229,6 +229,10 @@
(_format verilog)
(_timespec "2024-03-22T22:01:26")
)
(_file "source/src/internal/internal_sig_generator_en_contrler.v"
(_format verilog)
(_timespec "2024-03-23T16:58:20")
)
)
)
(_widget wgt_my_ips_src
@ -307,21 +311,21 @@
)
(_task tsk_compile
(_command cmd_compile
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-03-22T22:04:52")
(_timespec "2024-03-23T17:12:28")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-03-22T22:04:51")
(_timespec "2024-03-23T17:12:25")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-03-22T22:04:52")
(_timespec "2024-03-23T17:12:28")
)
)
)
@ -331,27 +335,27 @@
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-03-22T22:04:57")
(_timespec "2024-03-23T17:14:59")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-03-22T22:04:57")
(_timespec "2024-03-23T17:15:11")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-03-22T22:04:58")
(_timespec "2024-03-23T17:15:20")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-03-22T22:04:58")
(_timespec "2024-03-23T17:15:21")
)
)
)
@ -368,27 +372,7 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 3))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-03-22T22:05:00")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-03-22T22:05:00")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-03-22T22:05:00")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-03-22T22:05:01")
)
)
(_gci_state (_integer 0))
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
@ -405,40 +389,8 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 3))
(_gci_state (_integer 0))
(_option mode (_string "fast"))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-03-22T22:05:08")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-03-22T22:05:08")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-03-22T22:05:08")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-03-22T22:05:08")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-03-22T22:05:05")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-03-22T22:05:08")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-03-22T22:05:09")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -467,25 +419,7 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 3))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-03-22T22:05:15")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-03-22T22:05:15")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-03-22T22:05:15")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-03-22T22:05:15")
)
)
(_gci_state (_integer 0))
)
)
)

1
source/src/config.v
View File

@ -5,6 +5,7 @@
`define REGADDOFF__INTERNAL_TIMECODE 16'h0300
`define REGADDOFF__INTERNAL_GENLOCK 16'h0310
`define REGADDOFF__INTERNAL_CLOCK 16'h0320
`define REGADDOFF__INTERNAL_SIG_EN_CONTRLER 16'h03A0
`define REGADDOFF__TTLOUT1 16'h0200
`define REGADDOFF__TTLOUT2 16'h0210
`define REGADDOFF__TTLOUT3 16'h0220

6
source/src/internal/internal_clock_generator.v
View File

@ -12,6 +12,8 @@ module internal_clock_generator #(
input wr_en, //! 写使能
output wire [31:0] rd_data, //! 读出数据
input en,
output clk_output //! 输出频率
);
@ -72,14 +74,14 @@ module internal_clock_generator #(
cnt <= 0;
clk_sig <= 0;
if (r2_en[0]) begin
if (r2_en[0] & en) begin
state <= 1;
clk_sig <= 1;
end
end
1: begin
if (!r2_en[0]) begin
if (!(r2_en[0] & en)) begin
state <= 0;
end else begin
if (cnt < (r3_setting_cnt >> 1)) begin

3
source/src/internal/internal_genlock_generator.v
View File

@ -12,6 +12,7 @@ module internal_genlock_generator #(
input wr_en, //! 写使能
output wire [31:0] rd_data, //! 读出数据
input en,
output genlock_freq_signal //! genlock freq signal
);
@ -73,7 +74,7 @@ module internal_genlock_generator #(
) genlock (
.clk (clk),
.rst_n (rst_n),
.ctrl_sig (r2_en[0]),
.ctrl_sig (r2_en[0] & en),
.genlock_fps2397_clk(genlock_fps2397_clk),
.genlock_fps2398_clk(genlock_fps2398_clk),
.genlock_fps2400_clk(genlock_fps2400_clk),

57
source/src/internal/internal_sig_generator_en_contrler.v
View File

@ -0,0 +1,57 @@
`include "../config.v"
module internal_sig_generator_en_contrler #(
parameter REG_START_ADD = 0,
parameter SYS_CLOCK_FREQ = 10000000
) (
input clk, //! 时钟输入
input rst_n, //! 复位输入
input [31:0] addr, //! 寄存器地址
input [31:0] wr_data, //! 写入数据
input wr_en, //! 写使能
output wire [31:0] rd_data, //! 读出数据
output en0,
output en1,
output en2
);
reg [31:0] r1_en; //!使能控制
wire [31:0] reg_wr_index;
zutils_register_advanced #(
.REG_START_ADD(REG_START_ADD)
) _register (
.clk (clk),
.rst_n (rst_n),
.addr (addr),
.wr_data (wr_data),
.wr_en (wr_en),
.rd_data (rd_data),
.reg1 (r1_en),
.reg_wr_sig(reg_wr_sig),
.reg_index (reg_wr_index)
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
r1_en <= 0;
end else begin
if (reg_wr_sig) begin
case (reg_wr_index)
1: r1_en <= wr_data;
default: begin
end
endcase
end
end
end
assign en0 = r1_en[0];
assign en1 = r1_en[1];
assign en2 = r1_en[2];
endmodule

4
source/src/internal/internal_timecode_generator.v
View File

@ -12,6 +12,8 @@ module internal_timecode_generator #(
input wr_en,
output wire [31:0] rd_data,
input en,
output timecode_tigger_sig,
output [31:0] timecode_format,
output [63:0] timecode_data,
@ -81,7 +83,7 @@ module internal_timecode_generator #(
.timecode1 (wr_data),
.timecode1_export(reg4_timecode_data1),
.en(reg1_timecode_en[0]),
.en(reg1_timecode_en[0] & en),
.out_timecode_serial_data(timecode_serial_data),
.out_trigger_sig (timecode_tigger_sig),

40
source/src/spi_reg_bus.v
View File

@ -20,6 +20,7 @@ module spi_reg_bus (
input [31:0] rd_data_module_internal_timecode,
input [31:0] rd_data_module_internal_genlock,
input [31:0] rd_data_module_internal_clock,
input [31:0] rd_data_module_internal_sig_en_contrler,
input [31:0] rd_data_module_ttlout1,
input [31:0] rd_data_module_ttlout2,
input [31:0] rd_data_module_ttlout3,
@ -54,25 +55,26 @@ module spi_reg_bus (
assign addr_group = addr & 31'hFFFF_FFF0;
always @(*) begin
case (addr_group)
`REGADDOFF__FPGA_INFO: rd_data <= rd_data_module_fpga_info;
`REGADDOFF__TTLIN: rd_data <= rd_data_module_ttlin;
`REGADDOFF__TIMECODE_IN: rd_data <= rd_data_module_timecode_in;
`REGADDOFF__GENLOCK_IN: rd_data <= rd_data_module_genlock_in;
`REGADDOFF__INTERNAL_TIMECODE: rd_data <= rd_data_module_internal_timecode;
`REGADDOFF__INTERNAL_GENLOCK: rd_data <= rd_data_module_internal_genlock;
`REGADDOFF__INTERNAL_CLOCK: rd_data <= rd_data_module_internal_clock;
`REGADDOFF__TTLOUT1: rd_data <= rd_data_module_ttlout1;
`REGADDOFF__TTLOUT2: rd_data <= rd_data_module_ttlout2;
`REGADDOFF__TTLOUT3: rd_data <= rd_data_module_ttlout3;
`REGADDOFF__TTLOUT4: rd_data <= rd_data_module_ttlout4;
`REGADDOFF__TIMECODE_OUT: rd_data <= rd_data_module_timecode_out;
`REGADDOFF__GENLOCK_OUT: rd_data <= rd_data_module_genlock_out;
`REGADDOFF__CAMERA_SYNC_OUT: rd_data <= rd_data_module_camera_sync_out;
`REGADDOFF__SYS_TIMECODE: rd_data <= rd_data_module_sys_timecode;
`REGADDOFF__SYS_GENLOCK: rd_data <= rd_data_module_sys_genlock;
`REGADDOFF__SYS_CLOCK: rd_data <= rd_data_module_sys_clock;
`REGADDOFF__RECORD_SIG_GENERATOR: rd_data <= rd_data_module_record_sig_generator;
`REGADDOFF__DELAYER: rd_data <= rd_data_module_sys_signal_delayer;
`REGADDOFF__FPGA_INFO: rd_data <= rd_data_module_fpga_info;
`REGADDOFF__TTLIN: rd_data <= rd_data_module_ttlin;
`REGADDOFF__TIMECODE_IN: rd_data <= rd_data_module_timecode_in;
`REGADDOFF__GENLOCK_IN: rd_data <= rd_data_module_genlock_in;
`REGADDOFF__INTERNAL_TIMECODE: rd_data <= rd_data_module_internal_timecode;
`REGADDOFF__INTERNAL_GENLOCK: rd_data <= rd_data_module_internal_genlock;
`REGADDOFF__INTERNAL_CLOCK: rd_data <= rd_data_module_internal_clock;
`REGADDOFF__INTERNAL_SIG_EN_CONTRLER: rd_data <= rd_data_module_internal_sig_en_contrler;
`REGADDOFF__TTLOUT1: rd_data <= rd_data_module_ttlout1;
`REGADDOFF__TTLOUT2: rd_data <= rd_data_module_ttlout2;
`REGADDOFF__TTLOUT3: rd_data <= rd_data_module_ttlout3;
`REGADDOFF__TTLOUT4: rd_data <= rd_data_module_ttlout4;
`REGADDOFF__TIMECODE_OUT: rd_data <= rd_data_module_timecode_out;
`REGADDOFF__GENLOCK_OUT: rd_data <= rd_data_module_genlock_out;
`REGADDOFF__CAMERA_SYNC_OUT: rd_data <= rd_data_module_camera_sync_out;
`REGADDOFF__SYS_TIMECODE: rd_data <= rd_data_module_sys_timecode;
`REGADDOFF__SYS_GENLOCK: rd_data <= rd_data_module_sys_genlock;
`REGADDOFF__SYS_CLOCK: rd_data <= rd_data_module_sys_clock;
`REGADDOFF__RECORD_SIG_GENERATOR: rd_data <= rd_data_module_record_sig_generator;
`REGADDOFF__DELAYER: rd_data <= rd_data_module_sys_signal_delayer;
default: rd_data <= 0;
endcase

62
source/src/top.v
View File

@ -97,6 +97,7 @@ module Top (
wire [31:0] rd_data_module_internal_timecode; //! 模块寄存器数据总线读数据
wire [31:0] rd_data_module_internal_genlock; //! 模块寄存器数据总线读数据
wire [31:0] rd_data_module_internal_clock; //! 模块寄存器数据总线读数据
wire [31:0] rd_data_module_internal_sig_en_contrler; //! 模块寄存器数据总线读数据
wire [31:0] rd_data_module_ttlout1; //! 模块寄存器数据总线读数据
wire [31:0] rd_data_module_ttlout2; //! 模块寄存器数据总线读数据
wire [31:0] rd_data_module_ttlout3; //! 模块寄存器数据总线读数据
@ -191,25 +192,26 @@ module Top (
.spi_rx_pin (spi2_rx_pin),
.spi_tx_pin (spi2_tx_pin),
.rd_data_module_fpga_info (rd_data_module_fpga_info),
.rd_data_module_ttlin (rd_data_module_ttlin),
.rd_data_module_timecode_in (rd_data_module_timecode_in),
.rd_data_module_genlock_in (rd_data_module_genlock_in),
.rd_data_module_internal_timecode (rd_data_module_internal_timecode),
.rd_data_module_internal_genlock (rd_data_module_internal_genlock),
.rd_data_module_internal_clock (rd_data_module_internal_clock),
.rd_data_module_ttlout1 (rd_data_module_ttlout1),
.rd_data_module_ttlout2 (rd_data_module_ttlout2),
.rd_data_module_ttlout3 (rd_data_module_ttlout3),
.rd_data_module_ttlout4 (rd_data_module_ttlout4),
.rd_data_module_timecode_out (rd_data_module_timecode_out),
.rd_data_module_genlock_out (rd_data_module_genlock_out),
.rd_data_module_camera_sync_out (rd_data_module_camera_sync_out),
.rd_data_module_sys_timecode (rd_data_module_sys_timecode),
.rd_data_module_sys_genlock (rd_data_module_sys_genlock),
.rd_data_module_sys_clock (rd_data_module_sys_clock),
.rd_data_module_record_sig_generator(rd_data_module_record_sig_generator),
.rd_data_module_sys_signal_delayer (rd_data_module_sys_signal_delayer)
.rd_data_module_fpga_info (rd_data_module_fpga_info),
.rd_data_module_ttlin (rd_data_module_ttlin),
.rd_data_module_timecode_in (rd_data_module_timecode_in),
.rd_data_module_genlock_in (rd_data_module_genlock_in),
.rd_data_module_internal_timecode (rd_data_module_internal_timecode),
.rd_data_module_internal_genlock (rd_data_module_internal_genlock),
.rd_data_module_internal_clock (rd_data_module_internal_clock),
.rd_data_module_internal_sig_en_contrler(rd_data_module_internal_sig_en_contrler),
.rd_data_module_ttlout1 (rd_data_module_ttlout1),
.rd_data_module_ttlout2 (rd_data_module_ttlout2),
.rd_data_module_ttlout3 (rd_data_module_ttlout3),
.rd_data_module_ttlout4 (rd_data_module_ttlout4),
.rd_data_module_timecode_out (rd_data_module_timecode_out),
.rd_data_module_genlock_out (rd_data_module_genlock_out),
.rd_data_module_camera_sync_out (rd_data_module_camera_sync_out),
.rd_data_module_sys_timecode (rd_data_module_sys_timecode),
.rd_data_module_sys_genlock (rd_data_module_sys_genlock),
.rd_data_module_sys_clock (rd_data_module_sys_clock),
.rd_data_module_record_sig_generator (rd_data_module_record_sig_generator),
.rd_data_module_sys_signal_delayer (rd_data_module_sys_signal_delayer)
);
@ -385,6 +387,22 @@ module Top (
* 内部信号源 *
*******************************************************************************/
internal_sig_generator_en_contrler #(
.REG_START_ADD(`REGADDOFF__INTERNAL_SIG_EN_CONTRLER),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) internal_sig_generator_en_contrler0 (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr (RegReaderBus_addr),
.wr_data(RegReaderBus_wr_data),
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_internal_sig_en_contrler),
.en0(en0),
.en1(en1),
.en2(en2)
);
internal_timecode_generator #(
.REG_START_ADD(`REGADDOFF__INTERNAL_TIMECODE),
@ -399,6 +417,8 @@ module Top (
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_internal_timecode),
.en(en0),
.timecode_tigger_sig (internal_timecode_tigger_sig),
.timecode_format (internal_timecode_format),
.timecode_data (internal_timecode_data),
@ -417,6 +437,8 @@ module Top (
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_internal_genlock),
.en(en1),
.genlock_freq_signal(signal_internal_genlock_freq)
);
@ -432,6 +454,8 @@ module Top (
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_internal_clock),
.en(en2),
.clk_output(signal_internal_clk_sig)
);

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