diff --git a/led_test.pds b/led_test.pds index 25f6347..856f2e9 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Mar 4 22:31:29 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Tue Mar 5 12:39:14 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-03-04T22:13:55") + (_timespec "2024-03-05T12:38:35") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -59,7 +59,7 @@ ) (_file "source/src/output/ttl_output.v" (_format verilog) - (_timespec "2024-03-04T18:49:05") + (_timespec "2024-03-05T10:18:24") ) (_file "source/src/zutils/zutils_pwm_generator.v" (_format verilog) @@ -143,7 +143,7 @@ ) (_file "source/src/input/ttl_input.v" (_format verilog) - (_timespec "2024-03-04T19:00:29") + (_timespec "2024-03-05T10:18:22") ) (_file "source/src/zutils/ztuils_sig_devide.v" (_format verilog) @@ -185,6 +185,26 @@ (_format verilog) (_timespec "2024-03-04T22:11:20") ) + (_file "source/src/input/genlock_input_module.v" + (_format verilog) + (_timespec "2024-03-05T12:23:00") + ) + (_file "source/src/internal/internal_clock_generator.v" + (_format verilog) + (_timespec "2024-03-05T12:36:42") + ) + (_file "source/src/internal/internal_genlock_generator.v" + (_format verilog) + (_timespec "2024-03-05T12:36:20") + ) + (_file "source/src/sys/sys_genlock.v" + (_format verilog) + (_timespec "2024-03-05T12:23:28") + ) + (_file "source/src/sys/sys_clock.v" + (_format verilog) + (_timespec "2024-03-05T12:37:42") + ) ) ) (_widget wgt_my_ips_src @@ -255,17 +275,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-03-04T22:26:17") + (_timespec "2024-03-05T12:38:46") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-03-04T22:26:15") + (_timespec "2024-03-05T12:38:43") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-03-04T22:26:17") + (_timespec "2024-03-05T12:38:46") ) ) ) @@ -281,21 +301,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-03-04T22:26:37") + (_timespec "2024-03-05T12:39:11") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-03-04T22:26:38") + (_timespec "2024-03-05T12:39:12") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-03-04T22:26:39") + (_timespec "2024-03-05T12:39:14") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-03-04T22:26:39") + (_timespec "2024-03-05T12:39:14") ) ) ) @@ -312,27 +332,7 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 2)) - (_db_output - (_file "device_map/Top_map.adf" - (_format adif) - (_timespec "2024-03-04T22:26:49") - ) - ) - (_output - (_file "device_map/Top_dmr.prt" - (_format text) - (_timespec "2024-03-04T22:26:42") - ) - (_file "device_map/Top.dmr" - (_format text) - (_timespec "2024-03-04T22:26:49") - ) - (_file "device_map/dmr.db" - (_format text) - (_timespec "2024-03-04T22:26:50") - ) - ) + (_gci_state (_integer 0)) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) @@ -349,40 +349,8 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 2)) + (_gci_state (_integer 0)) (_option mode (_string "fast")) - (_db_output - (_file "place_route/Top_pnr.adf" - (_format adif) - (_timespec "2024-03-04T22:30:13") - ) - ) - (_output - (_file "place_route/Top.prr" - (_format text) - (_timespec "2024-03-04T22:30:13") - ) - (_file "place_route/Top_prr.prt" - (_format text) - (_timespec "2024-03-04T22:30:12") - ) - (_file "place_route/clock_utilization.txt" - (_format text) - (_timespec "2024-03-04T22:30:12") - ) - (_file "place_route/Top_plc.adf" - (_format adif) - (_timespec "2024-03-04T22:27:40") - ) - (_file "place_route/Top_pnr.netlist" - (_format text) - (_timespec "2024-03-04T22:30:13") - ) - (_file "place_route/prr.db" - (_format text) - (_timespec "2024-03-04T22:30:15") - ) - ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -411,25 +379,7 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 2)) - (_output - (_file "generate_bitstream/Top.sbit" - (_format text) - (_timespec "2024-03-04T22:31:27") - ) - (_file "generate_bitstream/Top.smsk" - (_format text) - (_timespec "2024-03-04T22:31:27") - ) - (_file "generate_bitstream/Top.bgr" - (_format text) - (_timespec "2024-03-04T22:31:27") - ) - (_file "generate_bitstream/bgr.db" - (_format text) - (_timespec "2024-03-04T22:31:29") - ) - ) + (_gci_state (_integer 0)) ) ) ) diff --git a/source/src/config.v b/source/src/config.v index b7de6f6..53011b3 100644 --- a/source/src/config.v +++ b/source/src/config.v @@ -16,3 +16,6 @@ `define REGADDOFF__SYS_GENLOCK 16'h0410 `define REGADDOFF__SYS_CLOCK 16'h0420 `define REGADDOFF__RECORD_SIG_GENERATOR 16'h0500 + + +`define FREQ_DETECT_BIAS_DEFAULT 32'd10 \ No newline at end of file diff --git a/source/src/input/genlock_input_module.v b/source/src/input/genlock_input_module.v new file mode 100644 index 0000000..14551de --- /dev/null +++ b/source/src/input/genlock_input_module.v @@ -0,0 +1,69 @@ +`include "../config.v" +module genlock_input_module #( + parameter REG_START_ADD = 0, + parameter SYS_CLOCK_FREQ = 10000000 +) ( + + input clk, //! 时钟输入 + input rst_n, //! 复位输入 + + input [31:0] addr, //! 寄存器地址 + input [31:0] wr_data, //! 写入数据 + input wr_en, //! 写使能 + output wire [31:0] rd_data, //! 读出数据 + + input genlock_in_hsync, //! genlock hsync + input genlock_in_vsync, //! genlock vsync + input genlock_in_fsync, //! genlock fsync + + output genlock_freq_signal, //! genlock freq signal + output genlock_in_state_led + + +); + + reg [31:0] r1_genlock_freq_detect_bias; + reg [31:0] r2_genlock_freq; + + wire [31:0] reg_wr_index; + zutils_register_advanced #( + .REG_START_ADD(REG_START_ADD) + ) _register ( + .clk (clk), + .rst_n (rst_n), + .addr (addr), + .wr_data (wr_data), + .wr_en (wr_en), + .rd_data (rd_data), + .reg1 (r1_genlock_freq_detect_bias), + .reg2 (r2_genlock_freq), + .reg_wr_sig(reg_wr_sig), + .reg_index (reg_wr_index) + ); + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + r1_genlock_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; + end else begin + if (reg_wr_sig) begin + case (reg_wr_index) + 1: r1_genlock_freq_detect_bias <= wr_data; + default: begin + end + endcase + end + end + end + + zutils_freq_detector_v2 freq_detector1 ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(r1_genlock_freq_detect_bias), + .pluse_input (ttlin1_sig_af_filter), + .pluse_width_cnt (r2_genlock_freq) + ); + + assign genlock_freq_signal = genlock_in_hsync; + assign genlock_in_state_led = 1; + +endmodule diff --git a/source/src/input/ttl_input.v b/source/src/input/ttl_input.v index d16ef84..06b05c9 100644 --- a/source/src/input/ttl_input.v +++ b/source/src/input/ttl_input.v @@ -4,6 +4,7 @@ // 2. 频率探测 // 3. 输出灯光控制 // +`include "../config.v" module ttl_input #( parameter REG_START_ADD = 0, parameter SYS_CLOCK_FREQ = 10000000 @@ -88,7 +89,7 @@ module ttl_input #( r7_ttlin2_filter_factor <= 32'd02; r8_ttlin3_filter_factor <= 32'd02; r9_ttlin4_filter_factor <= 32'd02; - r10_freq_detect_bias <= 32'd10; + r10_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; end else begin if (reg_wr_sig) begin case (reg_wr_index) diff --git a/source/src/internal/internal_clock_generator.v b/source/src/internal/internal_clock_generator.v index e69de29..d69d207 100644 --- a/source/src/internal/internal_clock_generator.v +++ b/source/src/internal/internal_clock_generator.v @@ -0,0 +1,117 @@ +`include "../config.v" +module internal_clock_generator #( + parameter REG_START_ADD = 0, + parameter SYS_CLOCK_FREQ = 10000000 +) ( + + input clk, //! 时钟输入 + input rst_n, //! 复位输入 + + input [31:0] addr, //! 寄存器地址 + input [31:0] wr_data, //! 写入数据 + input wr_en, //! 写使能 + output wire [31:0] rd_data, //! 读出数据 + + output clk_output //! 输出频率 + +); + + reg [31:0] r1_contrl_mode; //! 控制模式,目前未使用 + reg [31:0] r2_en; //!使能控制 + reg [31:0] r3_setting_cnt; //!格式 + wire [31:0] r4_detect_freq; //!输出频率探测 + + wire [31:0] reg_wr_index; + zutils_register_advanced #( + .REG_START_ADD(REG_START_ADD) + ) _register ( + .clk (clk), + .rst_n (rst_n), + .addr (addr), + .wr_data (wr_data), + .wr_en (wr_en), + .rd_data (rd_data), + .reg1 (r1_contrl_mode), + .reg2 (r2_en), + .reg3 (r3_setting_cnt), + .reg4 (r4_detect_freq), + .reg_wr_sig(reg_wr_sig), + .reg_index (reg_wr_index) + ); + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + r1_contrl_mode <= 0; + r2_en <= 1; + r3_setting_cnt <= 0; + end else begin + if (reg_wr_sig) begin + case (reg_wr_index) + 1: r1_contrl_mode <= wr_data; + 2: r2_en <= wr_data; + 3: r3_setting_cnt <= wr_data; + default: begin + end + endcase + end + end + end + + + reg state; + reg [31:0] cnt; + reg clk_sig; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + state <= 0; + clk_sig <= 0; + cnt <= 0; + end else begin + case (state) + 0: begin + cnt <= 0; + clk_sig <= 0; + + if (r2_en[0]) begin + state <= 1; + clk_sig <= 1; + end + + end + 1: begin + if (!r2_en[0]) begin + state <= 0; + end else begin + if (cnt < (r3_setting_cnt >> 1)) begin + cnt <= cnt + 1; + clk_sig <= 1; + end else if (cnt >= (r3_setting_cnt >> 1) && cnt < r3_setting_cnt) begin + cnt <= cnt + 1; + clk_sig <= 0; + end else begin + cnt <= 0; + clk_sig <= 1; + end + end + end + endcase + end + end + + + + zutils_freq_detector_v2 freq_detector1 ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(1), + .pluse_input (clk_sig), + .pluse_width_cnt (r4_detect_freq) + ); + + assign clk_output = clk_sig; + + + + + +endmodule diff --git a/source/src/internal/internal_genlock_generator.v b/source/src/internal/internal_genlock_generator.v index e69de29..898c4ac 100644 --- a/source/src/internal/internal_genlock_generator.v +++ b/source/src/internal/internal_genlock_generator.v @@ -0,0 +1,116 @@ +`include "../config.v" +module internal_genlock_generator #( + parameter REG_START_ADD = 0, + parameter SYS_CLOCK_FREQ = 10000000 +) ( + + input clk, //! 时钟输入 + input rst_n, //! 复位输入 + + input [31:0] addr, //! 寄存器地址 + input [31:0] wr_data, //! 写入数据 + input wr_en, //! 写使能 + output wire [31:0] rd_data, //! 读出数据 + + output genlock_freq_signal //! genlock freq signal + +); + + reg [31:0] r1_contrl_mode; //! 控制模式,目前未使用 + reg [31:0] r2_en; //!使能控制 + reg [31:0] r3_format; //!格式 + wire [31:0] r4_detect_freq; //!输出频率探测 + + wire [31:0] reg_wr_index; + zutils_register_advanced #( + .REG_START_ADD(REG_START_ADD) + ) _register ( + .clk (clk), + .rst_n (rst_n), + .addr (addr), + .wr_data (wr_data), + .wr_en (wr_en), + .rd_data (rd_data), + .reg1 (r1_contrl_mode), + .reg2 (r2_en), + .reg3 (r3_format), + .reg4 (r4_detect_freq), + .reg_wr_sig(reg_wr_sig), + .reg_index (reg_wr_index) + ); + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + r1_contrl_mode <= 0; + r2_en <= 1; + r3_format <= 0; + end else begin + if (reg_wr_sig) begin + case (reg_wr_index) + 1: r1_contrl_mode <= wr_data; + 2: r2_en <= wr_data; + 3: r3_format <= wr_data; + default: begin + end + endcase + end + end + end + + wire genlock_fps2397_clk; + wire genlock_fps2398_clk; + wire genlock_fps2400_clk; + wire genlock_fps2500_clk; + wire genlock_fps2997_clk; + wire genlock_fps3000_clk; + wire genlock_fps5000_clk; + wire genlock_fps5994_clk; + wire genlock_fps6000_clk; + wire genlock_sig_output; + + zutils_genlock_clk_generator #( + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) genlock ( + .clk (clk), + .rst_n (rst_n), + .ctrl_sig (r2_en[0]), + .genlock_fps2397_clk(genlock_fps2397_clk), + .genlock_fps2398_clk(genlock_fps2398_clk), + .genlock_fps2400_clk(genlock_fps2400_clk), + .genlock_fps2500_clk(genlock_fps2500_clk), + .genlock_fps2997_clk(genlock_fps2997_clk), + .genlock_fps3000_clk(genlock_fps3000_clk), + .genlock_fps5000_clk(genlock_fps5000_clk), + .genlock_fps5994_clk(genlock_fps5994_clk), + .genlock_fps6000_clk(genlock_fps6000_clk) + ); + + zutils_multiplexer_32t1_v2 genlock_clk_output_mult ( + .chooseindex(r3_format), + //in + .in0 (genlock_fps2397_clk), + .in1 (genlock_fps2398_clk), + .in2 (genlock_fps2400_clk), + .in3 (genlock_fps2500_clk), + .in4 (genlock_fps2997_clk), + .in5 (genlock_fps3000_clk), + .in6 (genlock_fps5000_clk), + .in7 (genlock_fps5994_clk), + .in8 (genlock_fps6000_clk), + //out + .out (genlock_sig_output) + ); + + zutils_freq_detector_v2 freq_detector1 ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(1), + .pluse_input (genlock_sig_output), + .pluse_width_cnt (r4_detect_freq) + ); + + + assign genlock_freq_signal = genlock_sig_output; + assign genlock_in_state_led = 1; + +endmodule diff --git a/source/src/output/ttl_output.v b/source/src/output/ttl_output.v index 49252e1..3df5461 100644 --- a/source/src/output/ttl_output.v +++ b/source/src/output/ttl_output.v @@ -1,3 +1,4 @@ +`include "../config.v" module ttl_output #( parameter REG_START_ADD = 0, parameter SYS_CLOCK_FREQ = 10000000, @@ -107,7 +108,7 @@ module ttl_output #( reg_pllout_trigger_edge_select <= 1; reg_forward_mode_polarity_ctrl <= 0; reg_placeholder0 <= 0; - reg_freq_detect_bias <= 32'd10; + reg_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; end else begin if (reg_wr_sig) begin case (reg_wr_index) diff --git a/source/src/sys/sys_clock.v b/source/src/sys/sys_clock.v new file mode 100644 index 0000000..3e5980f --- /dev/null +++ b/source/src/sys/sys_clock.v @@ -0,0 +1,116 @@ +`include "../config.v" +module sys_clock #( + parameter REG_START_ADD = 0, + parameter SYS_CLOCK_FREQ = 10000000 +) ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + + //寄存器读写接口 + input [31:0] addr, + input [31:0] wr_data, + input wr_en, + output wire [31:0] rd_data, + + input [31:0] signal_in, + output sys_clock +); + + /******************************************************************************* + * 寄存器列表 * + *******************************************************************************/ + reg [31:0] reg1_sig_src; //!信号源选择 + reg [31:0] reg2_freq_division_ctrl; //!分频控制 + reg [31:0] reg3_freq_multiplication_ctrl; //!倍频控制 + reg [31:0] reg4_freq_detect_bias; //!频率探测滤波系数 + reg [31:0] reg5_trigger_edge_select; //!触发电平 + wire [31:0] regE_infreq_detect; //!输入频率探测 + wire [31:0] regF_outfreq_detect; //!输出频率探测 + + wire [31:0] reg_wr_index; //!寄存器写入时相对地址 + wire signal_in_choose; //!选择的信号源 + wire signal_in_af_pll; + + + //!TTLOUT_寄存器自动赋值选择器 + zutils_register_advanced #( + .REG_START_ADD(REG_START_ADD) + ) _register ( + .clk (clk), + .rst_n (rst_n), + .addr (addr), + .wr_data(wr_data), + .wr_en (wr_en), + .rd_data(rd_data), + .reg1 (reg1_sig_src), + .reg2 (reg2_freq_division_ctrl), + .reg3 (reg3_freq_multiplication_ctrl), + .reg4 (reg4_freq_detect_bias), + + .regE (regE_infreq_detect), + .regF (regF_outfreq_detect), + .reg_wr_sig(reg_wr_sig), + .reg_index (reg_wr_index) + ); + + //!寄存器写入逻辑 + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + + reg1_sig_src <= 0; + reg2_freq_division_ctrl <= 0; + reg3_freq_multiplication_ctrl <= 0; + reg4_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; + end else begin + if (reg_wr_sig) begin + case (reg_wr_index) + 1: reg1_sig_src <= wr_data; + 2: reg2_freq_division_ctrl <= wr_data; + 3: reg3_freq_multiplication_ctrl <= wr_data; + 4: reg4_freq_detect_bias <= wr_data; + default: begin + end + endcase + end + end + end + + //!信号选择器 + zutils_multiplexer_32t1 signal_in_multiplexer ( + .chooseindex(reg1_sig_src), + .signal (signal_in), + .signalout (signal_in_choose) + ); + + //!pll信号处理 + zsimple_pll _simple_pll ( + .clk (clk), + .rst_n (rst_n), + .insignal (signal_in_choose), + .trigger_eage_type (reg5_trigger_edge_select[0]), + .freq_detect_bias (reg4_freq_detect_bias), + .freq_division (reg2_freq_division_ctrl), + .freq_multiplication(reg3_freq_multiplication_ctrl), + .polarity_ctrl (1'd0), + .cfg_change (reg_wr_sig), + .outsignal (signal_in_af_pll) + ); + + zutils_freq_detector_v2 in_freq_detector ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(reg4_freq_detect_bias), + .pluse_input (signal_in_choose), + .pluse_width_cnt (regE_infreq_detect) + ); + + zutils_freq_detector_v2 output_freq_detector ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(reg4_freq_detect_bias), + .pluse_input (sys_clock), + .pluse_width_cnt (regF_outfreq_detect) + ); + assign sys_clock = signal_in_af_pll; + +endmodule diff --git a/source/src/sys/sys_genlock.v b/source/src/sys/sys_genlock.v new file mode 100644 index 0000000..a9e284d --- /dev/null +++ b/source/src/sys/sys_genlock.v @@ -0,0 +1,81 @@ +`include "../config.v" +module sys_genlock #( + parameter REG_START_ADD = 0, + parameter SYS_CLOCK_FREQ = 10000000 +) ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + + //寄存器读写接口 + input [31:0] addr, + input [31:0] wr_data, + input wr_en, + output wire [31:0] rd_data, + + input internal_genlock_sig, + input external_genlock_sig, + + output reg sys_genlock_tigger_sig +); + + /******************************************************************************* + * 寄存器列表 * + *******************************************************************************/ + reg [31:0] reg1_sig_src; //!信号源选择 + reg [31:0] reg2_genlock_freq_detect_bias; //!频率探测滤波参数 + wire [31:0] reg3_sig_freq; //!信号源频率 + + wire [31:0] reg_wr_index; //!寄存器写入时相对地址 + + //!TTLOUT_寄存器自动赋值选择器 + zutils_register_advanced #( + .REG_START_ADD(REG_START_ADD) + ) _register ( + .clk (clk), + .rst_n (rst_n), + .addr (addr), + .wr_data (wr_data), + .wr_en (wr_en), + .rd_data (rd_data), + .reg1 (reg1_sig_src), + .reg2 (reg2_genlock_freq_detect_bias), + .reg3 (reg3_sig_freq), + .reg_wr_sig(reg_wr_sig), + .reg_index (reg_wr_index) + ); + + //!寄存器写入逻辑 + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + reg1_sig_src <= 0; + reg2_genlock_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; + end else begin + if (reg_wr_sig) begin + case (reg_wr_index) + 1: reg1_sig_src <= wr_data; + 2: reg2_genlock_freq_detect_bias <= wr_data; + default: begin + end + endcase + end + end + end + + always @(*) begin + if (!reg1_sig_src[0]) begin + sys_genlock_tigger_sig <= internal_genlock_sig; + end else begin + sys_genlock_tigger_sig <= external_genlock_sig; + end + end + + zutils_freq_detector_v2 freq_detector1 ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(reg2_genlock_freq_detect_bias), + .pluse_input (sys_genlock_tigger_sig), + .pluse_width_cnt (reg3_sig_freq) + ); + + +endmodule diff --git a/source/src/top.v b/source/src/top.v index 72902f1..dc897a0 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -120,7 +120,7 @@ module Top ( wire signal_ext_timecode_freq; //! 外部时间码频率信号 wire signal_internal_timecode_freq; //! 内部时间码频率信号 wire signal_internal_genlock_freq; //! 内部GENLOCK频率信号 - wire signal_internal_freq_sig; //! 内部频率信号 + wire signal_internal_clk_sig; //! 内部频率信号 wire signal_sys_clk_output; //! 系统时钟输出 wire signal_sys_genlock_output; //! 系统GENLOCK输出 wire signal_sys_timecode_freq_output; //! 系统时间码频率输出 @@ -152,7 +152,7 @@ module Top ( assign sig_src[7] = signal_ext_timecode_freq; assign sig_src[8] = signal_internal_timecode_freq; assign sig_src[9] = signal_internal_genlock_freq; - assign sig_src[10] = signal_internal_freq_sig; + assign sig_src[10] = signal_internal_clk_sig; assign sig_src[11] = signal_sys_clk_output; assign sig_src[12] = signal_sys_genlock_output; assign sig_src[13] = signal_sys_timecode_freq_output; @@ -323,6 +323,36 @@ module Top ( .timecode_serial_data(internal_timecode_serial_data) ); + internal_genlock_generator #( + .REG_START_ADD (`REGADDOFF__INTERNAL_GENLOCK), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) internal_genlock_generator0 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_internal_genlock), + + .genlock_freq_signal(signal_internal_genlock_freq) + ); + + internal_clock_generator #( + .REG_START_ADD (`REGADDOFF__INTERNAL_CLOCK), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) internal_clock_generator0 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_internal_clock), + + .clk_output(signal_internal_clk_sig) + ); + /******************************************************************************* * SYS * *******************************************************************************/ @@ -355,6 +385,41 @@ module Top ( .sys_timecode_serial_data(sys_timecode_serial_data) ); + + sys_genlock #( + .REG_START_ADD (`REGADDOFF__SYS_GENLOCK), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) sys_genlock0 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_sys_genlock), + + .internal_genlock_sig(signal_internal_genlock_freq), + .external_genlock_sig(signal_ext_genlock_freq), + + .sys_genlock_tigger_sig(signal_sys_genlock_output) + ); + + sys_clock #( + .REG_START_ADD (`REGADDOFF__SYS_CLOCK), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) sys_clock0 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_sys_clock), + + .signal_in(sig_src), + .sys_clock(signal_sys_clk_output) + ); + /******************************************************************************* * TTL_OUTPUT * *******************************************************************************/ @@ -454,12 +519,12 @@ module Top ( .in_timecode_data (sys_timecode_data), .in_timecode_serial_data(sys_timecode_serial_data), - .timecode_out_bnc(timecode_out_bnc), - .timecode_out_bnc_select(timecode_out_bnc_select), + .timecode_out_bnc (timecode_out_bnc), + .timecode_out_bnc_select (timecode_out_bnc_select), .timecode_out_bnc_state_led(timecode_out_bnc_state_led), - .timecode_out_headphone(timecode_out_headphone), - .timecode_out_headphone_select(timecode_out_headphone_select), + .timecode_out_headphone (timecode_out_headphone), + .timecode_out_headphone_select (timecode_out_headphone_select), .timecode_out_headphone_state_led(timecode_out_headphone_state_led) );