forked from p_lusterinc_xsync/xsync_fpge
10 changed files with 611 additions and 92 deletions
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118led_test.pds
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3source/src/config.v
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69source/src/input/genlock_input_module.v
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3source/src/input/ttl_input.v
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117source/src/internal/internal_clock_generator.v
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116source/src/internal/internal_genlock_generator.v
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3source/src/output/ttl_output.v
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116source/src/sys/sys_clock.v
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81source/src/sys/sys_genlock.v
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77source/src/top.v
@ -0,0 +1,69 @@ |
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`include "../config.v" |
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module genlock_input_module #( |
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parameter REG_START_ADD = 0, |
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parameter SYS_CLOCK_FREQ = 10000000 |
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) ( |
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|
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input clk, //! 时钟输入 |
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input rst_n, //! 复位输入 |
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input [31:0] addr, //! 寄存器地址 |
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input [31:0] wr_data, //! 写入数据 |
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input wr_en, //! 写使能 |
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output wire [31:0] rd_data, //! 读出数据 |
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input genlock_in_hsync, //! genlock hsync |
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input genlock_in_vsync, //! genlock vsync |
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input genlock_in_fsync, //! genlock fsync |
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output genlock_freq_signal, //! genlock freq signal |
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output genlock_in_state_led |
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); |
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reg [31:0] r1_genlock_freq_detect_bias; |
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reg [31:0] r2_genlock_freq; |
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wire [31:0] reg_wr_index; |
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zutils_register_advanced #( |
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.REG_START_ADD(REG_START_ADD) |
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) _register ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.addr (addr), |
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.wr_data (wr_data), |
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.wr_en (wr_en), |
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.rd_data (rd_data), |
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.reg1 (r1_genlock_freq_detect_bias), |
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.reg2 (r2_genlock_freq), |
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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); |
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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r1_genlock_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; |
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end else begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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1: r1_genlock_freq_detect_bias <= wr_data; |
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default: begin |
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end |
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endcase |
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end |
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end |
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end |
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|
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zutils_freq_detector_v2 freq_detector1 ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.freq_detect_bias(r1_genlock_freq_detect_bias), |
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.pluse_input (ttlin1_sig_af_filter), |
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.pluse_width_cnt (r2_genlock_freq) |
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); |
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assign genlock_freq_signal = genlock_in_hsync; |
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assign genlock_in_state_led = 1; |
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endmodule |
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@ -0,0 +1,117 @@ |
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`include "../config.v" |
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module internal_clock_generator #( |
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parameter REG_START_ADD = 0, |
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parameter SYS_CLOCK_FREQ = 10000000 |
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) ( |
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|
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input clk, //! 时钟输入 |
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input rst_n, //! 复位输入 |
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input [31:0] addr, //! 寄存器地址 |
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input [31:0] wr_data, //! 写入数据 |
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input wr_en, //! 写使能 |
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output wire [31:0] rd_data, //! 读出数据 |
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output clk_output //! 输出频率 |
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); |
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reg [31:0] r1_contrl_mode; //! 控制模式,目前未使用 |
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reg [31:0] r2_en; //!使能控制 |
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reg [31:0] r3_setting_cnt; //!格式 |
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wire [31:0] r4_detect_freq; //!输出频率探测 |
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wire [31:0] reg_wr_index; |
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zutils_register_advanced #( |
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.REG_START_ADD(REG_START_ADD) |
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) _register ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.addr (addr), |
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.wr_data (wr_data), |
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.wr_en (wr_en), |
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.rd_data (rd_data), |
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.reg1 (r1_contrl_mode), |
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.reg2 (r2_en), |
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.reg3 (r3_setting_cnt), |
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.reg4 (r4_detect_freq), |
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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); |
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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r1_contrl_mode <= 0; |
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r2_en <= 1; |
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r3_setting_cnt <= 0; |
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end else begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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1: r1_contrl_mode <= wr_data; |
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2: r2_en <= wr_data; |
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3: r3_setting_cnt <= wr_data; |
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default: begin |
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end |
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endcase |
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end |
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end |
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end |
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reg state; |
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reg [31:0] cnt; |
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reg clk_sig; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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state <= 0; |
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clk_sig <= 0; |
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cnt <= 0; |
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end else begin |
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case (state) |
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0: begin |
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cnt <= 0; |
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clk_sig <= 0; |
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if (r2_en[0]) begin |
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state <= 1; |
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clk_sig <= 1; |
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end |
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end |
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1: begin |
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if (!r2_en[0]) begin |
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state <= 0; |
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end else begin |
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if (cnt < (r3_setting_cnt >> 1)) begin |
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cnt <= cnt + 1; |
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clk_sig <= 1; |
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end else if (cnt >= (r3_setting_cnt >> 1) && cnt < r3_setting_cnt) begin |
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cnt <= cnt + 1; |
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clk_sig <= 0; |
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end else begin |
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cnt <= 0; |
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clk_sig <= 1; |
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end |
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end |
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end |
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endcase |
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end |
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end |
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zutils_freq_detector_v2 freq_detector1 ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.freq_detect_bias(1), |
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.pluse_input (clk_sig), |
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.pluse_width_cnt (r4_detect_freq) |
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); |
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assign clk_output = clk_sig; |
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endmodule |
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@ -0,0 +1,116 @@ |
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`include "../config.v" |
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module internal_genlock_generator #( |
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parameter REG_START_ADD = 0, |
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parameter SYS_CLOCK_FREQ = 10000000 |
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) ( |
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|
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input clk, //! 时钟输入 |
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input rst_n, //! 复位输入 |
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input [31:0] addr, //! 寄存器地址 |
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input [31:0] wr_data, //! 写入数据 |
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input wr_en, //! 写使能 |
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output wire [31:0] rd_data, //! 读出数据 |
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output genlock_freq_signal //! genlock freq signal |
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); |
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reg [31:0] r1_contrl_mode; //! 控制模式,目前未使用 |
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reg [31:0] r2_en; //!使能控制 |
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reg [31:0] r3_format; //!格式 |
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wire [31:0] r4_detect_freq; //!输出频率探测 |
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wire [31:0] reg_wr_index; |
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zutils_register_advanced #( |
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.REG_START_ADD(REG_START_ADD) |
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) _register ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.addr (addr), |
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.wr_data (wr_data), |
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.wr_en (wr_en), |
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.rd_data (rd_data), |
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.reg1 (r1_contrl_mode), |
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.reg2 (r2_en), |
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.reg3 (r3_format), |
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.reg4 (r4_detect_freq), |
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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); |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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r1_contrl_mode <= 0; |
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r2_en <= 1; |
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r3_format <= 0; |
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end else begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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1: r1_contrl_mode <= wr_data; |
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2: r2_en <= wr_data; |
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3: r3_format <= wr_data; |
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default: begin |
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end |
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endcase |
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end |
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end |
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end |
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wire genlock_fps2397_clk; |
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wire genlock_fps2398_clk; |
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wire genlock_fps2400_clk; |
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wire genlock_fps2500_clk; |
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wire genlock_fps2997_clk; |
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wire genlock_fps3000_clk; |
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wire genlock_fps5000_clk; |
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wire genlock_fps5994_clk; |
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wire genlock_fps6000_clk; |
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wire genlock_sig_output; |
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zutils_genlock_clk_generator #( |
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) |
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) genlock ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.ctrl_sig (r2_en[0]), |
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.genlock_fps2397_clk(genlock_fps2397_clk), |
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.genlock_fps2398_clk(genlock_fps2398_clk), |
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.genlock_fps2400_clk(genlock_fps2400_clk), |
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.genlock_fps2500_clk(genlock_fps2500_clk), |
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.genlock_fps2997_clk(genlock_fps2997_clk), |
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.genlock_fps3000_clk(genlock_fps3000_clk), |
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.genlock_fps5000_clk(genlock_fps5000_clk), |
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.genlock_fps5994_clk(genlock_fps5994_clk), |
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.genlock_fps6000_clk(genlock_fps6000_clk) |
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); |
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zutils_multiplexer_32t1_v2 genlock_clk_output_mult ( |
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.chooseindex(r3_format), |
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//in |
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.in0 (genlock_fps2397_clk), |
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.in1 (genlock_fps2398_clk), |
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.in2 (genlock_fps2400_clk), |
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.in3 (genlock_fps2500_clk), |
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.in4 (genlock_fps2997_clk), |
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.in5 (genlock_fps3000_clk), |
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.in6 (genlock_fps5000_clk), |
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.in7 (genlock_fps5994_clk), |
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.in8 (genlock_fps6000_clk), |
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//out |
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.out (genlock_sig_output) |
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); |
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zutils_freq_detector_v2 freq_detector1 ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.freq_detect_bias(1), |
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.pluse_input (genlock_sig_output), |
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.pluse_width_cnt (r4_detect_freq) |
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); |
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assign genlock_freq_signal = genlock_sig_output; |
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assign genlock_in_state_led = 1; |
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endmodule |
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@ -0,0 +1,116 @@ |
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`include "../config.v" |
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module sys_clock #( |
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parameter REG_START_ADD = 0, |
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parameter SYS_CLOCK_FREQ = 10000000 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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//寄存器读写接口 |
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input [31:0] addr, |
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input [31:0] wr_data, |
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input wr_en, |
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output wire [31:0] rd_data, |
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input [31:0] signal_in, |
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output sys_clock |
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); |
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/******************************************************************************* |
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* 寄存器列表 * |
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*******************************************************************************/ |
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reg [31:0] reg1_sig_src; //!信号源选择 |
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reg [31:0] reg2_freq_division_ctrl; //!分频控制 |
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reg [31:0] reg3_freq_multiplication_ctrl; //!倍频控制 |
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reg [31:0] reg4_freq_detect_bias; //!频率探测滤波系数 |
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reg [31:0] reg5_trigger_edge_select; //!触发电平 |
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wire [31:0] regE_infreq_detect; //!输入频率探测 |
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wire [31:0] regF_outfreq_detect; //!输出频率探测 |
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|
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wire [31:0] reg_wr_index; //!寄存器写入时相对地址 |
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wire signal_in_choose; //!选择的信号源 |
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wire signal_in_af_pll; |
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|
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|
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//!TTLOUT_寄存器自动赋值选择器 |
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zutils_register_advanced #( |
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.REG_START_ADD(REG_START_ADD) |
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) _register ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.addr (addr), |
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.wr_data(wr_data), |
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.wr_en (wr_en), |
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.rd_data(rd_data), |
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.reg1 (reg1_sig_src), |
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.reg2 (reg2_freq_division_ctrl), |
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.reg3 (reg3_freq_multiplication_ctrl), |
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.reg4 (reg4_freq_detect_bias), |
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|
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.regE (regE_infreq_detect), |
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.regF (regF_outfreq_detect), |
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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); |
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|
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//!寄存器写入逻辑 |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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|
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reg1_sig_src <= 0; |
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reg2_freq_division_ctrl <= 0; |
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reg3_freq_multiplication_ctrl <= 0; |
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reg4_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; |
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end else begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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1: reg1_sig_src <= wr_data; |
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2: reg2_freq_division_ctrl <= wr_data; |
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3: reg3_freq_multiplication_ctrl <= wr_data; |
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4: reg4_freq_detect_bias <= wr_data; |
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default: begin |
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end |
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endcase |
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end |
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end |
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end |
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|
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//!信号选择器 |
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zutils_multiplexer_32t1 signal_in_multiplexer ( |
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.chooseindex(reg1_sig_src), |
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.signal (signal_in), |
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.signalout (signal_in_choose) |
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); |
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|
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//!pll信号处理 |
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zsimple_pll _simple_pll ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.insignal (signal_in_choose), |
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.trigger_eage_type (reg5_trigger_edge_select[0]), |
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.freq_detect_bias (reg4_freq_detect_bias), |
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.freq_division (reg2_freq_division_ctrl), |
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.freq_multiplication(reg3_freq_multiplication_ctrl), |
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.polarity_ctrl (1'd0), |
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.cfg_change (reg_wr_sig), |
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.outsignal (signal_in_af_pll) |
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); |
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|
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zutils_freq_detector_v2 in_freq_detector ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.freq_detect_bias(reg4_freq_detect_bias), |
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.pluse_input (signal_in_choose), |
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.pluse_width_cnt (regE_infreq_detect) |
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); |
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|
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zutils_freq_detector_v2 output_freq_detector ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.freq_detect_bias(reg4_freq_detect_bias), |
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.pluse_input (sys_clock), |
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.pluse_width_cnt (regF_outfreq_detect) |
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); |
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assign sys_clock = signal_in_af_pll; |
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|
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endmodule |
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@ -0,0 +1,81 @@ |
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`include "../config.v" |
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module sys_genlock #( |
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parameter REG_START_ADD = 0, |
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parameter SYS_CLOCK_FREQ = 10000000 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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|
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//寄存器读写接口 |
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input [31:0] addr, |
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input [31:0] wr_data, |
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input wr_en, |
||||
|
output wire [31:0] rd_data, |
||||
|
|
||||
|
input internal_genlock_sig, |
||||
|
input external_genlock_sig, |
||||
|
|
||||
|
output reg sys_genlock_tigger_sig |
||||
|
); |
||||
|
|
||||
|
/******************************************************************************* |
||||
|
* 寄存器列表 * |
||||
|
*******************************************************************************/ |
||||
|
reg [31:0] reg1_sig_src; //!信号源选择 |
||||
|
reg [31:0] reg2_genlock_freq_detect_bias; //!频率探测滤波参数 |
||||
|
wire [31:0] reg3_sig_freq; //!信号源频率 |
||||
|
|
||||
|
wire [31:0] reg_wr_index; //!寄存器写入时相对地址 |
||||
|
|
||||
|
//!TTLOUT_寄存器自动赋值选择器 |
||||
|
zutils_register_advanced #( |
||||
|
.REG_START_ADD(REG_START_ADD) |
||||
|
) _register ( |
||||
|
.clk (clk), |
||||
|
.rst_n (rst_n), |
||||
|
.addr (addr), |
||||
|
.wr_data (wr_data), |
||||
|
.wr_en (wr_en), |
||||
|
.rd_data (rd_data), |
||||
|
.reg1 (reg1_sig_src), |
||||
|
.reg2 (reg2_genlock_freq_detect_bias), |
||||
|
.reg3 (reg3_sig_freq), |
||||
|
.reg_wr_sig(reg_wr_sig), |
||||
|
.reg_index (reg_wr_index) |
||||
|
); |
||||
|
|
||||
|
//!寄存器写入逻辑 |
||||
|
always @(posedge clk or negedge rst_n) begin |
||||
|
if (!rst_n) begin |
||||
|
reg1_sig_src <= 0; |
||||
|
reg2_genlock_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; |
||||
|
end else begin |
||||
|
if (reg_wr_sig) begin |
||||
|
case (reg_wr_index) |
||||
|
1: reg1_sig_src <= wr_data; |
||||
|
2: reg2_genlock_freq_detect_bias <= wr_data; |
||||
|
default: begin |
||||
|
end |
||||
|
endcase |
||||
|
end |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
always @(*) begin |
||||
|
if (!reg1_sig_src[0]) begin |
||||
|
sys_genlock_tigger_sig <= internal_genlock_sig; |
||||
|
end else begin |
||||
|
sys_genlock_tigger_sig <= external_genlock_sig; |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
zutils_freq_detector_v2 freq_detector1 ( |
||||
|
.clk (clk), |
||||
|
.rst_n (rst_n), |
||||
|
.freq_detect_bias(reg2_genlock_freq_detect_bias), |
||||
|
.pluse_input (sys_genlock_tigger_sig), |
||||
|
.pluse_width_cnt (reg3_sig_freq) |
||||
|
); |
||||
|
|
||||
|
|
||||
|
endmodule |
||||
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