p_lusterinc_xsync
/
xsync_fpge_v2
forked from p_lusterinc_xsync/xsync_fpge
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

v4

master
zhaohe 1 year ago
parent
250b6ad8a8
commit
d8d5f16302
5 changed files with 59 additions and 48 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Unified View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 7
      README.md
  2. 58
      led_test.pds
  3. 2
      source/src/config.v
  4. 36
      source/src/output/camera_sync_signal_output.v
  5. 4
      source/src/timecode/timecode_generator.v

7
README.md
View File

@ -14,4 +14,11 @@ https://iflytop1.feishu.cn/wiki/DyHLwd2pLicjXxkWNEvc7vI7n2b
插件: 插件:
Documenter - TerosHDL 0.1.4 documentation Documenter - TerosHDL 0.1.4 documentation
Verilog-HDL/SystemVerilog/Bluespec SystemVerilog Verilog-HDL/SystemVerilog/Bluespec SystemVerilog
```
```
v0.0.0.4
1. 修复timecode启动时前两帧重复的问题
2. 修复timecode输出时候子帧出现00的情况
``` ```

58
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7" (_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Mar 29 14:58:03 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Thu Apr 11 09:37:35 2024")
(_version "1.0.5") (_version "1.0.5")
(_status "initial") (_status "initial")
(_project (_project
@ -123,7 +123,7 @@
) )
(_file "source/src/timecode/timecode_generator.v" (_file "source/src/timecode/timecode_generator.v"
(_format verilog) (_format verilog)
(_timespec "2024-03-25T17:29:22")
(_timespec "2024-04-11T09:27:05")
) )
(_file "source/src/output/timecode_output.v" (_file "source/src/output/timecode_output.v"
(_format verilog) (_format verilog)
@ -207,7 +207,7 @@
) )
(_file "source/src/output/camera_sync_signal_output.v" (_file "source/src/output/camera_sync_signal_output.v"
(_format verilog) (_format verilog)
(_timespec "2024-03-27T12:07:13")
(_timespec "2024-04-11T09:29:51")
) )
(_file "source/src/business/record_sig_generator.v" (_file "source/src/business/record_sig_generator.v"
(_format verilog) (_format verilog)
@ -315,17 +315,17 @@
(_db_output (_db_output
(_file "compile/Top_comp.adf" (_file "compile/Top_comp.adf"
(_format adif) (_format adif)
(_timespec "2024-03-29T14:52:35")
(_timespec "2024-04-11T09:30:16")
) )
) )
(_output (_output
(_file "compile/Top.cmr" (_file "compile/Top.cmr"
(_format verilog) (_format verilog)
(_timespec "2024-03-29T14:52:32")
(_timespec "2024-04-11T09:30:13")
) )
(_file "compile/cmr.db" (_file "compile/cmr.db"
(_format text) (_format text)
(_timespec "2024-03-29T14:52:35")
(_timespec "2024-04-11T09:30:16")
) )
) )
) )
@ -341,21 +341,21 @@
(_db_output (_db_output
(_file "synthesize/Top_syn.adf" (_file "synthesize/Top_syn.adf"
(_format adif) (_format adif)
(_timespec "2024-03-29T14:53:10")
(_timespec "2024-04-11T09:30:51")
) )
) )
(_output (_output
(_file "synthesize/Top_syn.vm" (_file "synthesize/Top_syn.vm"
(_format structural_verilog) (_format structural_verilog)
(_timespec "2024-03-29T14:53:12")
(_timespec "2024-04-11T09:30:53")
) )
(_file "synthesize/Top.snr" (_file "synthesize/Top.snr"
(_format text) (_format text)
(_timespec "2024-03-29T14:53:13")
(_timespec "2024-04-11T09:30:54")
) )
(_file "synthesize/snr.db" (_file "synthesize/snr.db"
(_format text) (_format text)
(_timespec "2024-03-29T14:53:13")
(_timespec "2024-04-11T09:30:54")
) )
) )
) )
@ -376,21 +376,21 @@
(_db_output (_db_output
(_file "device_map/Top_map.adf" (_file "device_map/Top_map.adf"
(_format adif) (_format adif)
(_timespec "2024-03-29T14:53:19")
(_timespec "2024-04-11T09:31:00")
) )
) )
(_output (_output
(_file "device_map/Top_dmr.prt" (_file "device_map/Top_dmr.prt"
(_format text) (_format text)
(_timespec "2024-03-29T14:53:16")
(_timespec "2024-04-11T09:30:57")
) )
(_file "device_map/Top.dmr" (_file "device_map/Top.dmr"
(_format text) (_format text)
(_timespec "2024-03-29T14:53:19")
(_timespec "2024-04-11T09:31:00")
) )
(_file "device_map/dmr.db" (_file "device_map/dmr.db"
(_format text) (_format text)
(_timespec "2024-03-29T14:53:19")
(_timespec "2024-04-11T09:31:00")
) )
) )
) )
@ -399,7 +399,7 @@
(_input (_input
(_file "device_map/led_test.pcf" (_file "device_map/led_test.pcf"
(_format pcf) (_format pcf)
(_timespec "2024-03-29T14:53:19")
(_timespec "2024-04-11T09:31:00")
) )
) )
) )
@ -420,33 +420,33 @@
(_db_output (_db_output
(_file "place_route/Top_pnr.adf" (_file "place_route/Top_pnr.adf"
(_format adif) (_format adif)
(_timespec "2024-03-29T14:57:34")
(_timespec "2024-04-11T09:36:21")
) )
) )
(_output (_output
(_file "place_route/Top.prr" (_file "place_route/Top.prr"
(_format text) (_format text)
(_timespec "2024-03-29T14:57:34")
(_timespec "2024-04-11T09:36:21")
) )
(_file "place_route/Top_prr.prt" (_file "place_route/Top_prr.prt"
(_format text) (_format text)
(_timespec "2024-03-29T14:57:34")
(_timespec "2024-04-11T09:36:19")
) )
(_file "place_route/clock_utilization.txt" (_file "place_route/clock_utilization.txt"
(_format text) (_format text)
(_timespec "2024-03-29T14:57:34")
(_timespec "2024-04-11T09:36:19")
) )
(_file "place_route/Top_plc.adf" (_file "place_route/Top_plc.adf"
(_format adif) (_format adif)
(_timespec "2024-03-29T14:56:04")
(_timespec "2024-04-11T09:31:51")
) )
(_file "place_route/Top_pnr.netlist" (_file "place_route/Top_pnr.netlist"
(_format text) (_format text)
(_timespec "2024-03-29T14:57:34")
(_timespec "2024-04-11T09:36:21")
) )
(_file "place_route/prr.db" (_file "place_route/prr.db"
(_format text) (_format text)
(_timespec "2024-03-29T14:57:35")
(_timespec "2024-04-11T09:36:23")
) )
) )
) )
@ -462,17 +462,17 @@
(_db_output (_db_output
(_file "report_timing/Top_rtp.adf" (_file "report_timing/Top_rtp.adf"
(_format adif) (_format adif)
(_timespec "2024-03-29T14:57:43")
(_timespec "2024-04-11T09:36:32")
) )
) )
(_output (_output
(_file "report_timing/Top.rtr" (_file "report_timing/Top.rtr"
(_format text) (_format text)
(_timespec "2024-03-29T14:57:43")
(_timespec "2024-04-11T09:36:34")
) )
(_file "report_timing/rtr.db" (_file "report_timing/rtr.db"
(_format text) (_format text)
(_timespec "2024-03-29T14:57:44")
(_timespec "2024-04-11T09:36:36")
) )
) )
) )
@ -497,19 +497,19 @@
(_output (_output
(_file "generate_bitstream/Top.sbit" (_file "generate_bitstream/Top.sbit"
(_format text) (_format text)
(_timespec "2024-03-29T14:58:03")
(_timespec "2024-04-11T09:37:33")
) )
(_file "generate_bitstream/Top.smsk" (_file "generate_bitstream/Top.smsk"
(_format text) (_format text)
(_timespec "2024-03-29T14:58:03")
(_timespec "2024-04-11T09:37:33")
) )
(_file "generate_bitstream/Top.bgr" (_file "generate_bitstream/Top.bgr"
(_format text) (_format text)
(_timespec "2024-03-29T14:58:03")
(_timespec "2024-04-11T09:37:33")
) )
(_file "generate_bitstream/bgr.db" (_file "generate_bitstream/bgr.db"
(_format text) (_format text)
(_timespec "2024-03-29T14:58:03")
(_timespec "2024-04-11T09:37:35")
) )
) )
) )

2
source/src/config.v
View File

@ -43,4 +43,4 @@
`define TTL_OUTPUT_TRIGGER_MODE_SIG_WIDTH 32'd1000 `define TTL_OUTPUT_TRIGGER_MODE_SIG_WIDTH 32'd1000
`define FREQ_DETECT_BIAS_DEFAULT 32'd10 `define FREQ_DETECT_BIAS_DEFAULT 32'd10
`define EXT_TIMECODE_FREQ_DETECT_BIAS_DEFAULT 32'd500 `define EXT_TIMECODE_FREQ_DETECT_BIAS_DEFAULT 32'd500
`define VERSION 32'd3
`define VERSION 32'd4

36
source/src/output/camera_sync_signal_output.v
View File

@ -89,6 +89,7 @@ module camera_sync_signal_output #(
reg [31:0] timecode_data_cache0; //! reg [31:0] timecode_data_cache0; //!
reg [31:0] timecode_data_cache1; //! reg [31:0] timecode_data_cache1; //!
reg [31:0] reg4_sub_frame_cnt_cache;
wire [ 1:0] trigger_sig; wire [ 1:0] trigger_sig;
assign trigger_sig[0] = frame_sig_rising_edge; assign trigger_sig[0] = frame_sig_rising_edge;
@ -96,34 +97,37 @@ module camera_sync_signal_output #(
always @(posedge clk or negedge rst_n) begin always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
reg2_timecode_snapshot0 <= 0;
reg3_timecode_snapshot1 <= 0;
reg4_sub_frame_cnt <= 0;
timecode_data_cache0 <= 0;
timecode_data_cache1 <= 0;
reg2_timecode_snapshot0 <= 0;
reg3_timecode_snapshot1 <= 0;
reg4_sub_frame_cnt <= 0;
timecode_data_cache0 <= 0;
timecode_data_cache1 <= 0;
reg4_sub_frame_cnt_cache <= 0;
end else begin end else begin
case (trigger_sig) case (trigger_sig)
2'b01: begin 2'b01: begin
//帧触发信号 //帧触发信号
reg2_timecode_snapshot0 <= timecode_data_cache0;
reg3_timecode_snapshot1 <= timecode_data_cache1;
reg4_sub_frame_cnt <= reg4_sub_frame_cnt + 1;
reg2_timecode_snapshot0 <= timecode_data_cache0;
reg3_timecode_snapshot1 <= timecode_data_cache1;
reg4_sub_frame_cnt_cache <= reg4_sub_frame_cnt_cache + 1;
reg4_sub_frame_cnt <= reg4_sub_frame_cnt_cache + 1;
end end
2'b10: begin 2'b10: begin
//时码变更触发信号 //时码变更触发信号
timecode_data_cache0 <= in_timecode_data[31:0];
timecode_data_cache1 <= in_timecode_data[63:32];
reg4_sub_frame_cnt <= 0;
timecode_data_cache0 <= in_timecode_data[31:0];
timecode_data_cache1 <= in_timecode_data[63:32];
reg4_sub_frame_cnt_cache <= 0;
end end
2'b11: begin 2'b11: begin
//帧触发信号&时码变更信号 //帧触发信号&时码变更信号
timecode_data_cache0 <= in_timecode_data[31:0];
timecode_data_cache1 <= in_timecode_data[63:32];
reg2_timecode_snapshot0 <= in_timecode_data[31:0];
reg3_timecode_snapshot1 <= in_timecode_data[63:32];
reg4_sub_frame_cnt <= 1;
timecode_data_cache0 <= in_timecode_data[31:0];
timecode_data_cache1 <= in_timecode_data[63:32];
reg2_timecode_snapshot0 <= in_timecode_data[31:0];
reg3_timecode_snapshot1 <= in_timecode_data[63:32];
reg4_sub_frame_cnt_cache <= 1;
reg4_sub_frame_cnt <= 1;
end end
default: begin default: begin

4
source/src/timecode/timecode_generator.v
View File

@ -69,9 +69,9 @@ module timecode_generator #(
end end
end else begin end else begin
if (frame_trigger_sig) begin if (frame_trigger_sig) begin
if (!first_frame_sig) begin
// if (!first_frame_sig) begin
timecode <= timecode_next; timecode <= timecode_next;
end
// end
timecode_trigger_sig <= 1; timecode_trigger_sig <= 1;
end else begin end else begin
timecode_trigger_sig <= 0; timecode_trigger_sig <= 0;

Write Preview
Loading…
Cancel
Save