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zsimple_pll ok

master
zhaohe 1 year ago
parent
a5cb5390ef
commit
e17130f2b3
2 changed files with 33 additions and 32 deletions
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  1. 58
      led_test.pds
  2. 5
      source/src/zutils/zsimple_pll.v

58
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7" (_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sat Mar 2 22:23:23 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sat Mar 2 22:45:22 2024")
(_version "1.0.5") (_version "1.0.5")
(_status "initial") (_status "initial")
(_project (_project
@ -167,7 +167,7 @@
) )
(_file "source/src/zutils/zsimple_pll.v" (_file "source/src/zutils/zsimple_pll.v"
(_format verilog) (_format verilog)
(_timespec "2024-03-02T22:20:29")
(_timespec "2024-03-02T22:44:30")
) )
(_file "source/src/zutils/zutils_freq_detector_v2.v" (_file "source/src/zutils/zutils_freq_detector_v2.v"
(_format verilog) (_format verilog)
@ -239,21 +239,21 @@
) )
(_task tsk_compile (_task tsk_compile
(_command cmd_compile (_command cmd_compile
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_db_output (_db_output
(_file "compile/Top_comp.adf" (_file "compile/Top_comp.adf"
(_format adif) (_format adif)
(_timespec "2024-03-02T22:22:37")
(_timespec "2024-03-02T22:44:36")
) )
) )
(_output (_output
(_file "compile/Top.cmr" (_file "compile/Top.cmr"
(_format verilog) (_format verilog)
(_timespec "2024-03-02T22:22:36")
(_timespec "2024-03-02T22:44:35")
) )
(_file "compile/cmr.db" (_file "compile/cmr.db"
(_format text) (_format text)
(_timespec "2024-03-02T22:22:37")
(_timespec "2024-03-02T22:44:36")
) )
) )
) )
@ -263,27 +263,27 @@
) )
(_task tsk_synthesis (_task tsk_synthesis
(_command cmd_synthesize (_command cmd_synthesize
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_option ads (_switch ON)) (_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2)) (_option selected_syn_tool_opt (_integer 2))
(_db_output (_db_output
(_file "synthesize/Top_syn.adf" (_file "synthesize/Top_syn.adf"
(_format adif) (_format adif)
(_timespec "2024-03-02T22:22:46")
(_timespec "2024-03-02T22:44:44")
) )
) )
(_output (_output
(_file "synthesize/Top_syn.vm" (_file "synthesize/Top_syn.vm"
(_format structural_verilog) (_format structural_verilog)
(_timespec "2024-03-02T22:22:46")
(_timespec "2024-03-02T22:44:45")
) )
(_file "synthesize/Top.snr" (_file "synthesize/Top.snr"
(_format text) (_format text)
(_timespec "2024-03-02T22:22:47")
(_timespec "2024-03-02T22:44:46")
) )
(_file "synthesize/snr.db" (_file "synthesize/snr.db"
(_format text) (_format text)
(_timespec "2024-03-02T22:22:47")
(_timespec "2024-03-02T22:44:46")
) )
) )
) )
@ -300,25 +300,25 @@
) )
(_task tsk_devmap (_task tsk_devmap
(_command cmd_devmap (_command cmd_devmap
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_db_output (_db_output
(_file "device_map/Top_map.adf" (_file "device_map/Top_map.adf"
(_format adif) (_format adif)
(_timespec "2024-03-02T22:22:50")
(_timespec "2024-03-02T22:44:49")
) )
) )
(_output (_output
(_file "device_map/Top_dmr.prt" (_file "device_map/Top_dmr.prt"
(_format text) (_format text)
(_timespec "2024-03-02T22:22:49")
(_timespec "2024-03-02T22:44:48")
) )
(_file "device_map/Top.dmr" (_file "device_map/Top.dmr"
(_format text) (_format text)
(_timespec "2024-03-02T22:22:50")
(_timespec "2024-03-02T22:44:49")
) )
(_file "device_map/dmr.db" (_file "device_map/dmr.db"
(_format text) (_format text)
(_timespec "2024-03-02T22:22:50")
(_timespec "2024-03-02T22:44:49")
) )
) )
) )
@ -327,7 +327,7 @@
(_input (_input
(_file "device_map/led_test.pcf" (_file "device_map/led_test.pcf"
(_format pcf) (_format pcf)
(_timespec "2024-03-02T22:22:50")
(_timespec "2024-03-02T22:44:49")
) )
) )
) )
@ -337,38 +337,38 @@
) )
(_task tsk_pnr (_task tsk_pnr
(_command cmd_pnr (_command cmd_pnr
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_option mode (_string "fast")) (_option mode (_string "fast"))
(_db_output (_db_output
(_file "place_route/Top_pnr.adf" (_file "place_route/Top_pnr.adf"
(_format adif) (_format adif)
(_timespec "2024-03-02T22:23:05")
(_timespec "2024-03-02T22:45:03")
) )
) )
(_output (_output
(_file "place_route/Top.prr" (_file "place_route/Top.prr"
(_format text) (_format text)
(_timespec "2024-03-02T22:23:05")
(_timespec "2024-03-02T22:45:03")
) )
(_file "place_route/Top_prr.prt" (_file "place_route/Top_prr.prt"
(_format text) (_format text)
(_timespec "2024-03-02T22:23:05")
(_timespec "2024-03-02T22:45:03")
) )
(_file "place_route/clock_utilization.txt" (_file "place_route/clock_utilization.txt"
(_format text) (_format text)
(_timespec "2024-03-02T22:23:05")
(_timespec "2024-03-02T22:45:03")
) )
(_file "place_route/Top_plc.adf" (_file "place_route/Top_plc.adf"
(_format adif) (_format adif)
(_timespec "2024-03-02T22:22:56")
(_timespec "2024-03-02T22:44:55")
) )
(_file "place_route/Top_pnr.netlist" (_file "place_route/Top_pnr.netlist"
(_format text) (_format text)
(_timespec "2024-03-02T22:23:05")
(_timespec "2024-03-02T22:45:03")
) )
(_file "place_route/prr.db" (_file "place_route/prr.db"
(_format text) (_format text)
(_timespec "2024-03-02T22:23:05")
(_timespec "2024-03-02T22:45:04")
) )
) )
) )
@ -403,19 +403,19 @@
(_output (_output
(_file "generate_bitstream/Top.sbit" (_file "generate_bitstream/Top.sbit"
(_format text) (_format text)
(_timespec "2024-03-02T22:23:21")
(_timespec "2024-03-02T22:45:21")
) )
(_file "generate_bitstream/Top.smsk" (_file "generate_bitstream/Top.smsk"
(_format text) (_format text)
(_timespec "2024-03-02T22:23:21")
(_timespec "2024-03-02T22:45:21")
) )
(_file "generate_bitstream/Top.bgr" (_file "generate_bitstream/Top.bgr"
(_format text) (_format text)
(_timespec "2024-03-02T22:23:21")
(_timespec "2024-03-02T22:45:21")
) )
(_file "generate_bitstream/bgr.db" (_file "generate_bitstream/bgr.db"
(_format text) (_format text)
(_timespec "2024-03-02T22:23:23")
(_timespec "2024-03-02T22:45:22")
) )
) )
) )

5
source/src/zutils/zsimple_pll.v
View File

@ -109,6 +109,7 @@ module zsimple_pll (
if(insignal_division) begin if(insignal_division) begin
multiplication_state <= 2; multiplication_state <= 2;
gen_pluse_cnt <= 0; gen_pluse_cnt <= 0;
insignal_multiplication <= 1;
multiplication_cnt <= 0; multiplication_cnt <= 0;
end end
end end
@ -117,10 +118,10 @@ module zsimple_pll (
multiplication_cnt <= multiplication_cnt + freq_multiplication + 1; multiplication_cnt <= multiplication_cnt + freq_multiplication + 1;
insignal_multiplication <= 1; insignal_multiplication <= 1;
end end
else if(multiplication_cnt >= insignal_multiplication_freq_cnt) begin
else if((multiplication_cnt+freq_multiplication+2) >= insignal_multiplication_freq_cnt) begin
gen_pluse_cnt <= gen_pluse_cnt + 1; gen_pluse_cnt <= gen_pluse_cnt + 1;
insignal_multiplication <= 1;
multiplication_cnt <= 0; multiplication_cnt <= 0;
insignal_multiplication <= 1;
gen_pluse_cnt <= gen_pluse_cnt + 1; gen_pluse_cnt <= gen_pluse_cnt + 1;
end end
else begin else begin

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