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update

master
zhaohe 2 years ago
parent
commit
e344e85ce8
  1. 128
      led_test.pds
  2. 2
      source/src/top.v

128
led_test.pds

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Jan 8 17:03:12 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Jan 8 17:16:47 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-01-08T16:08:57")
(_timespec "2024-01-08T17:16:22")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -128,17 +128,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-01-08T17:03:12")
(_timespec "2024-01-08T17:16:26")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-01-08T17:03:11")
(_timespec "2024-01-08T17:16:25")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-01-08T17:03:12")
(_timespec "2024-01-08T17:16:26")
)
)
)
@ -148,9 +148,29 @@
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-01-08T17:16:29")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-01-08T17:16:29")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-01-08T17:16:29")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-01-08T17:16:29")
)
)
)
(_widget wgt_tech_view
(_attribute _click_to_run (_switch ON))
@ -165,14 +185,34 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-01-08T17:16:32")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-01-08T17:16:32")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-01-08T17:16:32")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-01-08T17:16:32")
)
)
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/led_test.pcf"
(_format pcf)
(_timespec "2024-01-08T16:51:29")
(_timespec "2024-01-08T17:16:32")
)
)
)
@ -182,7 +222,39 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-01-08T17:16:38")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-01-08T17:16:38")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-01-08T17:16:38")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-01-08T17:16:38")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-01-08T17:16:36")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-01-08T17:16:38")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-01-08T17:16:38")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -191,8 +263,24 @@
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_attribute _auto_exe_lock (_switch OFF))
(_db_output
(_file "report_timing/Top_rtp.adf"
(_format adif)
(_timespec "2024-01-08T17:16:41")
)
)
(_output
(_file "report_timing/Top.rtr"
(_format text)
(_timespec "2024-01-08T17:16:41")
)
(_file "report_timing/rtr.db"
(_format text)
(_timespec "2024-01-08T17:16:42")
)
)
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
@ -210,7 +298,25 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-01-08T17:16:47")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-01-08T17:16:47")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-01-08T17:16:47")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-01-08T17:16:47")
)
)
)
)
)

2
source/src/top.v

@ -164,7 +164,7 @@ module Top (
wire [31:0] reg_reader_bus_wr_data;
wire reg_reader_bus_wr_en;
wire [31:0] reg_reader_bus_rd_data;
spi_reg_reader spi1_reg_reader_inst (
spi_reg_reader spi_reg_reader_inst (
.clk (sys_clk),
.rst_n(rst_n),

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