p_lusterinc_xsync
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xsync_fpge_v2
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v1.0.7

master
zhaohe 9 months ago
parent
1c699be709
commit
f495d45bf5
6 changed files with 78 additions and 149 deletions
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  1. 9
      README.md
  2. 58
      source/src/app_top.v
  3. 2
      source/src/config.v
  4. 26
      source/src/input/timecode_input.v
  5. 130
      xsync.pds
  6. 2
      xsync.pds.lock

9
README.md
View File

@ -31,5 +31,14 @@ cfg_gen_sfc -device_name W25Q128Q -opcode 107 -sbit_start_address 0 -sbit ./gene
v1.0.6
1. 开机默认timecode不启动
v1.0.7
1.失能掉系统延迟延时功能模块
```
```
BUG:
系统延时功能模块的BUG
1. 输入信号没有经过滤波就给了延迟模块，延迟模块处理不了这种信号
2. 延迟模块只能延后一个脉冲信号
```

58
source/src/app_top.v
View File

@ -52,6 +52,8 @@ module AppTop (
output wire debug_tcin_ch2_sample_sig,
output wire debug_tcin_ch2_in_sig_edge,
output wire [15:0] sys_sig_delay_out,
output wire endsig
);
@ -239,7 +241,7 @@ module AppTop (
wire [15:0] sys_sig_delay_in;
wire [15:0] sys_sig_delay_out;
// wire [15:0] sys_sig_delay_out;
wire before_delay__sync_ttl_out1;
wire before_delay__sync_ttl_out2;
@ -294,25 +296,41 @@ module AppTop (
assign stm32if_camera_sync_out = sys_sig_delay_out[14];
assign stm32if_timecode_sync_out = sys_sig_delay_out[15];
sys_signal_delayer #(
.REG_START_ADD (`REGADDOFF__DELAYER),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.SIG_BUS_WIDTH (15)
) sys_signal_delayer_ins (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr (RegReaderBus_addr),
.wr_data(RegReaderBus_wr_data),
.wr_en (RegReaderBus_wr_en),
.rd_data(RegReaderBus_rd_data),
.sig_in (sys_sig_delay_in),
.sig_out(sys_sig_delay_out)
);
assign sys_sig_delay_out[0] = sys_sig_delay_in[0];
assign sys_sig_delay_out[1] = sys_sig_delay_in[1];
assign sys_sig_delay_out[2] = sys_sig_delay_in[2];
assign sys_sig_delay_out[3] = sys_sig_delay_in[3];
assign sys_sig_delay_out[4] = sys_sig_delay_in[4];
assign sys_sig_delay_out[5] = sys_sig_delay_in[5];
assign sys_sig_delay_out[7] = sys_sig_delay_in[7];
assign sys_sig_delay_out[6] = sys_sig_delay_in[6];
assign sys_sig_delay_out[8] = sys_sig_delay_in[8];
assign sys_sig_delay_out[9] = sys_sig_delay_in[9];
assign sys_sig_delay_out[10] = sys_sig_delay_in[10];
assign sys_sig_delay_out[11] = sys_sig_delay_in[11];
assign sys_sig_delay_out[12] = sys_sig_delay_in[12];
assign sys_sig_delay_out[13] = sys_sig_delay_in[13];
assign sys_sig_delay_out[14] = sys_sig_delay_in[14];
assign sys_sig_delay_out[15] = sys_sig_delay_in[15];
// sys_signal_delayer #(
// .REG_START_ADD (`REGADDOFF__DELAYER),
// .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
// .SIG_BUS_WIDTH (15)
// ) sys_signal_delayer_ins (
// .clk (sys_clk),
// .rst_n(sys_rst_n),
// .addr (RegReaderBus_addr),
// .wr_data(RegReaderBus_wr_data),
// .wr_en (RegReaderBus_wr_en),
// .rd_data(RegReaderBus_rd_data),
// .sig_in (sys_sig_delay_in),
// .sig_out(sys_sig_delay_out)
// );

2
source/src/config.v
View File

@ -43,4 +43,4 @@
`define TTL_OUTPUT_TRIGGER_MODE_SIG_WIDTH 32'd1000
`define FREQ_DETECT_BIAS_DEFAULT 32'd10
`define EXT_TIMECODE_FREQ_DETECT_BIAS_DEFAULT 32'd5000
`define VERSION 32'h00010006 //32'h main(2byte) sub(1byte) fix(1byte)
`define VERSION 32'h00010007 //32'h main(2byte) sub(1byte) fix(1byte)

26
source/src/input/timecode_input.v
View File

@ -54,6 +54,7 @@ module timecode_input #(
reg [31:0] r4_timecode1; //
reg [31:0] r5_freq; //
reg [31:0] r6_freq_direct; //
reg [31:0] r7_in_sig_filter_cnt; //
reg [31:0] rA_freq_bias; //
wire [31:0] reg_wr_index;
@ -73,6 +74,7 @@ module timecode_input #(
.reg4(r4_timecode1),
.reg5(r5_freq),
.reg6(r6_freq_direct),
.reg7(r7_in_sig_filter_cnt),
.regA (rA_freq_bias),
.reg_wr_sig(reg_wr_sig),
@ -81,11 +83,13 @@ module timecode_input #(
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rA_freq_bias <= `EXT_TIMECODE_FREQ_DETECT_BIAS_DEFAULT;
rA_freq_bias <= `EXT_TIMECODE_FREQ_DETECT_BIAS_DEFAULT;
r7_in_sig_filter_cnt <= 32'd100;
end else begin
if (reg_wr_sig) begin
case (reg_wr_index)
31'hA: rA_freq_bias <= wr_data;
31'h7: r7_in_sig_filter_cnt <= wr_data;
default: begin
end
endcase
@ -111,9 +115,17 @@ module timecode_input #(
zutils_signal_filter_advance filter1 (
.clk (clk),
.rst_n (rst_n),
.filter_delay_count(10),
.filter_delay_count(r7_in_sig_filter_cnt),
.in (timecode_bnc_in),
.out (timecode_bnc_in_after)
.out (timecode_bnc_in_af_filter)
);
zutils_signal_filter_advance filter2 (
.clk (clk),
.rst_n (rst_n),
.filter_delay_count(r7_in_sig_filter_cnt),
.in (timecode_headphone_in),
.out (timecode_headphone_in_af_filter)
);
@ -137,10 +149,10 @@ module timecode_input #(
) timecode_decoder_2 (
.clk (clk),
.rst_n (rst_n),
.timecode_in (timecode_headphone_in), // 时码输入
.timecode_tigger_sig (ch2_timecode_tigger_sig), //
.timecode_data (ch2_timecode_data), //[63:0]
.timecode_serial_data(ch2_timecode_serial_data), //
.timecode_in (timecode_headphone_in_af_filter), // 时码输入
.timecode_tigger_sig (ch2_timecode_tigger_sig), //
.timecode_data (ch2_timecode_data), //[63:0]
.timecode_serial_data(ch2_timecode_serial_data), //
.debug_sample_sig (debug_ch2_sample_sig),
.debug_in_sig_edge (debug_ch2_in_sig_edge)
);

130
xsync.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2022.2-SP4.2"
(_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Sun Nov 3 17:27:00 2024")
(_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Tue Nov 5 13:31:53 2024")
(_version "1.1.0")
(_status "initial")
(_project
@ -213,7 +213,7 @@
)
(_file "source/src/sys_signal_delayer.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-11-05T13:28:30")
)
(_file "source/src/zutils/zutils_sig_delayer.v"
(_format verilog)
@ -229,7 +229,7 @@
)
(_file "source/src/internal/internal_sig_generator_en_contrler.v"
(_format verilog)
(_timespec "2024-11-03T17:10:02")
(_timespec "2024-11-05T13:17:59")
)
(_file "source/src/zutils/zutils_timer.v"
(_format verilog)
@ -241,7 +241,7 @@
)
(_file "source/src/app_top.v"
(_format verilog)
(_timespec "2024-11-03T14:03:01")
(_timespec "2024-11-05T13:28:44")
)
(_file "source/src/timecode/timecode_freq_detector.v"
(_format verilog)
@ -330,23 +330,7 @@
)
(_task tsk_compile
(_command cmd_compile
(_gci_state (_integer 2))
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-11-03T17:12:52")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-11-03T17:12:52")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-11-03T17:12:52")
)
)
(_gci_state (_integer 5))
)
(_widget wgt_rtl_view
(_attribute _click_to_run (_switch ON))
@ -354,32 +338,8 @@
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 2))
(_gci_state (_integer 0))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-11-03T17:15:49")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-11-03T17:16:04")
)
(_file "synthesize/Top_controlsets.txt"
(_format text)
(_timespec "2024-11-03T17:15:35")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-11-03T17:16:12")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-11-03T17:16:12")
)
)
)
(_widget wgt_tech_view
(_attribute _click_to_run (_switch ON))
@ -394,34 +354,14 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 2))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-11-03T17:16:59")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-11-03T17:16:40")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-11-03T17:17:00")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-11-03T17:17:00")
)
)
(_gci_state (_integer 0))
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/xsync.pcf"
(_format pcf)
(_timespec "2024-11-03T17:17:00")
(_timespec "2024-11-05T11:05:49")
)
)
)
@ -431,7 +371,7 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 2))
(_gci_state (_integer 0))
(_option gplace_seed (_integer 8))
(_option seed_step (_integer 4))
(_option saved_outcome (_integer 4))
@ -439,38 +379,6 @@
(_option share_router_control_signal (_boolean FALSE))
(_option check_clk_net_route_by_srb (_boolean FALSE))
(_option fix_hold_violation_in_route (_boolean FALSE))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-11-03T17:25:08")
)
)
(_output
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-11-03T17:24:22")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-11-03T17:20:44")
)
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-11-03T17:25:10")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-11-03T17:24:22")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-11-03T17:25:09")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-11-03T17:25:10")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -499,26 +407,8 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 2))
(_gci_state (_integer 0))
(_option unused_io_status (_string "KEEPER"))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-11-03T17:26:56")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-11-03T17:26:56")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-11-03T17:27:00")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-11-03T17:27:00")
)
)
)
)
)

2
xsync.pds.lock
View File

@ -1,4 +1,4 @@
14124
21512
pds
ZHAOHE
f8caf121-d1d2-4c26-8a45-7e1d59cde8b6

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