From f64a6052e0dec17322dba3c51912ebd6f51e02aa Mon Sep 17 00:00:00 2001 From: zhaohe Date: Wed, 6 Mar 2024 00:06:28 +0800 Subject: [PATCH] update --- led_test.pds | 96 +++------- source/src/business/record_sig_generator.v | 251 ++++++++++++++++++++++++++ source/src/output/camera_sync_signal_output.v | 4 +- source/src/top.v | 49 ++++- 4 files changed, 327 insertions(+), 73 deletions(-) create mode 100644 source/src/business/record_sig_generator.v diff --git a/led_test.pds b/led_test.pds index 2d9f469..7fc7a7c 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Tue Mar 5 19:27:36 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Tue Mar 5 23:58:26 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-03-05T16:15:17") + (_timespec "2024-03-05T23:54:38") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -205,6 +205,14 @@ (_format verilog) (_timespec "2024-03-05T16:10:23") ) + (_file "source/src/output/camera_sync_signal_output.v" + (_format verilog) + (_timespec "2024-03-05T22:17:42") + ) + (_file "source/src/business/record_sig_generator.v" + (_format verilog) + (_timespec "2024-03-05T23:58:23") + ) ) ) (_widget wgt_my_ips_src @@ -271,21 +279,21 @@ ) (_task tsk_compile (_command cmd_compile - (_gci_state (_integer 2)) + (_gci_state (_integer 3)) (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-03-05T19:17:20") + (_timespec "2024-03-05T23:56:26") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-03-05T19:17:18") + (_timespec "2024-03-05T23:56:23") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-03-05T19:17:21") + (_timespec "2024-03-05T23:56:26") ) ) ) @@ -295,27 +303,27 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 2)) + (_gci_state (_integer 3)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-03-05T19:19:41") + (_timespec "2024-03-05T23:58:05") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-03-05T19:19:53") + (_timespec "2024-03-05T23:58:14") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-03-05T19:20:01") + (_timespec "2024-03-05T23:58:20") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-03-05T19:20:01") + (_timespec "2024-03-05T23:58:20") ) ) ) @@ -332,25 +340,25 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 2)) + (_gci_state (_integer 3)) (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-03-05T19:20:16") + (_timespec "2024-03-05T23:58:26") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-03-05T19:20:04") + (_timespec "2024-03-05T23:58:23") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-03-05T19:20:16") + (_timespec "2024-03-05T23:58:26") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-03-05T19:20:17") + (_timespec "2024-03-05T23:58:26") ) ) ) @@ -359,7 +367,7 @@ (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-03-05T19:20:16") + (_timespec "2024-03-05T23:58:26") ) ) ) @@ -369,40 +377,8 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 2)) + (_gci_state (_integer 0)) (_option mode (_string "fast")) - (_db_output - (_file "place_route/Top_pnr.adf" - (_format adif) - (_timespec "2024-03-05T19:26:10") - ) - ) - (_output - (_file "place_route/Top.prr" - (_format text) - (_timespec "2024-03-05T19:26:10") - ) - (_file "place_route/Top_prr.prt" - (_format text) - (_timespec "2024-03-05T19:26:08") - ) - (_file "place_route/clock_utilization.txt" - (_format text) - (_timespec "2024-03-05T19:26:08") - ) - (_file "place_route/Top_plc.adf" - (_format adif) - (_timespec "2024-03-05T19:21:27") - ) - (_file "place_route/Top_pnr.netlist" - (_format text) - (_timespec "2024-03-05T19:26:10") - ) - (_file "place_route/prr.db" - (_format text) - (_timespec "2024-03-05T19:26:12") - ) - ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -431,25 +407,7 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 2)) - (_output - (_file "generate_bitstream/Top.sbit" - (_format text) - (_timespec "2024-03-05T19:27:34") - ) - (_file "generate_bitstream/Top.smsk" - (_format text) - (_timespec "2024-03-05T19:27:34") - ) - (_file "generate_bitstream/Top.bgr" - (_format text) - (_timespec "2024-03-05T19:27:34") - ) - (_file "generate_bitstream/bgr.db" - (_format text) - (_timespec "2024-03-05T19:27:36") - ) - ) + (_gci_state (_integer 0)) ) ) ) diff --git a/source/src/business/record_sig_generator.v b/source/src/business/record_sig_generator.v new file mode 100644 index 0000000..d312f98 --- /dev/null +++ b/source/src/business/record_sig_generator.v @@ -0,0 +1,251 @@ +module record_sig_generator #( + parameter REG_START_ADD = 0, + parameter SYS_CLOCK_FREQ = 10000000, + parameter TEST = 0 +) ( + input clk, + input rst_n, + + input [31:0] addr, + input [31:0] wr_data, + input wr_en, + output wire [31:0] rd_data, + + input wire ttlin1_sig, + input wire ttlin2_sig, + input wire ttlin3_sig, + input wire ttlin4_sig, + + input wire frame_freq_sig, + input wire sys_timecode_tigger_sig, + input wire [63:0] sys_timecode_data, + + output reg out_record_en_sig, //!录制使能信号 + output reg out_record_exposure_sig //!录制曝光信号 + +); + + + + reg [31:0] reg1_ctrl_control_mode; //! 控制模式选择寄存器 + + reg [31:0] reg2_timecode_start0; //! 时码启动寄存器0 + reg [31:0] reg3_timecode_start1; //! 时码启动寄存器1 + reg [31:0] reg4_timecode_stop0; //! 时码停止寄存器0 + reg [31:0] reg5_timecode_stop1; //! 时码停止寄存器1 + reg [31:0] reg6_timecode_control_flag; //! 使能时码控制启动，使能使能时码控制停止 + + reg [31:0] reg7_ttlin_trigger_sig_source; //! TTL触发信号选择 + reg [31:0] reg8_ttlin_trigger_level; //! TTL输入信号极性反转 + + reg [31:0] reg9_exposure_time; //! 曝光时长 + reg [31:0] regA_exposure_delay; //! 曝光信号延迟 + + reg [31:0] regB_manual_ctrl; //! 手动控制 + localparam REGA_MANUAL_CTRL_REG_INDEX = 32'd11; + + reg [31:0] regD_start_timecode_snapshot0; //! + reg [31:0] regE_start_timecode_snapshot1; //! + reg [31:0] regF_record_state; //!工作状态 read only + + wire [31:0] reg_wr_index; + + zutils_register_advanced #( + .REG_START_ADD(REG_START_ADD) + ) _register ( + .clk (clk), + .rst_n (rst_n), + .addr (addr), + .wr_data(wr_data), + .wr_en (wr_en), + .rd_data(rd_data), + + .reg1(reg1_ctrl_control_mode), + .reg2(reg2_timecode_start0), + .reg3(reg3_timecode_start1), + .reg4(reg4_timecode_stop0), + .reg5(reg5_timecode_stop1), + .reg6(reg6_timecode_control_flag), + .reg7(reg7_ttlin_trigger_sig_source), + .reg8(reg8_ttlin_trigger_level), + .reg9(reg9_exposure_time), + .regA(regA_exposure_delay), + + .regB(regB_manual_ctrl), + .regD(regD_start_timecode_snapshot0), + .regE(regE_start_timecode_snapshot1), + .regF(regF_record_state), + + .reg_wr_sig(reg_wr_sig), + .reg_index (reg_wr_index) + ); + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + reg1_ctrl_control_mode <= 1; + reg2_timecode_start0 <= 0; + reg3_timecode_start1 <= 0; + reg4_timecode_stop0 <= 0; + reg5_timecode_stop1 <= 0; + reg6_timecode_control_flag <= 32'hFFFF_FFFF; + reg7_ttlin_trigger_sig_source <= 1; + reg8_ttlin_trigger_level <= 1; + reg9_exposure_time <= 32'd1000; //100us + regA_exposure_delay <= 0; + regB_manual_ctrl <= 0; + end else begin + if (reg_wr_sig) begin + case (reg_wr_index) + 1: reg1_ctrl_control_mode <= wr_data; + 2: reg2_timecode_start0 <= wr_data; + 3: reg3_timecode_start1 <= wr_data; + 4: reg4_timecode_stop0 <= wr_data; + 5: reg5_timecode_stop1 <= wr_data; + 6: reg6_timecode_control_flag <= wr_data; + 7: reg7_ttlin_trigger_sig_source <= wr_data; + 8: reg8_ttlin_trigger_level <= wr_data; + 9: reg9_exposure_time <= wr_data; + 10: regA_exposure_delay <= wr_data; + default: begin + end + endcase + end + end + end + + + wire ttl_in_choose; //! 选中的ttl触发信号，(已经经过电平翻转) + wire timecode_start_trigger_sig; //!timecode启动信号 + wire timecode_stop_trigger_sig; //!timecode停止信号 + wire record_exposure_sig; //!曝光信号 + wire frame_freq_sig_rising_edge; + + + zutils_multiplexer_32t1_v2 ttlin_level_trigger_multi ( + .chooseindex(reg7_ttlin_trigger_sig_source), + //in + .in1 (ttlin1_sig ^ (!reg8_ttlin_trigger_level[0])), + .in2 (ttlin2_sig ^ (!reg8_ttlin_trigger_level[0])), + .in3 (ttlin3_sig ^ (!reg8_ttlin_trigger_level[0])), + .in4 (ttlin4_sig ^ (!reg8_ttlin_trigger_level[0])), + //out + .out (ttl_in_choose) + ); + + /******************************************************************************* + * StartSig输出 * + *******************************************************************************/ + + timecode_comparator timecode_comparator_inst0 ( + .timecodeA0(sys_timecode_data[31:0]), + .timecodeA1(sys_timecode_data[63:32]), + .timecodeB0(reg2_timecode_start0), + .timecodeB1(reg3_timecode_start1), + .eq (timecode_start_trigger_sig) + ); + + timecode_comparator timecode_comparator_inst1 ( + .timecodeA0(sys_timecode_data[31:0]), + .timecodeA1(sys_timecode_data[63:32]), + .timecodeB0(reg4_timecode_stop0), + .timecodeB1(reg5_timecode_stop1), + .eq (timecode_stop_trigger_sig) + ); + + + zutils_edge_detecter _signal_in ( + .clk (clk), + .rst_n (rst_n), + .in_signal (frame_freq_sig), + .in_signal_rising_edge(frame_freq_sig_rising_edge) + ); + + zutils_pluse_generator _pluse_generator ( + .clk (clk), + .rst_n (rst_n), + .pluse_width (reg9_exposure_time), + .pluse_delay (regA_exposure_delay), + .trigger (frame_freq_sig_rising_edge), + .output_signal(record_exposure_sig) + ); + + reg en_state; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + en_state <= 0; + end else begin + case (reg1_ctrl_control_mode) + 1: begin + //手动控制触发启动停止 + if (reg_wr_sig && reg_wr_index == REGA_MANUAL_CTRL_REG_INDEX) begin + if (wr_data[0] == 1) begin + en_state <= 1; + end else begin + en_state <= 0; + end + end + + end + 2: begin + //TIMECODE控制启动 + if (timecode_start_trigger_sig && sys_timecode_tigger_sig && reg6_timecode_control_flag[0]) begin + en_state <= 1; + end else if (timecode_stop_trigger_sig && sys_timecode_tigger_sig && reg6_timecode_control_flag[1]) begin + en_state <= 0; + end else if (reg_wr_sig && reg_wr_index == REGA_MANUAL_CTRL_REG_INDEX) begin + if (wr_data[0] == 1) begin + en_state <= 1; + end else begin + en_state <= 0; + end + end + end + + 3: begin + //外部电平控制 + if (ttl_in_choose == 1) begin + en_state <= 1; + end else begin + en_state <= 0; + end + end + default: begin + end + endcase + end + end + + + reg en_state_af_sync; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + en_state_af_sync <= 0; + end else begin + case (en_state) + 0: begin + if (en_state_af_sync != en_state) begin + en_state_af_sync <= 0; + end + end + + 1: begin + if (en_state_af_sync == 0) begin + if (frame_freq_sig_rising_edge) begin + regD_start_timecode_snapshot0 <= sys_timecode_data[31:0]; + regE_start_timecode_snapshot1 <= sys_timecode_data[63:32]; + en_state_af_sync <= 1; + end + end + end + endcase + end + end + + + always @(*) begin + regF_record_state[0] <= en_state_af_sync; + out_record_en_sig <= en_state_af_sync; + out_record_exposure_sig <= out_record_en_sig & record_exposure_sig; + end + +endmodule diff --git a/source/src/output/camera_sync_signal_output.v b/source/src/output/camera_sync_signal_output.v index 2451a70..8d41a82 100644 --- a/source/src/output/camera_sync_signal_output.v +++ b/source/src/output/camera_sync_signal_output.v @@ -40,7 +40,7 @@ module camera_sync_signal_output #( always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - reg1_pulse_mode_valid_len <= 0; + reg1_pulse_mode_valid_len <= SYS_CLOCK_FREQ / 1000; end else begin if (reg_wr_sig) begin case (reg_wr_index) @@ -71,7 +71,7 @@ module camera_sync_signal_output #( zutils_pluse_generator _pluse_generator ( .clk (clk), .rst_n (rst_n), - .pluse_width (SYS_CLOCK_FREQ / 1000), //100us + .pluse_width (reg1_pulse_mode_valid_len), //100us .pluse_delay (0), .trigger (frame_sig_rising_edge), .output_signal(frame_sig_fa_process) diff --git a/source/src/top.v b/source/src/top.v index c461578..58ecaf6 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -124,7 +124,7 @@ module Top ( wire signal_sys_clk_output; //! 系统时钟输出 wire signal_sys_genlock_output; //! 系统GENLOCK输出 wire signal_sys_timecode_freq_output; //! 系统时间码频率输出 - wire signal_business_record_sig; //! 业务摄影状态信号 + wire signal_business_record_en_sig; //! 业务摄影状态信号 wire signal_business_record_exposure_sig; //! 业务摄影拍照曝光信号 wire internal_timecode_tigger_sig; //!内部timecode频率信号 @@ -157,7 +157,7 @@ module Top ( assign sig_src[`SIGNAL_SYS_CLK_OUTPUT] = signal_sys_clk_output; assign sig_src[`SIGNAL_SYS_GENLOCK_OUTPUT] = signal_sys_genlock_output; assign sig_src[`SIGNAL_SYS_TIMECODE_FREQ_OUTPUT] = signal_sys_timecode_freq_output; - assign sig_src[`SIGNAL_BUSINESS_RECORD_SIG] = signal_business_record_sig; + assign sig_src[`SIGNAL_BUSINESS_RECORD_SIG] = signal_business_record_en_sig; assign sig_src[`SIGNAL_BUSINESS_RECORD_EXPOSURE_SIG] = signal_business_record_exposure_sig; assign signal_logic0 = 1'b0; @@ -552,6 +552,51 @@ module Top ( ); + record_sig_generator #( + .REG_START_ADD(`REGADDOFF__RECORD_SIG_GENERATOR), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .TEST(0) + ) record_sig_generator0 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_record_sig_generator), + + .ttlin1_sig(signal_ttlin1), + .ttlin2_sig(signal_ttlin2), + .ttlin3_sig(signal_ttlin3), + .ttlin4_sig(signal_ttlin4), + + .frame_freq_sig (signal_sys_clk_output), + .sys_timecode_tigger_sig(sys_timecode_tigger_sig), + .sys_timecode_data (sys_timecode_data), + + .out_record_en_sig (signal_business_record_en_sig), + .out_record_exposure_sig(signal_business_record_exposure_sig) + ); + + camera_sync_signal_output #( + .REG_START_ADD (`REGADDOFF__CAMERA_SYNC_OUT), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) camera_sync_signal_output0 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_camera_sync_out), + + .frame_sig (signal_business_record_exposure_sig), + .record_en_sig(signal_business_record_en_sig), + + .stm32if_camera_sync_out(stm32if_camera_sync_out), + .stm32if_record_sync_out(stm32if_start_signal_out) + ); + assign debug_signal_output[0] = sys_clk; assign debug_signal_output[1] = sync_ttl_in1; assign debug_signal_output[2] = sync_ttl_in2;