forked from p_lusterinc_xsync/xsync_fpge
4 changed files with 327 additions and 73 deletions
-
96led_test.pds
-
251source/src/business/record_sig_generator.v
-
4source/src/output/camera_sync_signal_output.v
-
49source/src/top.v
@ -0,0 +1,251 @@ |
|||||
|
module record_sig_generator #( |
||||
|
parameter REG_START_ADD = 0, |
||||
|
parameter SYS_CLOCK_FREQ = 10000000, |
||||
|
parameter TEST = 0 |
||||
|
) ( |
||||
|
input clk, |
||||
|
input rst_n, |
||||
|
|
||||
|
input [31:0] addr, |
||||
|
input [31:0] wr_data, |
||||
|
input wr_en, |
||||
|
output wire [31:0] rd_data, |
||||
|
|
||||
|
input wire ttlin1_sig, |
||||
|
input wire ttlin2_sig, |
||||
|
input wire ttlin3_sig, |
||||
|
input wire ttlin4_sig, |
||||
|
|
||||
|
input wire frame_freq_sig, |
||||
|
input wire sys_timecode_tigger_sig, |
||||
|
input wire [63:0] sys_timecode_data, |
||||
|
|
||||
|
output reg out_record_en_sig, //!录制使能信号 |
||||
|
output reg out_record_exposure_sig //!录制曝光信号 |
||||
|
|
||||
|
); |
||||
|
|
||||
|
|
||||
|
|
||||
|
reg [31:0] reg1_ctrl_control_mode; //! 控制模式选择寄存器 |
||||
|
|
||||
|
reg [31:0] reg2_timecode_start0; //! 时码启动寄存器0 |
||||
|
reg [31:0] reg3_timecode_start1; //! 时码启动寄存器1 |
||||
|
reg [31:0] reg4_timecode_stop0; //! 时码停止寄存器0 |
||||
|
reg [31:0] reg5_timecode_stop1; //! 时码停止寄存器1 |
||||
|
reg [31:0] reg6_timecode_control_flag; //! 使能时码控制启动，使能使能时码控制停止 |
||||
|
|
||||
|
reg [31:0] reg7_ttlin_trigger_sig_source; //! TTL触发信号选择 |
||||
|
reg [31:0] reg8_ttlin_trigger_level; //! TTL输入信号极性反转 |
||||
|
|
||||
|
reg [31:0] reg9_exposure_time; //! 曝光时长 |
||||
|
reg [31:0] regA_exposure_delay; //! 曝光信号延迟 |
||||
|
|
||||
|
reg [31:0] regB_manual_ctrl; //! 手动控制 |
||||
|
localparam REGA_MANUAL_CTRL_REG_INDEX = 32'd11; |
||||
|
|
||||
|
reg [31:0] regD_start_timecode_snapshot0; //! |
||||
|
reg [31:0] regE_start_timecode_snapshot1; //! |
||||
|
reg [31:0] regF_record_state; //!工作状态 read only |
||||
|
|
||||
|
wire [31:0] reg_wr_index; |
||||
|
|
||||
|
zutils_register_advanced #( |
||||
|
.REG_START_ADD(REG_START_ADD) |
||||
|
) _register ( |
||||
|
.clk (clk), |
||||
|
.rst_n (rst_n), |
||||
|
.addr (addr), |
||||
|
.wr_data(wr_data), |
||||
|
.wr_en (wr_en), |
||||
|
.rd_data(rd_data), |
||||
|
|
||||
|
.reg1(reg1_ctrl_control_mode), |
||||
|
.reg2(reg2_timecode_start0), |
||||
|
.reg3(reg3_timecode_start1), |
||||
|
.reg4(reg4_timecode_stop0), |
||||
|
.reg5(reg5_timecode_stop1), |
||||
|
.reg6(reg6_timecode_control_flag), |
||||
|
.reg7(reg7_ttlin_trigger_sig_source), |
||||
|
.reg8(reg8_ttlin_trigger_level), |
||||
|
.reg9(reg9_exposure_time), |
||||
|
.regA(regA_exposure_delay), |
||||
|
|
||||
|
.regB(regB_manual_ctrl), |
||||
|
.regD(regD_start_timecode_snapshot0), |
||||
|
.regE(regE_start_timecode_snapshot1), |
||||
|
.regF(regF_record_state), |
||||
|
|
||||
|
.reg_wr_sig(reg_wr_sig), |
||||
|
.reg_index (reg_wr_index) |
||||
|
); |
||||
|
|
||||
|
always @(posedge clk or negedge rst_n) begin |
||||
|
if (!rst_n) begin |
||||
|
reg1_ctrl_control_mode <= 1; |
||||
|
reg2_timecode_start0 <= 0; |
||||
|
reg3_timecode_start1 <= 0; |
||||
|
reg4_timecode_stop0 <= 0; |
||||
|
reg5_timecode_stop1 <= 0; |
||||
|
reg6_timecode_control_flag <= 32'hFFFF_FFFF; |
||||
|
reg7_ttlin_trigger_sig_source <= 1; |
||||
|
reg8_ttlin_trigger_level <= 1; |
||||
|
reg9_exposure_time <= 32'd1000; //100us |
||||
|
regA_exposure_delay <= 0; |
||||
|
regB_manual_ctrl <= 0; |
||||
|
end else begin |
||||
|
if (reg_wr_sig) begin |
||||
|
case (reg_wr_index) |
||||
|
1: reg1_ctrl_control_mode <= wr_data; |
||||
|
2: reg2_timecode_start0 <= wr_data; |
||||
|
3: reg3_timecode_start1 <= wr_data; |
||||
|
4: reg4_timecode_stop0 <= wr_data; |
||||
|
5: reg5_timecode_stop1 <= wr_data; |
||||
|
6: reg6_timecode_control_flag <= wr_data; |
||||
|
7: reg7_ttlin_trigger_sig_source <= wr_data; |
||||
|
8: reg8_ttlin_trigger_level <= wr_data; |
||||
|
9: reg9_exposure_time <= wr_data; |
||||
|
10: regA_exposure_delay <= wr_data; |
||||
|
default: begin |
||||
|
end |
||||
|
endcase |
||||
|
end |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
|
||||
|
wire ttl_in_choose; //! 选中的ttl触发信号，(已经经过电平翻转) |
||||
|
wire timecode_start_trigger_sig; //!timecode启动信号 |
||||
|
wire timecode_stop_trigger_sig; //!timecode停止信号 |
||||
|
wire record_exposure_sig; //!曝光信号 |
||||
|
wire frame_freq_sig_rising_edge; |
||||
|
|
||||
|
|
||||
|
zutils_multiplexer_32t1_v2 ttlin_level_trigger_multi ( |
||||
|
.chooseindex(reg7_ttlin_trigger_sig_source), |
||||
|
//in |
||||
|
.in1 (ttlin1_sig ^ (!reg8_ttlin_trigger_level[0])), |
||||
|
.in2 (ttlin2_sig ^ (!reg8_ttlin_trigger_level[0])), |
||||
|
.in3 (ttlin3_sig ^ (!reg8_ttlin_trigger_level[0])), |
||||
|
.in4 (ttlin4_sig ^ (!reg8_ttlin_trigger_level[0])), |
||||
|
//out |
||||
|
.out (ttl_in_choose) |
||||
|
); |
||||
|
|
||||
|
/******************************************************************************* |
||||
|
* StartSig输出 * |
||||
|
*******************************************************************************/ |
||||
|
|
||||
|
timecode_comparator timecode_comparator_inst0 ( |
||||
|
.timecodeA0(sys_timecode_data[31:0]), |
||||
|
.timecodeA1(sys_timecode_data[63:32]), |
||||
|
.timecodeB0(reg2_timecode_start0), |
||||
|
.timecodeB1(reg3_timecode_start1), |
||||
|
.eq (timecode_start_trigger_sig) |
||||
|
); |
||||
|
|
||||
|
timecode_comparator timecode_comparator_inst1 ( |
||||
|
.timecodeA0(sys_timecode_data[31:0]), |
||||
|
.timecodeA1(sys_timecode_data[63:32]), |
||||
|
.timecodeB0(reg4_timecode_stop0), |
||||
|
.timecodeB1(reg5_timecode_stop1), |
||||
|
.eq (timecode_stop_trigger_sig) |
||||
|
); |
||||
|
|
||||
|
|
||||
|
zutils_edge_detecter _signal_in ( |
||||
|
.clk (clk), |
||||
|
.rst_n (rst_n), |
||||
|
.in_signal (frame_freq_sig), |
||||
|
.in_signal_rising_edge(frame_freq_sig_rising_edge) |
||||
|
); |
||||
|
|
||||
|
zutils_pluse_generator _pluse_generator ( |
||||
|
.clk (clk), |
||||
|
.rst_n (rst_n), |
||||
|
.pluse_width (reg9_exposure_time), |
||||
|
.pluse_delay (regA_exposure_delay), |
||||
|
.trigger (frame_freq_sig_rising_edge), |
||||
|
.output_signal(record_exposure_sig) |
||||
|
); |
||||
|
|
||||
|
reg en_state; |
||||
|
always @(posedge clk or negedge rst_n) begin |
||||
|
if (!rst_n) begin |
||||
|
en_state <= 0; |
||||
|
end else begin |
||||
|
case (reg1_ctrl_control_mode) |
||||
|
1: begin |
||||
|
//手动控制触发启动停止 |
||||
|
if (reg_wr_sig && reg_wr_index == REGA_MANUAL_CTRL_REG_INDEX) begin |
||||
|
if (wr_data[0] == 1) begin |
||||
|
en_state <= 1; |
||||
|
end else begin |
||||
|
en_state <= 0; |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
end |
||||
|
2: begin |
||||
|
//TIMECODE控制启动 |
||||
|
if (timecode_start_trigger_sig && sys_timecode_tigger_sig && reg6_timecode_control_flag[0]) begin |
||||
|
en_state <= 1; |
||||
|
end else if (timecode_stop_trigger_sig && sys_timecode_tigger_sig && reg6_timecode_control_flag[1]) begin |
||||
|
en_state <= 0; |
||||
|
end else if (reg_wr_sig && reg_wr_index == REGA_MANUAL_CTRL_REG_INDEX) begin |
||||
|
if (wr_data[0] == 1) begin |
||||
|
en_state <= 1; |
||||
|
end else begin |
||||
|
en_state <= 0; |
||||
|
end |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
3: begin |
||||
|
//外部电平控制 |
||||
|
if (ttl_in_choose == 1) begin |
||||
|
en_state <= 1; |
||||
|
end else begin |
||||
|
en_state <= 0; |
||||
|
end |
||||
|
end |
||||
|
default: begin |
||||
|
end |
||||
|
endcase |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
|
||||
|
reg en_state_af_sync; |
||||
|
always @(posedge clk or negedge rst_n) begin |
||||
|
if (!rst_n) begin |
||||
|
en_state_af_sync <= 0; |
||||
|
end else begin |
||||
|
case (en_state) |
||||
|
0: begin |
||||
|
if (en_state_af_sync != en_state) begin |
||||
|
en_state_af_sync <= 0; |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
1: begin |
||||
|
if (en_state_af_sync == 0) begin |
||||
|
if (frame_freq_sig_rising_edge) begin |
||||
|
regD_start_timecode_snapshot0 <= sys_timecode_data[31:0]; |
||||
|
regE_start_timecode_snapshot1 <= sys_timecode_data[63:32]; |
||||
|
en_state_af_sync <= 1; |
||||
|
end |
||||
|
end |
||||
|
end |
||||
|
endcase |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
|
||||
|
always @(*) begin |
||||
|
regF_record_state[0] <= en_state_af_sync; |
||||
|
out_record_en_sig <= en_state_af_sync; |
||||
|
out_record_exposure_sig <= out_record_en_sig & record_exposure_sig; |
||||
|
end |
||||
|
|
||||
|
endmodule |
||||
Write
Preview
Loading…
Cancel
Save
Reference in new issue