forked from p_lusterinc_xsync/xsync_fpge
4 changed files with 327 additions and 73 deletions
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96led_test.pds
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251source/src/business/record_sig_generator.v
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4source/src/output/camera_sync_signal_output.v
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49source/src/top.v
@ -0,0 +1,251 @@ |
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module record_sig_generator #( |
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parameter REG_START_ADD = 0, |
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parameter SYS_CLOCK_FREQ = 10000000, |
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parameter TEST = 0 |
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) ( |
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input clk, |
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input rst_n, |
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|
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input [31:0] addr, |
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input [31:0] wr_data, |
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input wr_en, |
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output wire [31:0] rd_data, |
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|
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input wire ttlin1_sig, |
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input wire ttlin2_sig, |
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input wire ttlin3_sig, |
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input wire ttlin4_sig, |
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|
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input wire frame_freq_sig, |
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input wire sys_timecode_tigger_sig, |
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input wire [63:0] sys_timecode_data, |
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|
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output reg out_record_en_sig, //!录制使能信号 |
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output reg out_record_exposure_sig //!录制曝光信号 |
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); |
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|
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reg [31:0] reg1_ctrl_control_mode; //! 控制模式选择寄存器 |
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reg [31:0] reg2_timecode_start0; //! 时码启动寄存器0 |
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reg [31:0] reg3_timecode_start1; //! 时码启动寄存器1 |
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reg [31:0] reg4_timecode_stop0; //! 时码停止寄存器0 |
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reg [31:0] reg5_timecode_stop1; //! 时码停止寄存器1 |
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reg [31:0] reg6_timecode_control_flag; //! 使能时码控制启动，使能使能时码控制停止 |
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|
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reg [31:0] reg7_ttlin_trigger_sig_source; //! TTL触发信号选择 |
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reg [31:0] reg8_ttlin_trigger_level; //! TTL输入信号极性反转 |
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|
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reg [31:0] reg9_exposure_time; //! 曝光时长 |
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reg [31:0] regA_exposure_delay; //! 曝光信号延迟 |
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|
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reg [31:0] regB_manual_ctrl; //! 手动控制 |
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localparam REGA_MANUAL_CTRL_REG_INDEX = 32'd11; |
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|
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reg [31:0] regD_start_timecode_snapshot0; //! |
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reg [31:0] regE_start_timecode_snapshot1; //! |
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reg [31:0] regF_record_state; //!工作状态 read only |
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|
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wire [31:0] reg_wr_index; |
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|
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zutils_register_advanced #( |
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.REG_START_ADD(REG_START_ADD) |
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) _register ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.addr (addr), |
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.wr_data(wr_data), |
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.wr_en (wr_en), |
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.rd_data(rd_data), |
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|
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.reg1(reg1_ctrl_control_mode), |
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.reg2(reg2_timecode_start0), |
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.reg3(reg3_timecode_start1), |
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.reg4(reg4_timecode_stop0), |
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.reg5(reg5_timecode_stop1), |
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.reg6(reg6_timecode_control_flag), |
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.reg7(reg7_ttlin_trigger_sig_source), |
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.reg8(reg8_ttlin_trigger_level), |
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.reg9(reg9_exposure_time), |
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.regA(regA_exposure_delay), |
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|
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.regB(regB_manual_ctrl), |
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.regD(regD_start_timecode_snapshot0), |
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.regE(regE_start_timecode_snapshot1), |
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.regF(regF_record_state), |
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|
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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); |
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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reg1_ctrl_control_mode <= 1; |
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reg2_timecode_start0 <= 0; |
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reg3_timecode_start1 <= 0; |
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reg4_timecode_stop0 <= 0; |
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reg5_timecode_stop1 <= 0; |
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reg6_timecode_control_flag <= 32'hFFFF_FFFF; |
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reg7_ttlin_trigger_sig_source <= 1; |
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reg8_ttlin_trigger_level <= 1; |
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reg9_exposure_time <= 32'd1000; //100us |
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regA_exposure_delay <= 0; |
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regB_manual_ctrl <= 0; |
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end else begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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1: reg1_ctrl_control_mode <= wr_data; |
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2: reg2_timecode_start0 <= wr_data; |
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3: reg3_timecode_start1 <= wr_data; |
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4: reg4_timecode_stop0 <= wr_data; |
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5: reg5_timecode_stop1 <= wr_data; |
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6: reg6_timecode_control_flag <= wr_data; |
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7: reg7_ttlin_trigger_sig_source <= wr_data; |
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8: reg8_ttlin_trigger_level <= wr_data; |
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9: reg9_exposure_time <= wr_data; |
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10: regA_exposure_delay <= wr_data; |
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default: begin |
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end |
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endcase |
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end |
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end |
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end |
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|
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|
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wire ttl_in_choose; //! 选中的ttl触发信号，(已经经过电平翻转) |
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wire timecode_start_trigger_sig; //!timecode启动信号 |
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wire timecode_stop_trigger_sig; //!timecode停止信号 |
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wire record_exposure_sig; //!曝光信号 |
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wire frame_freq_sig_rising_edge; |
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|
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|
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zutils_multiplexer_32t1_v2 ttlin_level_trigger_multi ( |
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.chooseindex(reg7_ttlin_trigger_sig_source), |
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//in |
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.in1 (ttlin1_sig ^ (!reg8_ttlin_trigger_level[0])), |
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.in2 (ttlin2_sig ^ (!reg8_ttlin_trigger_level[0])), |
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.in3 (ttlin3_sig ^ (!reg8_ttlin_trigger_level[0])), |
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.in4 (ttlin4_sig ^ (!reg8_ttlin_trigger_level[0])), |
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//out |
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.out (ttl_in_choose) |
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); |
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|
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/******************************************************************************* |
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* StartSig输出 * |
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*******************************************************************************/ |
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|
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timecode_comparator timecode_comparator_inst0 ( |
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.timecodeA0(sys_timecode_data[31:0]), |
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.timecodeA1(sys_timecode_data[63:32]), |
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.timecodeB0(reg2_timecode_start0), |
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.timecodeB1(reg3_timecode_start1), |
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.eq (timecode_start_trigger_sig) |
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); |
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|
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timecode_comparator timecode_comparator_inst1 ( |
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.timecodeA0(sys_timecode_data[31:0]), |
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.timecodeA1(sys_timecode_data[63:32]), |
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.timecodeB0(reg4_timecode_stop0), |
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.timecodeB1(reg5_timecode_stop1), |
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.eq (timecode_stop_trigger_sig) |
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); |
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|
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|
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zutils_edge_detecter _signal_in ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.in_signal (frame_freq_sig), |
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.in_signal_rising_edge(frame_freq_sig_rising_edge) |
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); |
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|
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zutils_pluse_generator _pluse_generator ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.pluse_width (reg9_exposure_time), |
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.pluse_delay (regA_exposure_delay), |
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.trigger (frame_freq_sig_rising_edge), |
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.output_signal(record_exposure_sig) |
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); |
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|
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reg en_state; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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en_state <= 0; |
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end else begin |
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case (reg1_ctrl_control_mode) |
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1: begin |
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//手动控制触发启动停止 |
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if (reg_wr_sig && reg_wr_index == REGA_MANUAL_CTRL_REG_INDEX) begin |
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if (wr_data[0] == 1) begin |
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en_state <= 1; |
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end else begin |
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en_state <= 0; |
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end |
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end |
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|
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end |
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2: begin |
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//TIMECODE控制启动 |
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if (timecode_start_trigger_sig && sys_timecode_tigger_sig && reg6_timecode_control_flag[0]) begin |
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en_state <= 1; |
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end else if (timecode_stop_trigger_sig && sys_timecode_tigger_sig && reg6_timecode_control_flag[1]) begin |
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en_state <= 0; |
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end else if (reg_wr_sig && reg_wr_index == REGA_MANUAL_CTRL_REG_INDEX) begin |
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if (wr_data[0] == 1) begin |
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en_state <= 1; |
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end else begin |
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en_state <= 0; |
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end |
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end |
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end |
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3: begin |
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//外部电平控制 |
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if (ttl_in_choose == 1) begin |
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en_state <= 1; |
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end else begin |
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en_state <= 0; |
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end |
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end |
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default: begin |
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end |
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endcase |
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end |
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end |
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reg en_state_af_sync; |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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en_state_af_sync <= 0; |
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end else begin |
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case (en_state) |
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0: begin |
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if (en_state_af_sync != en_state) begin |
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en_state_af_sync <= 0; |
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end |
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end |
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1: begin |
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if (en_state_af_sync == 0) begin |
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if (frame_freq_sig_rising_edge) begin |
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regD_start_timecode_snapshot0 <= sys_timecode_data[31:0]; |
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regE_start_timecode_snapshot1 <= sys_timecode_data[63:32]; |
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en_state_af_sync <= 1; |
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end |
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end |
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end |
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endcase |
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end |
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end |
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always @(*) begin |
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regF_record_state[0] <= en_state_af_sync; |
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out_record_en_sig <= en_state_af_sync; |
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out_record_exposure_sig <= out_record_en_sig & record_exposure_sig; |
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end |
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|
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endmodule |
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