`timescale 10ns / 10ns
module test_top;
  reg  sys_clk;
  reg  rst_n;

  wire core_board_debug_led;

  reg  spi1_cs_pin;
  reg  spi1_clk_pin;
  reg  spi1_tx_pin;
  wire spi1_rx_pin;

  initial begin
    spi1_cs_pin  = 1;
    spi1_clk_pin = 1;
    spi1_tx_pin  = 1;
  end


  task spi_write_reg;

    input [15:0] addr;
    input [31:0] data;
    integer i;
    spi1_cs_pin = 0;
    #10;  // 100ns
   
    for ( i = 0; i <= 48; i=i+1) begin
      spi1_clk_pin = 0;
      if (i <= 15) spi1_tx_pin = addr[i];
      else spi1_tx_pin = data[i-16];
      #10;
      spi1_clk_pin = 1;
      #10;
    end
    #10
    spi1_cs_pin = 1;

  endtask


  Top top_impl (
      .sys_clk(sys_clk),
      .rst_n(rst_n),
      .core_board_debug_led(core_board_debug_led),

      .spi1_cs_pin (spi1_cs_pin),
      .spi1_clk_pin(spi1_clk_pin),
      .spi1_rx_pin (spi1_tx_pin),
      .spi1_tx_pin (spi1_rx_pin)

  );




  initial begin
    sys_clk = 0;
    rst_n   = 0;

    #100;
    rst_n = 1;

    #100;
    // spi_write_reg(16'h0020, 32'h00000000);

  end
  always #1 sys_clk = ~sys_clk;  // 50MHZ时钟
endmodule