forked from p_lusterinc_xsync/xsync_fpge
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zhaohe
e87a363a9b
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9 months ago | |
|---|---|---|
| .vscode | 11 months ago | |
| ip_backup/20240321095414/ShiftRegister | 1 year ago | |
| ipcore | 11 months ago | |
| pango_tools | 11 months ago | |
| release | 9 months ago | |
| source | 9 months ago | |
| .gitignore | 10 months ago | |
| ACPGL22G核心板原理图.pdf | 2 years ago | |
| README.md | 9 months ago | |
| cfg_verify_result.sbit | 1 year ago | |
| csv2fdc.exe | 11 months ago | |
| data.wf | 2 years ago | |
| fdc2csv.exe | 11 months ago | |
| msg_level.txt | 11 months ago | |
| pin.md | 2 years ago | |
| rdfile_2024_3_26_21_12_43 | 1 year ago | |
| xsync.csv | 11 months ago | |
| xsync.fdc | 10 months ago | |
| xsync.pds | 9 months ago | |
README.md
https://iflytop1.feishu.cn/docx/Fk3CdIRNZoal1XxCGgjc9q1Dn1f
固化
https://iflytop1.feishu.cn/wiki/DyHLwd2pLicjXxkWNEvc7vI7n2b
cfg_gen_sfc -device_name W25Q128Q -opcode 107 -sbit_start_address 0 -sbit ./generate_bitstream/Top.sbit
注意事项:
倍频和分频的前提建立在输入频率稳定的情况才有效的。如果输入频率在+-一定范围内变化，输出波形可能会出现异常
插件:
Documenter - TerosHDL 0.1.4 documentation
Verilog-HDL/SystemVerilog/Bluespec SystemVerilog
v0.0.0.4
1. 修复timecode启动时前两帧重复的问题
2. 修复timecode输出时候子帧出现00的情况
v1.0.5
1. 修复timecode识别出错的BUG(为什么能修复不知道)
2. 优化系统总线相关代码
v1.0.6
1. 开机默认timecode不启动
v1.0.7
1.失能掉系统延迟延时功能模块
BUG:
系统延时功能模块的BUG
1. 输入信号没有经过滤波就给了延迟模块，延迟模块处理不了这种信号
2. 延迟模块只能延后一个脉冲信号