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(_flow fab_demo "2022.2-SP4.2"
(_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Tue Nov 5 14:21:01 2024")
(_version "1.1.0")
(_status "initial")
(_project
(_option prj_work_dir (_string "."))
(_option prj_impl_dir (_string "."))
)
(_task tsk_setup
(_widget wgt_select_arch
(_input
(_part
(_family Logos2)
(_device PG2L100H)
(_speedgrade -6)
(_package FBG484)
)
)
)
(_widget wgt_my_design_src
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-11-03T14:04:29")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_pluse_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_edge_detecter.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_register.v"
(_format verilog)
(_timespec "2024-11-01T19:28:46")
)
(_file "source/src/zutils/zutils_multiplexer_4t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_debug_led.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_signal_filter.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_clk_parser.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_multiplexer_16t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/output/ttl_output.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_pwm_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_reset_sig_gen.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_multiplexer_2t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_multiplexer_32t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_muti_debug_signal_gen.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_pwm_generator_advanced.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_register_advanced.v"
(_format verilog)
(_timespec "2024-11-01T18:58:01")
)
(_file "source/src/zutils/zutils_genlock_clk_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_multiplexer_32t1_v2.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/ztutils_timecode_next_code.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_smpte_timecode_clk_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/timecode/timecode_nextcode.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/timecode/timecode_basesig_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/timecode/timecode_serialization.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/timecode/timecode_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/output/timecode_output.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/input/timecode_input.v"
(_format verilog)
(_timespec "2024-11-05T14:09:39")
)
(_file "source/src/timecode/timecode_decoder.v"
(_format verilog)
(_timespec "2024-11-03T13:58:51")
)
(_file "source/src/timecode/timecode_sample_sig_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/input/ttl_input.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/ztuils_sig_devide.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_signal_filter_advance.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/timecode/timecode_comparator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_freq_detector.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zsimple_pll.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_freq_detector_v2.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_multiplexer_8t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/spi_reg_bus.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/internal/internal_timecode_generator.v"
(_format verilog)
(_timespec "2024-11-03T13:12:31")
)
(_file "source/src/sys/sys_timecode.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/input/genlock_input_module.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/internal/internal_clock_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/internal/internal_genlock_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/sys/sys_genlock.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/sys/sys_clock.v"
(_format verilog)
(_timespec "2024-10-28T20:46:00")
)
(_file "source/src/output/camera_sync_signal_output.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/business/record_sig_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/sys_signal_delayer.v"
(_format verilog)
(_timespec "2024-11-05T13:28:30")
)
(_file "source/src/zutils/zutils_sig_delayer.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_sig_delayer_v2.v"
(_format verilog)
(_timespec "2024-08-23T15:51:36")
)
(_file "source/src/zutils/zutils_pluse_delayer.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/internal/internal_sig_generator_en_contrler.v"
(_format verilog)
(_timespec "2024-11-05T13:17:59")
)
(_file "source/src/zutils/zutils_timer.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/breathing_lamp.v"
(_format verilog)
(_timespec "2024-08-28T18:42:17")
)
(_file "source/src/app_top.v"
(_format verilog)
(_timespec "2024-11-05T13:28:44")
)
(_file "source/src/timecode/timecode_freq_detector.v"
(_format verilog)
(_timespec "2024-11-02T18:41:12")
)
)
)
(_widget wgt_my_ips_src
(_input
(_ip "ipcore/ShiftRegister/ShiftRegister.idf"
(_timespec "2024-08-23T13:36:15")
(_ip_source_item "ipcore/ShiftRegister/rtl/ipm_distributed_sdpram_v1_2_ShiftRegister.v"
(_timespec "2024-08-23T13:36:15")
)
(_ip_source_item "ipcore/ShiftRegister/rtl/ipm_distributed_shiftregister_v1_2_ShiftRegister.v"
(_timespec "2024-08-23T13:36:15")
)
(_ip_source_item "ipcore/ShiftRegister/ShiftRegister.v"
(_timespec "2024-08-23T13:36:15")
)
)
(_ip "ipcore/SPLL/SPLL.idf"
(_timespec "2024-08-28T18:24:17")
(_ip_source_item "ipcore/SPLL/SPLL.v"
(_timespec "2024-08-28T18:24:17")
)
)
)
)
(_widget wgt_import_logic_con_file
(_input
(_file "xsync.fdc"
(_format fdc)
(_timespec "2024-10-28T20:46:00")
)
)
)
(_widget wgt_edit_user_cons
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_simulation
(_option compiled_lib_location (_string "pango_sim_libraries"))
(_option verilog_options (_string ""))
(_option gen_param (_string ""))
(_option simulate_runtime (_string "10000ms"))
(_option sim_exe_dir (_string "C:/modeltech64_10.5/win64"))
(_input
(_file "source/test/test_transmitter.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_baud_rate_gen.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_top.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_uart_reg_reader.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_spi_reg_reader.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_timecode_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_timecode_decoder.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_app_top.v" + "test_app_top:"
(_format verilog)
(_timespec "2024-11-01T21:02:30")
)
(_file "source/test/test_timecode_input_and_output.v"
(_format verilog)
(_timespec "2024-11-02T10:40:37")
)
)
)
)
(_task tsk_compile
(_command cmd_compile
(_gci_state (_integer 2))
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-11-05T14:10:07")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-11-05T14:10:07")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-11-05T14:10:07")
)
)
)
(_widget wgt_rtl_view
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 2))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-11-05T14:12:40")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-11-05T14:12:53")
)
(_file "synthesize/Top_controlsets.txt"
(_format text)
(_timespec "2024-11-05T14:12:29")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-11-05T14:13:00")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-11-05T14:13:00")
)
)
)
(_widget wgt_tech_view
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_map_constraint
)
(_widget wgt_my_fic_src
)
(_widget wgt_inserter_gui_view
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 2))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-11-05T14:13:51")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-11-05T14:13:29")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-11-05T14:13:52")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-11-05T14:13:52")
)
)
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/xsync.pcf"
(_format pcf)
(_timespec "2024-11-05T14:13:51")
)
)
)
(_widget wgt_edit_route_cons
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 2))
(_option gplace_seed (_integer 8))
(_option seed_step (_integer 4))
(_option saved_outcome (_integer 4))
(_option parallel (_integer 4))
(_option share_router_control_signal (_boolean FALSE))
(_option check_clk_net_route_by_srb (_boolean FALSE))
(_option fix_hold_violation_in_route (_boolean FALSE))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-11-05T14:20:38")
)
)
(_output
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-11-05T14:20:01")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-11-05T14:17:17")
)
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-11-05T14:20:39")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-11-05T14:20:01")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-11-05T14:20:38")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-11-05T14:20:39")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_timing_analysis
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_power
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
(_command cmd_gen_netlist
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 2))
(_option unused_io_status (_string "KEEPER"))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-11-05T14:21:00")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-11-05T14:21:00")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-11-05T14:21:01")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-11-05T14:21:01")
)
)
)
)
)