forked from p_lusterinc_xsync/xsync_fpge
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69 lines
1.1 KiB
69 lines
1.1 KiB
`timescale 10ns / 10ns
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module test_top;
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reg sys_clk;
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reg rst_n;
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wire core_board_debug_led;
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reg spi1_cs_pin;
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reg spi1_clk_pin;
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reg spi1_tx_pin;
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wire spi1_rx_pin;
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initial begin
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spi1_cs_pin = 1;
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spi1_clk_pin = 1;
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spi1_tx_pin = 1;
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end
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task spi_write_reg;
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input [15:0] addr;
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input [31:0] data;
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integer i;
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spi1_cs_pin = 0;
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#10; // 100ns
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for ( i = 0; i <= 48; i=i+1) begin
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spi1_clk_pin = 0;
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if (i <= 15) spi1_tx_pin = addr[i];
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else spi1_tx_pin = data[i-16];
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#10;
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spi1_clk_pin = 1;
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#10;
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end
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#10
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spi1_cs_pin = 1;
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endtask
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Top top_impl (
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.sys_clk(sys_clk),
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.rst_n(rst_n),
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.core_board_debug_led(core_board_debug_led),
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.spi1_cs_pin (spi1_cs_pin),
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.spi1_clk_pin(spi1_clk_pin),
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.spi1_rx_pin (spi1_tx_pin),
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.spi1_tx_pin (spi1_rx_pin)
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);
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initial begin
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sys_clk = 0;
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rst_n = 0;
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#100;
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rst_n = 1;
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#100;
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// spi_write_reg(16'h0020, 32'h00000000);
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end
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always #1 sys_clk = ~sys_clk; // 50MHZ时钟
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endmodule
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