forked from p_lusterinc_xsync/xsync_fpge
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304 lines
9.9 KiB
304 lines
9.9 KiB
`include "config.v"
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`timescale 1ns / 1ns
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module Top (
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input sys_clk,
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input rst_n,
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/*******************************************************************************
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* genlock *
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*******************************************************************************/
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input genlock_in_hsync,
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input genlock_in_vsync,
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input genlock_in_fsync,
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output genlock_state_led,
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/*******************************************************************************
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* GENLOCK_OUTPUT *
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*******************************************************************************/
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output [12:0] genlock_out_dac,
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output genlock_out_dac_state_led,
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/*******************************************************************************
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* TTL_IN *
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*******************************************************************************/
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input sync_ttl_in1,
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output sync_ttl_state_led1,
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input sync_ttl_in2,
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output sync_ttl_state_led2,
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input sync_ttl_in3,
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output sync_ttl_state_led3,
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input sync_ttl_in4,
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output sync_ttl_state_led4,
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/*******************************************************************************
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* TTL_OUT *
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*******************************************************************************/
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output sync_ttl_out1,
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output sync_ttl_out1_state_led,
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output sync_ttl_out2,
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output sync_ttl_out2_state_led,
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output sync_ttl_out3,
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output sync_ttl_out3_state_led,
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output sync_ttl_out4,
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output sync_ttl_out4_state_led,
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/*******************************************************************************
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* TIMECODE_IN *
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*******************************************************************************/
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input timecode_headphone_in,
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input timecode_headphone_in_state_led,
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input timecode_bnc_in,
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input timecode_bnc_in_state_led,
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/*******************************************************************************
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* TIMECODE_OUTPUT *
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*******************************************************************************/
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output timecode_bnc_out,
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output timecode_bnc_output_select,
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output timecode_bnc_out_state_led,
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output timecode_headphone_out,
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output timecode_headphone_output_select,
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output timecode_headphone_out_state_led,
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/*******************************************************************************
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* STM32_IF *
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*******************************************************************************/
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output stm32if_camera_sync_out,
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output stm32if_timecode_sync_out,
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output stm32if_start_signal_out,
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output [3:0] stm32if_timecode_add,
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output [3:0] stm32if_timecode_data,
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//SPI 串行总线1
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input wire spi1_cs_pin,
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input wire spi1_clk_pin,
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input wire spi1_rx_pin,
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output wire spi1_tx_pin,
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//SPI 串行总线2
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input wire spi2_cs_pin,
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input wire spi2_clk_pin,
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input wire spi2_rx_pin,
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output wire spi2_tx_pin,
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/*******************************************************************************
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* debug_signal_output *
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*******************************************************************************/
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output [15:0] debug_signal_output,
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/*******************************************************************************
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* CODE_BOARD *
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*******************************************************************************/
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output wire core_board_debug_led
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);
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localparam HARDWARE_TEST_MODE = 1;
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SPLL spll (
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.clkin1(sys_clk), // input
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.pll_lock(pll_lock), // output
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.clkout0(sys_clk_25m), // output
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.clkout1(sys_clk_10m), // output
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.clkout2(sys_clk_5m) // output
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);
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/*******************************************************************************
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* 调试器 *
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*******************************************************************************/
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// wire [6:0] trig0_i;
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// JtagHubIst jtag_hub_ist (
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// .resetn_i(rst_n), // input
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// .drck_o (drck_o), // output
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// .hub_tdi (hub_tdi), // output
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// .capt_o (capt_o), // output
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// .shift_o (shift_o), // output
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// .conf_sel(conf_sel), // output [14:0]
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// .id_o (id_o), // output [4:0]
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// .hub_tdo (hub_tdo) // input [14:0]
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// );
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// DebugCoreIst debug_core_ist (
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// .hub_tdi (hub_tdi), // input
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// .hub_tdo (hub_tdo[0]), // output
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// .id_i (id_o), // input [4:0]
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// .capt_i (capt_o), // input
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// .shift_i (shift_o), // input
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// .conf_sel(conf_sel[0]), // input
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// .drck_in (drck_o), // input
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// .clk (sys_clk), // input
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// .resetn_i(rst_n), // input
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// .trig0_i (trig0_i)
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// );
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/*******************************************************************************
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* DEBUG_LED *
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*******************************************************************************/
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zutils_debug_led #(
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.PERIOD_COUNT(10000000)
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) core_board_debug_led_inst (
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.clk(sys_clk),
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.rst_n(rst_n),
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.debug_led(core_board_debug_led)
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);
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/*******************************************************************************
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* SPIREADER *
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*******************************************************************************/
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wire [31:0] reg_reader_bus_addr;
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wire [31:0] reg_reader_bus_wr_data;
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wire reg_reader_bus_wr_en;
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wire [31:0] reg_reader_bus_rd_data;
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spi_reg_reader spi1_reg_reader_inst (
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.clk (sys_clk),
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.rst_n(rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(reg_reader_bus_rd_data),
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//
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.spi_cs_pin(spi1_cs_pin),
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.spi_clk_pin(spi1_clk_pin),
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.spi_rx_pin(spi1_rx_pin),
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.spi_tx_pin(spi1_tx_pin)
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);
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rd_data_router rd_data_router_inst (
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.addr(reg_reader_bus_addr),
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.stm32_rd_data(0),
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.fpga_test_rd_data(fpga_test_rd_data),
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.control_sensor_rd_data(control_sensor_rd_data),
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.ttlin1_rd_data(ttlin1_rd_data),
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.ttlin2_rd_data(ttlin2_rd_data),
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.ttlin3_rd_data(ttlin3_rd_data),
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.ttlin4_rd_data(ttlin4_rd_data),
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.timecode_in_rd_data(timecode_in_rd_data),
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.genlock_in_rd_data(genlock_in_rd_data),
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.ttlout1_rd_data(ttlout1_rd_data), // ok
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.ttlout2_rd_data(ttlout2_rd_data), // ok
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.ttlout3_rd_data(ttlout3_rd_data), // ok
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.ttlout4_rd_data(ttlout4_rd_data), // ok
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.timecode_out_rd_data(timecode_out_rd_data),
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.genlock_out_rd_data(genlock_out_rd_data),
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.stm32_if_rd_data(stm32_if_rd_data),
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.debuger_rd_data(debuger_rd_data),
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.rd_data_out(reg_reader_bus_rd_data)
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);
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/*******************************************************************************
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* TEST_SPI_REG *
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*******************************************************************************/
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zutils_register16 #(
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.REG_START_ADD(`REG_ADD_OFF_FPGA_TEST)
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) core_board_debug_led_reg (
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.clk(sys_clk),
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.rst_n(rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(fpga_test_rd_data)
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);
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/*******************************************************************************
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* 输出组件 *
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*******************************************************************************/
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wire [7:0] ttl_output_signal_in;
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ttl_output #(
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.REG_START_ADD(`REG_ADD_OFF_TTLIN1),
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.TEST(HARDWARE_TEST_MODE)
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) ttl_output_1 (
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.clk (sys_clk),
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.rst_n(rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(ttlout1_rd_data),
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.signal_in(ttl_output_signal_in),
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.ttloutput(sync_ttl_out1),
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.ttloutput_state_led(sync_ttl_out1_state_led)
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);
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ttl_output #(
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.REG_START_ADD(`REG_ADD_OFF_TTLIN2),
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.TEST(HARDWARE_TEST_MODE)
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) ttl_output_2 (
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.clk (sys_clk),
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.rst_n(rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(ttlout2_rd_data),
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.signal_in(ttl_output_signal_in),
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.ttloutput(sync_ttl_out2),
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.ttloutput_state_led(sync_ttl_out2_state_led)
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);
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ttl_output #(
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.REG_START_ADD(`REG_ADD_OFF_TTLIN3),
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.TEST(HARDWARE_TEST_MODE)
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) ttl_output_3 (
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.clk (sys_clk),
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.rst_n(rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(ttlout3_rd_data),
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.signal_in(ttl_output_signal_in),
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.ttloutput(sync_ttl_out3),
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.ttloutput_state_led(sync_ttl_out3_state_led)
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);
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ttl_output #(
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.REG_START_ADD(`REG_ADD_OFF_TTLIN4),
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.TEST(HARDWARE_TEST_MODE)
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) ttl_output_4 (
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.clk (sys_clk),
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.rst_n(rst_n),
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.addr(reg_reader_bus_addr),
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.wr_data(reg_reader_bus_wr_data),
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.wr_en(reg_reader_bus_wr_en),
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.rd_data(ttlout4_rd_data),
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.signal_in(ttl_output_signal_in),
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.ttloutput(sync_ttl_out4),
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.ttloutput_state_led(sync_ttl_out4_state_led)
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);
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endmodule
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