This website works better with JavaScript.
Home
Explore
Help
Sign In
p_lusterinc_xsync
/
xsync_fpge_v2
forked from
p_lusterinc_xsync/xsync_fpge
Watch
1
Star
0
Fork
0
Code
Issues
Pull Requests
Projects
Releases
Wiki
Activity
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
63
Commits
1
Branch
0
Tags
14 MiB
Verilog
95.7%
C++
3.6%
VHDL
0.7%
Tree:
3ebac6a5d9
master
Branches
Tags
${ item.name }
Create tag
${ searchTerm }
Create branch
${ searchTerm }
from '3ebac6a5d9'
${ noResults }
xsync_fpge_v2
/
source
History
zhaohe
3ebac6a5d9
部分模块添加频率探测功能
1 year ago
..
bak
timecode 添加频率探测功能
1 year ago
src
部分模块添加频率探测功能
1 year ago
test
add timecode input
2 years ago