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p_lusterinc_xsync
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xsync_fpge_v2
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63 Commits
1 Branch
0 Tags
14 MiB
Verilog 95.7%
C++ 3.6%
VHDL 0.7%
 
 
 
Tree: 3ebac6a5d9
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xsync_fpge_v2/source/src
History
zhaohe 3ebac6a5d9
部分模块添加频率探测功能
1 year ago
..
business V2.0 1 year ago
input 部分模块添加频率探测功能 1 year ago
internal 部分模块添加频率探测功能 1 year ago
output 添加延时模块 1 year ago
sys 部分模块添加频率探测功能 1 year ago
timecode reformat timecode decoder 1 year ago
zutils timecode 添加频率探测功能 1 year ago
config.v 内部信号源支持使能控制模块 1 year ago
spi_reg_bus.v 内部信号源支持使能控制模块 1 year ago
spi_reg_reader.v update 2 years ago
sys_signal_delayer.v 添加延时模块 1 year ago
top.bak.v add ttl_input 1 year ago
top.v 内部信号源支持使能控制模块 1 year ago
xsync_internal_generator.v 部分模块添加频率探测功能 1 year ago
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