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p_lusterinc_xsync
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xsync_fpge_v2
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63 Commits
1 Branch
0 Tags
14 MiB
Verilog 95.7%
C++ 3.6%
VHDL 0.7%
 
 
 
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xsync_fpge_v2/source/src/internal
History
zhaohe 3ebac6a5d9
部分模块添加频率探测功能
1 year ago
..
internal_clock_generator.v 内部信号源支持使能控制模块 1 year ago
internal_genlock_generator.v 内部信号源支持使能控制模块 1 year ago
internal_sig_generator_en_contrler.v 内部信号源支持使能控制模块 1 year ago
internal_timecode_generator.v 部分模块添加频率探测功能 1 year ago
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