forked from p_lusterinc_xsync/xsync_fpge
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149 lines
4.4 KiB
149 lines
4.4 KiB
module zsimple_pll (
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input clk, //!clock input
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input rst_n, //!asynchronous reset input, low active
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input insignal, //!输入信号
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input trigger_eage_type,
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input wire [31:0] freq_detect_bias, //! 频率偏差计数
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input wire [31:0] freq_division,
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input wire [31:0] freq_multiplication,
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input wire polarity_ctrl,
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input wire cfg_change,
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output wire outsignal
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);
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//
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//
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//insignal
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// ----->
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// insignal_trigger_sig
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// ------->
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// insignal_division
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// -------->
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// insignal_multiplication
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wire insignal_rising_edge; //! 输入信号上升沿
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wire insignal_falling_edge; //! 输入信号下降沿
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wire insignal_trigger_sig; //! 触发信号
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wire module_reset; //! 模块内部复位信号
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reg insignal_division; //! 输入信号分频后的信号
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reg insignal_multiplication;//! 输入信号倍频后的信号
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reg insignal_pluse_width_modulation;//! 输入信号脉宽调制后的信号
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zutils_edge_detecter edge_detecter (
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.clk(clk),
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.rst_n(rst_n),
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.in_signal(insignal),
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.in_signal_rising_edge(insignal_rising_edge),
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.in_signal_falling_edge(insignal_falling_edge)
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);
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assign insignal_trigger_sig = trigger_eage_type ? insignal_rising_edge : insignal_falling_edge;
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assign module_reset = !rst_n || cfg_change;
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// 分频
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reg [31:0] insignal_division_cnt;
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always @(posedge clk or posedge module_reset) begin
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if (module_reset) begin
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insignal_division_cnt <= 0;
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insignal_division <= 0;
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end
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else begin
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if(insignal_trigger_sig) begin
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if(insignal_division_cnt >= freq_division) begin
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insignal_division_cnt <= 0;
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insignal_division <= 1;
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end
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else begin
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insignal_division_cnt <= insignal_division_cnt + 1;
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end
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end
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else begin
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insignal_division <= 0;
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end
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end
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end
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wire [31:0] insignal_multiplication_freq_cnt;
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wire pluse_width_cnt_lock;
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zutils_freq_detector_v2
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freq_detector (
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.clk(clk),
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.rst_n(rst_n),
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.freq_detect_bias(freq_detect_bias),
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.pluse_input(insignal_division),
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.pluse_width_cnt(insignal_multiplication_freq_cnt),
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.pluse_width_cnt_lock(pluse_width_cnt_lock)
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);
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reg [31:0] multiplication_cnt;
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reg [31:0] multiplication_state;
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reg [31:0] gen_pluse_cnt;
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always @(posedge clk or posedge module_reset) begin
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if (module_reset || !pluse_width_cnt_lock) begin
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multiplication_cnt <= 0;
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multiplication_state <= 0;
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gen_pluse_cnt <= 0;
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insignal_multiplication <= 0;
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end
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else begin
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case (multiplication_state)
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0 : begin
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gen_pluse_cnt <= 0;
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multiplication_cnt <= 0;
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insignal_multiplication <= 0;
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if(pluse_width_cnt_lock) begin
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multiplication_state <= 1;
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end
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end
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1 : begin
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if(insignal_division) begin
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multiplication_state <= 2;
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gen_pluse_cnt <= 0;
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insignal_multiplication <= 1;
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multiplication_cnt <= 0;
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end
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end
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2: begin
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if(multiplication_cnt < insignal_multiplication_freq_cnt>>1) begin
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multiplication_cnt <= multiplication_cnt + freq_multiplication + 1;
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insignal_multiplication <= 1;
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end
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else if((multiplication_cnt+freq_multiplication+2) >= insignal_multiplication_freq_cnt) begin
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gen_pluse_cnt <= gen_pluse_cnt + 1;
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multiplication_cnt <= 0;
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insignal_multiplication <= 1;
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gen_pluse_cnt <= gen_pluse_cnt + 1;
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end
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else begin
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if(gen_pluse_cnt >= freq_multiplication ) begin
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multiplication_state <= 1;
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insignal_multiplication <= 0;
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multiplication_cnt <= 0;
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end
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else begin
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multiplication_cnt <= multiplication_cnt + freq_multiplication + 1;
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insignal_multiplication <= 0;
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end
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end
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end
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default: begin
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multiplication_state <= 0;
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end
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endcase
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end
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end
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assign outsignal = insignal_multiplication ^ polarity_ctrl;
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endmodule
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