xsync_fpge_v2/source/src/ttl_input.v

//
//  @功能:
//          1. 分频
//          2. 滤波(add later)
//    
module ttl_input #(
    parameter REG_START_ADD = 0,
    parameter SYS_CLOCK_FREQ = 10000000,
    // parameter TEST = 0,
    parameter ID = 1
) (
    input clk,   //clock input
    input rst_n, //asynchronous reset input, low active

    //寄存器读写接口    
    input       [31:0] addr,
    input       [31:0] wr_data,
    input              wr_en,
    output wire [31:0] rd_data,

    input ttlin1,
    input ttlin2,
    input ttlin3,
    input ttlin4,

    //指示灯 
    output ttlin1_state_led,
    output ttlin2_state_led,
    output ttlin3_state_led,
    output ttlin4_state_led,

    //原始信号输入
    output ttlin1_ext,
    output ttlin2_ext,
    output ttlin3_ext,
    output ttlin4_ext,

    //分频后的信号
    output ttlin1_divide,
    output ttlin2_divide,
    output ttlin3_divide,
    output ttlin4_divide

);

  reg  [31:0] r0_ttlin_en;  //信号源选择 0:off,1:bnc,2:headphone
  reg  [31:0] r1_ttlin1_devide_factor;  // 分频因子
  reg  [31:0] r2_ttlin2_devide_factor;  // 分频因子
  reg  [31:0] r3_ttlin3_devide_factor;  // 分频因子
  reg  [31:0] r4_ttlin4_devide_factor;  // 分频因子
  reg  [31:0] r5_ttlin1_filter_factor;  // 滤波
  reg  [31:0] r6_ttlin2_filter_factor;  // 滤波
  reg  [31:0] r7_ttlin3_filter_factor;  // 滤波
  reg  [31:0] r8_ttlin4_filter_factor;  // 滤波


  wire [31:0] reg_wr_index;
  zutils_register_advanced #(
      .REG_START_ADD(REG_START_ADD)
  ) _register (
      .clk(clk),
      .rst_n(rst_n),
      .addr(addr),
      .wr_data(wr_data),
      .wr_en(wr_en),
      .rd_data(rd_data),

      .reg0(r0_ttlin_en),
      .reg1(r1_ttlin1_devide_factor),
      .reg2(r2_ttlin2_devide_factor),
      .reg3(r3_ttlin3_devide_factor),
      .reg4(r4_ttlin4_devide_factor),
      .reg5(r5_ttlin1_filter_factor),
      .reg6(r6_ttlin2_filter_factor),
      .reg7(r7_ttlin3_filter_factor),
      .reg8(r8_ttlin4_filter_factor),
      .reg_wr_sig(reg_wr_sig),
      .reg_index(reg_wr_index)
  );

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      r0_ttlin_en <= 32'hffff_ffff;
      r1_ttlin1_devide_factor <= 0;
      r2_ttlin2_devide_factor <= 0;
      r3_ttlin3_devide_factor <= 0;
      r4_ttlin4_devide_factor <= 0;
      r5_ttlin1_filter_factor <= 32'd02;
      r6_ttlin2_filter_factor <= 32'd02;
      r7_ttlin3_filter_factor <= 32'd02;
      r8_ttlin4_filter_factor <= 32'd02;
    end else begin
      if (reg_wr_sig) begin
        case (reg_wr_index)
          0: r0_ttlin_en <= wr_data;
          1: r1_ttlin1_devide_factor <= wr_data;
          2: r2_ttlin2_devide_factor <= wr_data;
          3: r3_ttlin3_devide_factor <= wr_data;
          4: r4_ttlin4_devide_factor <= wr_data;
          5: r5_ttlin1_filter_factor <= wr_data;
          6: r6_ttlin2_filter_factor <= wr_data;
          7: r7_ttlin3_filter_factor <= wr_data;
          8: r8_ttlin4_filter_factor <= wr_data;
          default: begin
          end
        endcase
      end
    end
  end

  //   使能 --> 滤波 --> 分频 --> 输出

  // 使能
  assign ttlin1_sig = r0_ttlin_en[0] & ttlin1;
  assign ttlin2_sig = r0_ttlin_en[1] & ttlin2;
  assign ttlin3_sig = r0_ttlin_en[2] & ttlin3;
  assign ttlin4_sig = r0_ttlin_en[3] & ttlin4;

  // 滤波
  wire ttlin1_sig_af_filter;
  wire ttlin2_sig_af_filter;
  wire ttlin3_sig_af_filter;
  wire ttlin4_sig_af_filter;

  zutils_signal_filter_advance filter1 (
      .clk(clk),
      .rst_n(rst_n),
      .filter_delay_count(r5_ttlin1_filter_factor),
      .in(ttlin1_sig),
      .out(ttlin1_sig_af_filter)
  );
  zutils_signal_filter_advance filter2 (
      .clk(clk),
      .rst_n(rst_n),
      .filter_delay_count(r6_ttlin2_filter_factor),
      .in(ttlin2_sig),
      .out(ttlin2_sig_af_filter)
  );
  zutils_signal_filter_advance filter3 (
      .clk(clk),
      .rst_n(rst_n),
      .filter_delay_count(r7_ttlin3_filter_factor),
      .in(ttlin3_sig),
      .out(ttlin3_sig_af_filter)
  );
  zutils_signal_filter_advance filter4 (
      .clk(clk),
      .rst_n(rst_n),
      .filter_delay_count(r8_ttlin4_filter_factor),
      .in(ttlin4_sig),
      .out(ttlin4_sig_af_filter)
  );

  //分频
  wire ttlin1_sig_af_devide;
  wire ttlin2_sig_af_devide;
  wire ttlin3_sig_af_devide;
  wire ttlin4_sig_af_devide;

  ztuils_sig_devide sig_devide1 (
      .clk(clk),
      .rst_n(rst_n),
      .devide(r1_ttlin1_devide_factor),
      .in(ttlin1_sig_af_filter),
      .out(ttlin1_sig_af_devide)
  );
  ztuils_sig_devide sig_devide2 (
      .clk(clk),
      .rst_n(rst_n),
      .devide(r1_ttlin1_devide_factor),
      .in(ttlin2_sig_af_filter),
      .out(ttlin2_sig_af_devide)
  );
  ztuils_sig_devide sig_devide3 (
      .clk(clk),
      .rst_n(rst_n),
      .devide(r1_ttlin1_devide_factor),
      .in(ttlin3_sig_af_filter),
      .out(ttlin3_sig_af_devide)
  );
  ztuils_sig_devide sig_devide4 (
      .clk(clk),
      .rst_n(rst_n),
      .devide(r1_ttlin1_devide_factor),
      .in(ttlin4_sig_af_filter),
      .out(ttlin4_sig_af_devide)
  );
  assign ttlin1_state_led = 1;
  assign ttlin2_state_led = 1;
  assign ttlin3_state_led = 1;
  assign ttlin4_state_led = 1;

  //原始信号输入
  assign ttlin1_ext = ttlin1_sig_af_filter;
  assign ttlin2_ext = ttlin2_sig_af_filter;
  assign ttlin3_ext = ttlin3_sig_af_filter;
  assign ttlin4_ext = ttlin4_sig_af_filter;

  //分频后的信号
  assign ttlin1_divide = ttlin1_sig_af_devide;
  assign ttlin2_divide = ttlin2_sig_af_devide;
  assign ttlin3_divide = ttlin3_sig_af_devide;
  assign ttlin4_divide = ttlin4_sig_af_devide;


endmodule