forked from p_lusterinc_xsync/xsync_fpge
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97 lines
2.7 KiB
97 lines
2.7 KiB
module sys_signal_delayer #(
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parameter REG_START_ADD = 0,
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parameter SYS_CLOCK_FREQ = 10000000,
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parameter SIG_BUS_WIDTH = 15
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) (
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input clk, //! 时钟输入
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input rst_n, //! 复位输入
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input [31:0] addr, //! 寄存器地址
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input [31:0] wr_data, //! 写入数据
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input wr_en, //! 写使能
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output wire [31:0] rd_data, //! 读出数据
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/*******************************************************************************
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* 输入信号延迟 *
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*******************************************************************************/
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input [SIG_BUS_WIDTH:0] sig_in,
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output [SIG_BUS_WIDTH:0] sig_out
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);
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reg [31:0] r1_ctrl_reg_index;
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reg [31:0] r2_delay_cnt_ctrl;
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reg [31:0] delay_ctrl [SIG_BUS_WIDTH:0];
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wire [31:0] reg_wr_index;
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zutils_register_advanced #(
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.REG_START_ADD(REG_START_ADD)
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) _register (
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.clk (clk),
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.rst_n (rst_n),
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.addr (addr),
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.wr_data (wr_data),
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.wr_en (wr_en),
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.rd_data (rd_data),
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.reg1 (r1_ctrl_reg_index),
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.reg2 (r2_delay_cnt_ctrl),
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.reg_wr_sig(reg_wr_sig),
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.reg_index (reg_wr_index)
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);
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reg delayer_rst_n_ctrl;
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integer m;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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r1_ctrl_reg_index <= 0;
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r2_delay_cnt_ctrl <= delay_ctrl[r1_ctrl_reg_index][31:0];
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for (m = 0; m <= SIG_BUS_WIDTH; m = m + 1) begin
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delay_ctrl[m] <= 0;
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end
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delayer_rst_n_ctrl <= 1;
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end else begin
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case (reg_wr_sig)
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0: begin
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delayer_rst_n_ctrl <= 1;
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// r2_delay_cnt_ctrl <= delay_ctrl[r1_ctrl_reg_index][31:0];
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end
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1: begin
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delayer_rst_n_ctrl <= 0;
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case (reg_wr_index)
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1: begin
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if (wr_data <= SIG_BUS_WIDTH) begin
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r1_ctrl_reg_index <= wr_data;
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r2_delay_cnt_ctrl <= delay_ctrl[wr_data][31:0];
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end
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end
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2: begin
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delay_ctrl[r1_ctrl_reg_index][31:0] <= wr_data;
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r2_delay_cnt_ctrl <= wr_data;
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end
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endcase
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end
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endcase
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end
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end
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assign delayer_rst_n = delayer_rst_n_ctrl & rst_n;
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genvar i;
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generate
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for (i = 0; i <= SIG_BUS_WIDTH; i = i + 1) begin
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zutils_sig_delayer_v2 sig_delayer_inst (
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.clk (clk),
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.rst_n (delayer_rst_n),
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.delay_cnt(delay_ctrl[i]),
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.in (sig_in[i]),
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.out (sig_out[i])
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);
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// assign sig_out[i] = sig_in[i];
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end
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endgenerate
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// assign sig_out = sig_in;
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endmodule
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