forked from p_lusterinc_xsync/xsync_fpge
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zhaohe
9e9c057811
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11 months ago | |
|---|---|---|
| .vscode | 11 months ago | |
| constraint_check | 11 months ago | |
| ip_backup/20240321095414/ShiftRegister | 1 year ago | |
| ipcore | 11 months ago | |
| pango_tools | 11 months ago | |
| release | 1 year ago | |
| source | 11 months ago | |
| .gitignore | 12 months ago | |
| ACPGL22G核心板原理图.pdf | 2 years ago | |
| README.md | 1 year ago | |
| cfg_verify_result.sbit | 1 year ago | |
| data.wf | 2 years ago | |
| fdc_generator.exe | 11 months ago | |
| msg_level.txt | 11 months ago | |
| multiseed_summary.csv | 11 months ago | |
| pin.md | 2 years ago | |
| rdfile_2024_3_26_21_12_43 | 1 year ago | |
| xsync.backup_1.pds | 11 months ago | |
| xsync.csv | 11 months ago | |
| xsync.fdc | 11 months ago | |
| xsync.pds | 11 months ago | |
| xsync.pds.lock | 11 months ago | |
| xsync_ok.csv | 11 months ago | |
README.md
https://iflytop1.feishu.cn/docx/Fk3CdIRNZoal1XxCGgjc9q1Dn1f
固化
https://iflytop1.feishu.cn/wiki/DyHLwd2pLicjXxkWNEvc7vI7n2b
cfg_gen_sfc -device_name W25Q128Q -opcode 107 -sbit_start_address 0 -sbit D:/workspace/p_lusterinc/xsync_fpge/generate_bitstream/Top.sbit
注意事项:
倍频和分频的前提建立在输入频率稳定的情况才有效的。如果输入频率在+-一定范围内变化，输出波形可能会出现异常
插件:
Documenter - TerosHDL 0.1.4 documentation
Verilog-HDL/SystemVerilog/Bluespec SystemVerilog
v0.0.0.4
1. 修复timecode启动时前两帧重复的问题
2. 修复timecode输出时候子帧出现00的情况