forked from p_lusterinc_xsync/xsync_fpge
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753 lines
27 KiB
753 lines
27 KiB
`timescale 1ns / 1ns
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`include "config.v"
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module Top (
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input ex_clk,
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input ex_rst_n,
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input genlock_in_hsync,
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input genlock_in_vsync,
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input genlock_in_fsync,
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output genlock_in_state_led,
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output [9:0] genlock_out_dac,
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output genlock_out_dac_clk,
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output genlock_out_dac_state_led,
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input sync_ttl_in1,
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output sync_ttl_in1_state_led,
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input sync_ttl_in2,
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output sync_ttl_in2_state_led,
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input sync_ttl_in3,
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output sync_ttl_in3_state_led,
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input sync_ttl_in4,
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output sync_ttl_in4_state_led,
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output sync_ttl_out1,
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output sync_ttl_out1_state_led,
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output sync_ttl_out2,
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output sync_ttl_out2_state_led,
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output sync_ttl_out3,
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output sync_ttl_out3_state_led,
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output sync_ttl_out4,
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output sync_ttl_out4_state_led,
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input timecode_headphone_in,
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output timecode_headphone_in_state_led,
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input timecode_bnc_in,
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output timecode_bnc_in_state_led,
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output timecode_out_bnc,
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output timecode_out_bnc_select,
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output timecode_out_bnc_state_led,
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output timecode_out_headphone,
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output timecode_out_headphone_select,
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output timecode_out_headphone_state_led,
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output stm32if_start_signal_out,
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output stm32if_camera_sync_out,
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output stm32if_timecode_sync_out,
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//SPI 串行总线1
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input wire spi1_cs_pin,
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input wire spi1_clk_pin,
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input wire spi1_rx_pin,
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output wire spi1_tx_pin,
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output [15:0] debug_signal_output,
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output core_board_debug_led
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);
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/***********************************************************************************************************************
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* 时钟 *
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***********************************************************************************************************************/
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localparam SYS_CLOCK_FREQ = 10000000;
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wire sys_clk; //! 系统时钟
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wire sys_rst_n; //! 系统复位
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//系统时钟源
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SPLL spll (
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.clkin1 (ex_clk),
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.lock (pll_lock),
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.clkout0(sys_clk_25m),
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.clkout1(sys_clk_10m),
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.clkout2(sys_clk_5m)
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);
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assign sys_clk = sys_clk_10m;
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assign sys_rst_n = pll_lock;
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/***********************************************************************************************************************
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* 调试指示灯 *
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***********************************************************************************************************************/
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breathing_lamp breathing_lamp_ins (
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.clk (sys_clk),
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.rst_n (sys_rst_n),
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.lampio(core_board_debug_led)
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);
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/***********************************************************************************************************************
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* 其他 *
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***********************************************************************************************************************/
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//寄存器读写总线
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wire [31:0] RegReaderBus_addr; //!寄存器读写-地址总线
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wire [31:0] RegReaderBus_wr_data; //!寄存器读写-数据总线
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wire RegReaderBus_wr_en; //!寄存器读写-写使能位置
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reg [31:0] RegReaderBus_rd_data; //!寄存器读写-读数据总线
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//模块寄存器读总线
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wire [31:0] rd_data_module_fpga_info; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_ttlin; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_timecode_in; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_genlock_in; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_internal_timecode; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_internal_genlock; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_internal_clock; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_internal_sig_en_contrler; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_ttlout1; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_ttlout2; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_ttlout3; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_ttlout4; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_timecode_out; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_genlock_out; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_camera_sync_out; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_sys_timecode; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_sys_genlock; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_sys_clock; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_record_sig_generator; //! 模块寄存器数据总线读数据
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wire [31:0] rd_data_module_sys_signal_delayer; //! 模块寄存器数据总线读数据
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//内部信号
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wire signal_logic0; //! 逻辑0
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wire signal_logic1; //! 逻辑1
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wire signal_ttlin1; //! TTL输入1
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wire signal_ttlin2; //! TTL输入2
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wire signal_ttlin3; //! TTL输入3
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wire signal_ttlin4; //! TTL输入4
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wire signal_ext_genlock_freq; //! 外部GENLOCK频率信号
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wire signal_ext_timecode_freq; //! 外部时间码频率信号
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wire signal_internal_timecode_freq; //! 内部时间码频率信号
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wire signal_internal_genlock_freq; //! 内部GENLOCK频率信号
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wire signal_internal_clk_sig; //! 内部频率信号
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wire signal_sys_clk_output; //! 系统时钟输出
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wire signal_sys_genlock_output; //! 系统GENLOCK输出
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wire signal_sys_timecode_freq_output; //! 系统时间码频率输出
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wire signal_business_record_en_sig; //! 业务摄影状态信号
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wire signal_business_record_exposure_sig; //! 业务摄影拍照曝光信号
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wire signal_business_record_en_rsing_edge_sig; //! 业务摄影状态信号
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wire signal_business_record_en_falling_edge_sig; //! 业务摄影状态信号
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wire signal_business_record_en_edge_sig; //! 业务摄影状态信号
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wire internal_timecode_tigger_sig; //!内部timecode频率信号
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wire [31:0] internal_timecode_format; //!内部timecode格式
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wire [63:0] internal_timecode_data; //!内部timecode数据
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wire internal_timecode_serial_data; //!内部timecode串行数据
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wire ext_timecode_tigger_sig; //!外部timecode频率信号
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wire [31:0] ext_timecode_format; //!外部timecode格式
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wire [63:0] ext_timecode_data; //!外部timecode数据
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wire ext_timecode_serial_data; //!外部timecode串行数据
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wire sys_timecode_tigger_sig; //!外部timecode频率信号
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wire [31:0] sys_timecode_format; //!外部timecode格式
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wire [63:0] sys_timecode_data; //!外部timecode数据
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wire sys_timecode_serial_data; //!外部timecode串行数据
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wire [31:0] sig_src; // 系统内部信号总线
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assign sig_src[`SIGNAL_LOGIC0] = signal_logic0;
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assign sig_src[`SIGNAL_LOGIC1] = signal_logic1;
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assign sig_src[`SIGNAL_TTLIN1] = signal_ttlin1;
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assign sig_src[`SIGNAL_TTLIN2] = signal_ttlin2;
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assign sig_src[`SIGNAL_TTLIN3] = signal_ttlin3;
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assign sig_src[`SIGNAL_TTLIN4] = signal_ttlin4;
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assign sig_src[`SIGNAL_EXT_GENLOCK_FREQ] = signal_ext_genlock_freq;
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assign sig_src[`SIGNAL_EXT_TIMECODE_FREQ] = signal_ext_timecode_freq;
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assign sig_src[`SIGNAL_INTERNAL_TIMECODE_FREQ] = signal_internal_timecode_freq;
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assign sig_src[`SIGNAL_INTERNAL_GENLOCK_FREQ] = signal_internal_genlock_freq;
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assign sig_src[`SIGNAL_INTERNAL_CLOCK_SIG] = signal_internal_clk_sig;
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assign sig_src[`SIGNAL_SYS_CLK_OUTPUT] = signal_sys_clk_output;
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assign sig_src[`SIGNAL_SYS_GENLOCK_OUTPUT] = signal_sys_genlock_output;
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assign sig_src[`SIGNAL_SYS_TIMECODE_FREQ_OUTPUT] = signal_sys_timecode_freq_output;
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assign sig_src[`SIGNAL_BUSINESS_RECORD_SIG] = signal_business_record_en_sig;
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assign sig_src[`SIGNAL_BUSINESS_RECORD_EXPOSURE_SIG] = signal_business_record_exposure_sig;
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assign sig_src[`SIGNAL_BUSINESS_RECORD_EN_RSING_EDGE_SIG] = signal_business_record_en_rsing_edge_sig;
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assign sig_src[`SIGNAL_BUSINESS_RECORD_EN_FALLING_EDGE_SIG] = signal_business_record_en_falling_edge_sig;
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assign sig_src[`SIGNAL_BUSINESS_RECORD_EN_EDGE_SIG] = signal_business_record_en_edge_sig;
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assign signal_logic0 = 1'b0;
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assign signal_logic1 = 1'b1;
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assign signal_internal_timecode_freq = internal_timecode_serial_data;
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assign signal_sys_timecode_freq_output = sys_timecode_tigger_sig;
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spi_reg_bus _spi_reg_bus (
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.clk (sys_clk),
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.rst_n (sys_rst_n),
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.addr (RegReaderBus_addr),
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.wr_data (RegReaderBus_wr_data),
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.wr_en (RegReaderBus_wr_en),
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.spi_cs_pin (spi1_cs_pin),
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.spi_clk_pin(spi1_clk_pin),
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.spi_rx_pin (spi1_rx_pin),
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.spi_tx_pin (spi1_tx_pin),
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.rd_data_module_fpga_info (rd_data_module_fpga_info),
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.rd_data_module_ttlin (rd_data_module_ttlin),
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.rd_data_module_timecode_in (rd_data_module_timecode_in),
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.rd_data_module_genlock_in (rd_data_module_genlock_in),
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.rd_data_module_internal_timecode (rd_data_module_internal_timecode),
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.rd_data_module_internal_genlock (rd_data_module_internal_genlock),
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.rd_data_module_internal_clock (rd_data_module_internal_clock),
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.rd_data_module_internal_sig_en_contrler(rd_data_module_internal_sig_en_contrler),
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.rd_data_module_ttlout1 (rd_data_module_ttlout1),
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.rd_data_module_ttlout2 (rd_data_module_ttlout2),
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.rd_data_module_ttlout3 (rd_data_module_ttlout3),
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.rd_data_module_ttlout4 (rd_data_module_ttlout4),
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.rd_data_module_timecode_out (rd_data_module_timecode_out),
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.rd_data_module_genlock_out (rd_data_module_genlock_out),
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.rd_data_module_camera_sync_out (rd_data_module_camera_sync_out),
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.rd_data_module_sys_timecode (rd_data_module_sys_timecode),
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.rd_data_module_sys_genlock (rd_data_module_sys_genlock),
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.rd_data_module_sys_clock (rd_data_module_sys_clock),
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.rd_data_module_record_sig_generator (rd_data_module_record_sig_generator),
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.rd_data_module_sys_signal_delayer (rd_data_module_sys_signal_delayer)
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);
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zutils_register16 #(
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.REG_START_ADD(`REGADDOFF__FPGA_INFO),
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.REG0_INIT(`VERSION),
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.REG1_INIT(0),
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.REG2_INIT(0),
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.REG3_INIT(0),
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.REG4_INIT(0),
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.REG5_INIT(0),
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.REG6_INIT(0),
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.REG7_INIT(0),
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.REG8_INIT(0),
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.REG9_INIT(0),
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.REGA_INIT(0),
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.REGB_INIT(0),
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.REGC_INIT(0),
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.REGD_INIT(0),
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.REGE_INIT(0),
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.REGF_INIT(0)
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) test_reg (
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.clk (sys_clk),
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.rst_n (sys_rst_n),
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.addr (RegReaderBus_addr),
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.wr_data(RegReaderBus_wr_data),
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.wr_en (RegReaderBus_wr_en),
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.rd_data(rd_data_module_fpga_info)
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);
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/***********************************************************************************************************************
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* 呼吸灯输出结束 *
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***********************************************************************************************************************/
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assign debug_signal_output[0] = sys_clk;
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assign debug_signal_output[1] = spi1_cs_pin;
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assign debug_signal_output[2] = spi1_clk_pin;
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assign debug_signal_output[3] = spi1_cs_pin;
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assign debug_signal_output[4] = spi1_tx_pin;
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/*
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wire [15:0] sys_sig_delay_in;
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wire [15:0] sys_sig_delay_out;
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wire before_delay__sync_ttl_out1;
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wire before_delay__sync_ttl_out2;
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wire before_delay__sync_ttl_out3;
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wire before_delay__sync_ttl_out4;
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wire before_delay__stm32if_start_signal_out;
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wire before_delay__stm32if_camera_sync_out;
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wire before_delay__stm32if_timecode_sync_out;
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wire af_delay__sync_ttl_in1;
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wire af_delay__sync_ttl_in2;
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wire af_delay__sync_ttl_in3;
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wire af_delay__sync_ttl_in4;
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wire af_delay__timecode_headphone_in;
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wire af_delay__timecode_bnc_in;
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wire af_delay__genlock_in_hsync;
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wire af_delay__genlock_in_vsync;
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wire af_delay__genlock_in_fsync;
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assign sys_sig_delay_in[0] = sync_ttl_in1; //
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assign sys_sig_delay_in[1] = sync_ttl_in2; //
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assign sys_sig_delay_in[2] = sync_ttl_in3; //
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assign sys_sig_delay_in[3] = !sync_ttl_in4; //
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assign sys_sig_delay_in[4] = timecode_headphone_in; //
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assign sys_sig_delay_in[5] = timecode_bnc_in; //
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assign sys_sig_delay_in[7] = genlock_in_vsync; //
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assign sys_sig_delay_in[6] = genlock_in_hsync; //
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assign sys_sig_delay_in[8] = genlock_in_fsync; //
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assign sys_sig_delay_in[9] = before_delay__sync_ttl_out1; //
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assign sys_sig_delay_in[10] = before_delay__sync_ttl_out2; //
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assign sys_sig_delay_in[11] = before_delay__sync_ttl_out3; //
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assign sys_sig_delay_in[12] = before_delay__sync_ttl_out4; //
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assign sys_sig_delay_in[13] = before_delay__stm32if_start_signal_out; //
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assign sys_sig_delay_in[14] = before_delay__stm32if_camera_sync_out; //
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assign sys_sig_delay_in[15] = before_delay__stm32if_timecode_sync_out; //
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assign af_delay__sync_ttl_in1 = sys_sig_delay_out[0];
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assign af_delay__sync_ttl_in2 = sys_sig_delay_out[1];
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assign af_delay__sync_ttl_in3 = sys_sig_delay_out[2];
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assign af_delay__sync_ttl_in4 = sys_sig_delay_out[3];
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assign af_delay__timecode_headphone_in = sys_sig_delay_out[4];
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assign af_delay__timecode_bnc_in = sys_sig_delay_out[5];
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assign af_delay__genlock_in_vsync = sys_sig_delay_out[7];
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assign af_delay__genlock_in_hsync = sys_sig_delay_out[6];
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assign af_delay__genlock_in_fsync = sys_sig_delay_out[8];
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assign sync_ttl_out1 = sys_sig_delay_out[9];
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assign sync_ttl_out2 = sys_sig_delay_out[10];
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assign sync_ttl_out3 = sys_sig_delay_out[11];
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assign sync_ttl_out4 = sys_sig_delay_out[12];
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assign stm32if_start_signal_out = sys_sig_delay_out[13];
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assign stm32if_camera_sync_out = sys_sig_delay_out[14];
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assign stm32if_timecode_sync_out = sys_sig_delay_out[15];
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sys_signal_delayer #(
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.REG_START_ADD (`REGADDOFF__DELAYER),
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
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.SIG_BUS_WIDTH(15)
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) sys_signal_delayer_ins (
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.clk (sys_clk),
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.rst_n(sys_rst_n),
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.addr (RegReaderBus_addr),
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.wr_data(RegReaderBus_wr_data),
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.wr_en (RegReaderBus_wr_en),
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.rd_data(rd_data_module_sys_signal_delayer),
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.sig_in (sys_sig_delay_in),
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.sig_out(sys_sig_delay_out)
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);
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internal_sig_generator_en_contrler #(
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.REG_START_ADD (`REGADDOFF__INTERNAL_SIG_EN_CONTRLER),
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
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) internal_sig_generator_en_contrler0 (
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.clk (sys_clk),
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.rst_n(sys_rst_n),
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.addr (RegReaderBus_addr),
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.wr_data(RegReaderBus_wr_data),
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.wr_en (RegReaderBus_wr_en),
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.rd_data(rd_data_module_internal_sig_en_contrler),
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.en0(en0),
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.en1(en1),
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.en2(en2)
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);
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internal_timecode_generator #(
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.REG_START_ADD(`REGADDOFF__INTERNAL_TIMECODE),
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.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
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.ID(1)
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) internal_timecode_generator0 (
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.clk (sys_clk),
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.rst_n(sys_rst_n),
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.addr (RegReaderBus_addr),
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.wr_data(RegReaderBus_wr_data),
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.wr_en (RegReaderBus_wr_en),
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.rd_data(rd_data_module_internal_timecode),
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.en(en0),
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.timecode_tigger_sig (internal_timecode_tigger_sig),
|
|
.timecode_format (internal_timecode_format),
|
|
.timecode_data (internal_timecode_data),
|
|
.timecode_serial_data(internal_timecode_serial_data)
|
|
);
|
|
|
|
sys_timecode #(
|
|
.REG_START_ADD (`REGADDOFF__SYS_TIMECODE),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
|
|
) sys_timecode_ins (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_sys_timecode),
|
|
|
|
.internal_timecode_tigger_sig (internal_timecode_tigger_sig),
|
|
.internal_timecode_format (internal_timecode_format),
|
|
.internal_timecode_data (internal_timecode_data),
|
|
.internal_timecode_serial_data(internal_timecode_serial_data),
|
|
|
|
.external_timecode_tigger_sig (ext_timecode_tigger_sig),
|
|
.external_timecode_format (ext_timecode_format),
|
|
.external_timecode_data (ext_timecode_data),
|
|
.external_timecode_serial_data(ext_timecode_serial_data),
|
|
|
|
.sys_timecode_tigger_sig (sys_timecode_tigger_sig),
|
|
.sys_timecode_format (sys_timecode_format),
|
|
.sys_timecode_data (sys_timecode_data),
|
|
.sys_timecode_serial_data(sys_timecode_serial_data)
|
|
);
|
|
|
|
timecode_input_parser #(
|
|
.REG_START_ADD (`REGADDOFF__TIMECODE_IN),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
|
|
) timecode_input_ins (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_timecode_in),
|
|
|
|
//input
|
|
.timecode_bnc_in (af_delay__timecode_bnc_in),
|
|
.timecode_headphone_in(af_delay__timecode_headphone_in),
|
|
|
|
//output
|
|
.timecode_tigger_sig (ext_timecode_tigger_sig),
|
|
.timecode_format (ext_timecode_format), //[31:0]
|
|
.timecode_data (ext_timecode_data), //[63:0]
|
|
.timecode_serial_data (ext_timecode_serial_data),
|
|
.timecode_is_detected (timecode_is_detected),
|
|
.timecode_headphone_in_state_led(timecode_headphone_in_state_led),
|
|
.timecode_bnc_in_state_led (timecode_bnc_in_state_led)
|
|
);
|
|
|
|
timecode_output #(
|
|
.REG_START_ADD (`REGADDOFF__TIMECODE_OUT),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
|
|
) timecode_output_inst (
|
|
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_timecode_out),
|
|
|
|
.in_timecode_tigger_sig (sys_timecode_tigger_sig),
|
|
.in_timecode_format (sys_timecode_format),
|
|
.in_timecode_data (sys_timecode_data),
|
|
.in_timecode_serial_data(sys_timecode_serial_data),
|
|
|
|
.timecode_out_bnc (timecode_out_bnc),
|
|
.timecode_out_bnc_select (timecode_out_bnc_select),
|
|
.timecode_out_bnc_state_led(timecode_out_bnc_state_led),
|
|
|
|
.timecode_out_headphone (timecode_out_headphone),
|
|
.timecode_out_headphone_select (timecode_out_headphone_select),
|
|
.timecode_out_headphone_state_led(timecode_out_headphone_state_led)
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
genlock_input_module #(
|
|
.REG_START_ADD (`REGADDOFF__GENLOCK_IN),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
|
|
) genlock_input (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_genlock_in),
|
|
|
|
.genlock_in_hsync(af_delay__genlock_in_hsync),
|
|
.genlock_in_vsync(af_delay__genlock_in_vsync),
|
|
.genlock_in_fsync(af_delay__genlock_in_fsync),
|
|
|
|
.genlock_freq_signal (signal_ext_genlock_freq),
|
|
.genlock_in_state_led(genlock_in_state_led)
|
|
);
|
|
|
|
internal_genlock_generator #(
|
|
.REG_START_ADD (`REGADDOFF__INTERNAL_GENLOCK),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
|
|
) internal_genlock_generator0 (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_internal_genlock),
|
|
|
|
.en(en1),
|
|
|
|
.genlock_freq_signal(signal_internal_genlock_freq)
|
|
);
|
|
|
|
sys_genlock #(
|
|
.REG_START_ADD (`REGADDOFF__SYS_GENLOCK),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
|
|
) sys_genlock0 (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_sys_genlock),
|
|
|
|
.internal_genlock_sig(signal_internal_genlock_freq),
|
|
.external_genlock_sig(signal_ext_genlock_freq),
|
|
|
|
.sys_genlock_tigger_sig(signal_sys_genlock_output)
|
|
);
|
|
|
|
internal_clock_generator #(
|
|
.REG_START_ADD (`REGADDOFF__INTERNAL_CLOCK),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
|
|
) internal_clock_generator0 (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_internal_clock),
|
|
|
|
.en(en2),
|
|
|
|
.clk_output(signal_internal_clk_sig)
|
|
);
|
|
|
|
ttl_input #(
|
|
.REG_START_ADD (`REGADDOFF__TTLIN),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
|
|
) ttl_inputr_ins (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_ttlin),
|
|
|
|
.ttlin1_raw(af_delay__sync_ttl_in1),
|
|
.ttlin2_raw(af_delay__sync_ttl_in2),
|
|
.ttlin3_raw(af_delay__sync_ttl_in3),
|
|
.ttlin4_raw(!af_delay__sync_ttl_in4), //in4电路上进行了反向
|
|
|
|
//指示灯
|
|
.ttlin1_state_led(sync_ttl_in1_state_led),
|
|
.ttlin2_state_led(sync_ttl_in2_state_led),
|
|
.ttlin3_state_led(sync_ttl_in3_state_led),
|
|
.ttlin4_state_led(sync_ttl_in4_state_led),
|
|
|
|
//原始信号
|
|
.sig_ttlin1(signal_ttlin1),
|
|
.sig_ttlin2(signal_ttlin2),
|
|
.sig_ttlin3(signal_ttlin3),
|
|
.sig_ttlin4(signal_ttlin4)
|
|
);
|
|
|
|
|
|
sys_clock #(
|
|
.REG_START_ADD (`REGADDOFF__SYS_CLOCK),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
|
|
) sys_clock0 (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_sys_clock),
|
|
|
|
.signal_in(sig_src),
|
|
.sys_clock(signal_sys_clk_output)
|
|
);
|
|
|
|
camera_sync_signal_output #(
|
|
.REG_START_ADD (`REGADDOFF__CAMERA_SYNC_OUT),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
|
|
) camera_sync_signal_output0 (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_camera_sync_out),
|
|
|
|
.in_timecode_tigger_sig (sys_timecode_tigger_sig),
|
|
.in_timecode_format (sys_timecode_format),
|
|
.in_timecode_data (sys_timecode_data),
|
|
.in_timecode_serial_data(sys_timecode_serial_data),
|
|
|
|
.frame_sig (signal_sys_clk_output),
|
|
.record_en_sig(signal_business_record_en_sig),
|
|
|
|
|
|
.stm32if_camera_sync_out (before_delay__stm32if_camera_sync_out),
|
|
.stm32if_record_state_change_sig(before_delay__stm32if_start_signal_out),
|
|
.stm32if_timecode_tigger_sig (before_delay__stm32if_timecode_sync_out)
|
|
);
|
|
// /*
|
|
|
|
ttl_output #(
|
|
.REG_START_ADD(`REGADDOFF__TTLOUT1),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
|
|
.ID(1)
|
|
) ttl_output_1 (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_ttlout1),
|
|
|
|
.signal_in(sig_src),
|
|
|
|
.ttloutput (before_delay__sync_ttl_out1),
|
|
.ttloutput_state_led(sync_ttl_out1_state_led)
|
|
);
|
|
ttl_output #(
|
|
.REG_START_ADD(`REGADDOFF__TTLOUT2),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
|
|
.ID(2)
|
|
) ttl_output_2 (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_ttlout2),
|
|
|
|
.signal_in(sig_src),
|
|
|
|
.ttloutput (before_delay__sync_ttl_out2),
|
|
.ttloutput_state_led(sync_ttl_out2_state_led)
|
|
);
|
|
|
|
ttl_output #(
|
|
.REG_START_ADD(`REGADDOFF__TTLOUT3),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
|
|
.ID(3)
|
|
) ttl_output_3 (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_ttlout3),
|
|
|
|
.signal_in(sig_src),
|
|
|
|
.ttloutput (before_delay__sync_ttl_out3),
|
|
.ttloutput_state_led(sync_ttl_out3_state_led)
|
|
);
|
|
|
|
ttl_output #(
|
|
.REG_START_ADD(`REGADDOFF__TTLOUT4),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
|
|
.ID(4)
|
|
) ttl_output_4 (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_ttlout4),
|
|
|
|
.signal_in(sig_src),
|
|
|
|
.ttloutput (before_delay__sync_ttl_out4),
|
|
.ttloutput_state_led(sync_ttl_out4_state_led)
|
|
);
|
|
|
|
|
|
record_sig_generator #(
|
|
.REG_START_ADD(`REGADDOFF__RECORD_SIG_GENERATOR),
|
|
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
|
|
.TEST(0)
|
|
) record_sig_generator0 (
|
|
.clk (sys_clk),
|
|
.rst_n(sys_rst_n),
|
|
|
|
.addr (RegReaderBus_addr),
|
|
.wr_data(RegReaderBus_wr_data),
|
|
.wr_en (RegReaderBus_wr_en),
|
|
.rd_data(rd_data_module_record_sig_generator),
|
|
|
|
.ttlin1_sig(signal_ttlin1),
|
|
.ttlin2_sig(signal_ttlin2),
|
|
.ttlin3_sig(signal_ttlin3),
|
|
.ttlin4_sig(signal_ttlin4),
|
|
|
|
.frame_freq_sig(signal_sys_clk_output),
|
|
|
|
.out_record_en_rsing_edge_sig (signal_business_record_en_rsing_edge_sig),
|
|
.out_record_en_falling_edge_sig(signal_business_record_en_falling_edge_sig),
|
|
.out_record_en_edge_sig (signal_business_record_en_edge_sig),
|
|
|
|
.sys_timecode_tigger_sig(sys_timecode_tigger_sig),
|
|
.sys_timecode_data (sys_timecode_data),
|
|
|
|
.out_record_en_sig (signal_business_record_en_sig),
|
|
.out_record_exposure_sig(signal_business_record_exposure_sig)
|
|
);
|
|
*/
|
|
|
|
|
|
/*
|
|
assign debug_signal_output[0] = sys_clk;
|
|
assign debug_signal_output[1] = af_delay__sync_ttl_in3;
|
|
assign debug_signal_output[2] = af_delay__sync_ttl_in2;
|
|
assign debug_signal_output[3] = genlock_in_vsync;
|
|
assign debug_signal_output[4] = af_delay__genlock_in_vsync;
|
|
assign debug_signal_output[5] = !timecode_headphone_in | !timecode_bnc_in;
|
|
assign debug_signal_output[6] = !af_delay__timecode_headphone_in | !af_delay__timecode_bnc_in;
|
|
assign debug_signal_output[7] = sync_ttl_out1;
|
|
assign debug_signal_output[8] = sync_ttl_out2;
|
|
assign debug_signal_output[9] = sync_ttl_out3;
|
|
assign debug_signal_output[10] = sync_ttl_out4;
|
|
assign debug_signal_output[11] = sync_ttl_in1;
|
|
assign debug_signal_output[12] = sync_ttl_in2;
|
|
assign debug_signal_output[13] = sync_ttl_in3;
|
|
assign debug_signal_output[15] = !sync_ttl_in4;
|
|
*/
|
|
|
|
endmodule
|