forked from p_lusterinc_xsync/xsync_fpge
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693 B
693 B
https://iflytop1.feishu.cn/docx/Fk3CdIRNZoal1XxCGgjc9q1Dn1f
固化
https://iflytop1.feishu.cn/wiki/DyHLwd2pLicjXxkWNEvc7vI7n2b
cfg_gen_sfc -device_name W25Q128Q -opcode 107 -sbit_start_address 0 -sbit ./generate_bitstream/Top.sbit
注意事项:
倍频和分频的前提建立在输入频率稳定的情况才有效的。如果输入频率在+-一定范围内变化，输出波形可能会出现异常
插件:
Documenter - TerosHDL 0.1.4 documentation
Verilog-HDL/SystemVerilog/Bluespec SystemVerilog
v0.0.0.4
1. 修复timecode启动时前两帧重复的问题
2. 修复timecode输出时候子帧出现00的情况