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(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Thu Apr 11 09:37:35 2024")
(_version "1.0.5")
(_status "initial")
(_project
)
(_task tsk_setup
(_widget wgt_select_arch
(_input
(_part
(_family Logos)
(_device PGL22G)
(_speedgrade -6)
(_package MBG324)
)
)
)
(_widget wgt_my_design_src
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-03-29T14:52:17")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_pluse_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_edge_detecter.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_register.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_multiplexer_4t1.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_debug_led.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_signal_filter.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_clk_parser.v"
(_format verilog)
(_timespec "2024-03-04T10:38:07")
)
(_file "source/src/zutils/zutils_multiplexer_16t1.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/output/ttl_output.v"
(_format verilog)
(_timespec "2024-03-29T13:10:05")
)
(_file "source/src/zutils/zutils_pwm_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_reset_sig_gen.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_multiplexer_2t1.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_multiplexer_32t1.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_muti_debug_signal_gen.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/xsync_internal_generator.v"
(_format verilog)
(_timespec "2024-03-23T19:55:54")
)
(_file "source/src/zutils/zutils_pwm_generator_advanced.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_register_advanced.v"
(_format verilog)
(_timespec "2024-03-25T09:14:45")
)
(_file "source/src/zutils/zutils_genlock_clk_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_multiplexer_32t1_v2.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/ztutils_timecode_next_code.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_smpte_timecode_clk_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/timecode/timecode_nextcode.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/timecode/timecode_basesig_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/timecode/timecode_serialization.v"
(_format verilog)
(_timespec "2024-03-25T16:05:09")
)
(_file "source/src/timecode/timecode_generator.v"
(_format verilog)
(_timespec "2024-04-11T09:27:05")
)
(_file "source/src/output/timecode_output.v"
(_format verilog)
(_timespec "2024-03-25T17:21:13")
)
(_file "source/src/input/timecode_input.v"
(_format verilog)
(_timespec "2024-03-26T22:03:36")
)
(_file "source/src/timecode/timecode_decoder.v"
(_format verilog)
(_timespec "2024-03-23T18:54:04")
)
(_file "source/src/timecode/timecode_sample_sig_generator.v"
(_format verilog)
(_timespec "2024-03-25T09:20:42")
)
(_file "source/src/input/ttl_input.v"
(_format verilog)
(_timespec "2024-03-22T21:00:04")
)
(_file "source/src/zutils/ztuils_sig_devide.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_signal_filter_advance.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/timecode/timecode_comparator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_freq_detector.v"
(_format verilog)
(_timespec "2024-03-02T17:47:04")
)
(_file "source/src/zutils/zsimple_pll.v"
(_format verilog)
(_timespec "2024-03-29T13:12:21")
)
(_file "source/src/zutils/zutils_freq_detector_v2.v"
(_format verilog)
(_timespec "2024-03-04T15:12:52")
)
(_file "source/src/zutils/zutils_multiplexer_8t1.v"
(_format verilog)
(_timespec "2024-03-04T10:57:15")
)
(_file "source/src/spi_reg_bus.v"
(_format verilog)
(_timespec "2024-03-23T17:00:10")
)
(_file "source/src/internal/internal_timecode_generator.v"
(_format verilog)
(_timespec "2024-03-26T20:23:00")
)
(_file "source/src/sys/sys_timecode.v"
(_format verilog)
(_timespec "2024-03-23T20:10:27")
)
(_file "source/src/input/genlock_input_module.v"
(_format verilog)
(_timespec "2024-03-05T19:17:12")
)
(_file "source/src/internal/internal_clock_generator.v"
(_format verilog)
(_timespec "2024-03-27T12:08:29")
)
(_file "source/src/internal/internal_genlock_generator.v"
(_format verilog)
(_timespec "2024-03-23T16:38:08")
)
(_file "source/src/sys/sys_genlock.v"
(_format verilog)
(_timespec "2024-03-05T16:10:48")
)
(_file "source/src/sys/sys_clock.v"
(_format verilog)
(_timespec "2024-03-27T12:19:38")
)
(_file "source/src/output/camera_sync_signal_output.v"
(_format verilog)
(_timespec "2024-04-11T09:29:51")
)
(_file "source/src/business/record_sig_generator.v"
(_format verilog)
(_timespec "2024-03-27T17:03:14")
)
(_file "source/src/sys_signal_delayer.v"
(_format verilog)
(_timespec "2024-03-27T14:18:37")
)
(_file "source/src/zutils/zutils_sig_delayer.v"
(_format verilog)
(_timespec "2024-03-21T17:36:08")
)
(_file "source/src/zutils/zutils_sig_delayer_v2.v"
(_format verilog)
(_timespec "2024-03-27T15:35:13")
)
(_file "source/src/zutils/zutils_pluse_delayer.v"
(_format verilog)
(_timespec "2024-03-22T22:01:26")
)
(_file "source/src/internal/internal_sig_generator_en_contrler.v"
(_format verilog)
(_timespec "2024-03-23T16:58:20")
)
)
)
(_widget wgt_my_ips_src
(_input
(_ip "ipcore/SPLL/SPLL.idf"
(_timespec "2024-02-27T20:28:55")
(_ip_source_item "ipcore/SPLL/SPLL.v"
(_timespec "2024-02-27T20:28:55")
)
)
(_ip "ipcore/genlock_sig_gen_pll/genlock_sig_gen_pll.idf"
(_timespec "2024-02-27T20:28:55")
)
(_ip "ipcore/ShiftRegister/ShiftRegister.idf"
(_timespec "2024-03-21T09:54:18")
(_ip_source_item "ipcore/ShiftRegister/rtl/ipm_distributed_sdpram_v1_2_ShiftRegister.v"
(_timespec "2024-03-21T09:54:18")
)
(_ip_source_item "ipcore/ShiftRegister/rtl/ipm_distributed_shiftregister_v1_2_ShiftRegister.v"
(_timespec "2024-03-21T09:54:18")
)
(_ip_source_item "ipcore/ShiftRegister/ShiftRegister.v"
(_timespec "2024-03-21T09:54:18")
)
)
)
)
(_widget wgt_import_logic_con_file
(_input
(_file "led_test.fdc"
(_format fdc)
(_timespec "2024-03-29T14:52:06")
)
)
)
(_widget wgt_edit_user_cons
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_simulation
(_option compiled_lib_location (_string "pango_sim_libraries"))
(_option verilog_options (_string ""))
(_option gen_param (_string ""))
(_option simulate_runtime (_string "10000ms"))
(_option sim_exe_dir (_string "C:/modeltech64_10.5/win64"))
(_input
(_file "source/test/test_transmitter.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/test/test_baud_rate_gen.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/test/test_top.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/test/test_uart_reg_reader.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/test/test_spi_reg_reader.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/test/test_timecode_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/test/test_timecode_decoder.v" + "test_timecode_decoder:"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
)
)
)
(_task tsk_compile
(_command cmd_compile
(_gci_state (_integer 2))
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-04-11T09:30:16")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-04-11T09:30:13")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-04-11T09:30:16")
)
)
)
(_widget wgt_rtl_view
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 2))
(_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-04-11T09:30:51")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-04-11T09:30:53")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-04-11T09:30:54")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-04-11T09:30:54")
)
)
)
(_widget wgt_tech_view
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_map_constraint
)
(_widget wgt_my_fic_src
)
(_widget wgt_inserter_gui_view
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 2))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-04-11T09:31:00")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-04-11T09:30:57")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-04-11T09:31:00")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-04-11T09:31:00")
)
)
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/led_test.pcf"
(_format pcf)
(_timespec "2024-04-11T09:31:00")
)
)
)
(_widget wgt_edit_route_cons
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 2))
(_option gplace_seed (_integer 8))
(_option seed_step (_integer 4))
(_option saved_outcome (_integer 4))
(_option parallel (_integer 4))
(_option share_router_control_signal (_boolean FALSE))
(_option check_clk_net_route_by_srb (_boolean FALSE))
(_option fix_hold_violation_in_route (_boolean FALSE))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-04-11T09:36:21")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-04-11T09:36:21")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-04-11T09:36:19")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-04-11T09:36:19")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-04-11T09:31:51")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-04-11T09:36:21")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-04-11T09:36:23")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_timing_analysis
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 2))
(_attribute _auto_exe_lock (_switch OFF))
(_db_output
(_file "report_timing/Top_rtp.adf"
(_format adif)
(_timespec "2024-04-11T09:36:32")
)
)
(_output
(_file "report_timing/Top.rtr"
(_format text)
(_timespec "2024-04-11T09:36:34")
)
(_file "report_timing/rtr.db"
(_format text)
(_timespec "2024-04-11T09:36:36")
)
)
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_power
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
(_command cmd_gen_netlist
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 2))
(_option unused_io_status (_string "KEEPER"))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-04-11T09:37:33")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-04-11T09:37:33")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-04-11T09:37:33")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-04-11T09:37:35")
)
)
)
)
)