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xsync_fpge_v2
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xsync_fpge_v2/led_test.pds

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(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sat Mar 2 22:45:22 2024")
(_version "1.0.5")
(_status "initial")
(_project
)
(_task tsk_setup
(_widget wgt_select_arch
(_input
(_part
(_family Logos)
(_device PGL22G)
(_speedgrade -6)
(_package MBG324)
)
)
)
(_widget wgt_my_design_src
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-03-02T17:50:26")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_pluse_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_edge_detecter.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_register.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_multiplexer_4t1.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_debug_led.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_signal_filter.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_clk_parser.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_multiplexer_16t1.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/output/ttl_output.v"
(_format verilog)
(_timespec "2024-03-02T22:23:06")
)
(_file "source/src/zutils/zutils_pwm_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_reset_sig_gen.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_multiplexer_2t1.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_multiplexer_32t1.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_muti_debug_signal_gen.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/xsync_internal_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_pwm_generator_advanced.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_register_advanced.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_genlock_clk_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_multiplexer_32t1_v2.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/ztutils_timecode_next_code.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_smpte_timecode_clk_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/xsync_internal_sub/internal_timecode_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/timecode/timecode_nextcode.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/timecode/timecode_basesig_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/timecode/timecode_serialization.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/timecode/timecode_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/output/timecode_output.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/input/timecode_input.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/timecode/timecode_decoder.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/timecode/timecode_sample_sig_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/input/ttl_input.v"
(_format verilog)
(_timespec "2024-03-02T22:21:29")
)
(_file "source/src/zutils/ztuils_sig_devide.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_signal_filter_advance.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/timecode/timecode_comparator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/src/zutils/zutils_freq_detector.v"
(_format verilog)
(_timespec "2024-03-02T17:47:04")
)
(_file "source/src/zutils/zsimple_pll.v"
(_format verilog)
(_timespec "2024-03-02T22:44:30")
)
(_file "source/src/zutils/zutils_freq_detector_v2.v"
(_format verilog)
(_timespec "2024-03-02T22:20:27")
)
)
)
(_widget wgt_my_ips_src
(_input
(_ip "ipcore/SPLL/SPLL.idf"
(_timespec "2024-02-27T20:28:55")
(_ip_source_item "ipcore/SPLL/SPLL.v"
(_timespec "2024-02-27T20:28:55")
)
)
(_ip "ipcore/genlock_sig_gen_pll/genlock_sig_gen_pll.idf"
(_timespec "2024-02-27T20:28:55")
)
)
)
(_widget wgt_import_logic_con_file
(_input
(_file "led_test.fdc"
(_format fdc)
(_timespec "2024-02-27T20:28:55")
)
)
)
(_widget wgt_edit_user_cons
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_simulation
(_option compiled_lib_location (_string "pango_sim_libraries"))
(_option verilog_options (_string ""))
(_option gen_param (_string ""))
(_option simulate_runtime (_string "10000ms"))
(_option sim_exe_dir (_string "C:/modeltech64_10.5/win64"))
(_input
(_file "source/test/test_transmitter.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/test/test_baud_rate_gen.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/test/test_top.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/test/test_uart_reg_reader.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/test/test_spi_reg_reader.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/test/test_timecode_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
(_file "source/test/test_timecode_decoder.v" + "test_timecode_decoder:"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
)
)
)
)
(_task tsk_compile
(_command cmd_compile
(_gci_state (_integer 2))
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-03-02T22:44:36")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-03-02T22:44:35")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-03-02T22:44:36")
)
)
)
(_widget wgt_rtl_view
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 2))
(_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-03-02T22:44:44")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-03-02T22:44:45")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-03-02T22:44:46")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-03-02T22:44:46")
)
)
)
(_widget wgt_tech_view
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_map_constraint
)
(_widget wgt_my_fic_src
)
(_widget wgt_inserter_gui_view
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 2))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-03-02T22:44:49")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-03-02T22:44:48")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-03-02T22:44:49")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-03-02T22:44:49")
)
)
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/led_test.pcf"
(_format pcf)
(_timespec "2024-03-02T22:44:49")
)
)
)
(_widget wgt_edit_route_cons
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 2))
(_option mode (_string "fast"))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-03-02T22:45:03")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-03-02T22:45:03")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-03-02T22:45:03")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-03-02T22:45:03")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-03-02T22:44:55")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-03-02T22:45:03")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-03-02T22:45:04")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_timing_analysis
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_power
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
(_command cmd_gen_netlist
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 2))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-03-02T22:45:21")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-03-02T22:45:21")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-03-02T22:45:21")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-03-02T22:45:22")
)
)
)
)
)