forked from p_lusterinc_xsync/xsync_fpge
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108 lines
3.1 KiB
108 lines
3.1 KiB
`timescale 10ns / 10ns
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module test_app_top;
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reg sys_clk;
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reg sys_rst_n;
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reg genlock_in_hsync;
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reg genlock_in_vsync;
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reg genlock_in_fsync;
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wire [9:0] genlock_out_dac;
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wire genlock_out_dac_clk;
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reg sync_ttl_in1;
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reg sync_ttl_in2;
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reg sync_ttl_in3;
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reg sync_ttl_in4;
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wire sync_ttl_out1;
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wire sync_ttl_out2;
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wire sync_ttl_out3;
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wire sync_ttl_out4;
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reg timecode_headphone_in;
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wire timecode_bnc_in;
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wire timecode_out_bnc;
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wire timecode_out_bnc_select;
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wire timecode_out_headphone;
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wire timecode_out_headphone_select;
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wire stm32if_start_signal_out;
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wire stm32if_camera_sync_out;
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wire stm32if_timecode_sync_out;
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//SPI 串行总线1
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reg spi1_cs_pin;
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reg spi1_clk_pin;
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reg spi1_rx_pin;
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wire spi1_tx_pin;
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AppTop appTop (
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.genlock_in_hsync (genlock_in_hsync),
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.genlock_in_vsync (genlock_in_vsync),
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.genlock_in_fsync (genlock_in_fsync),
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.genlock_out_dac (genlock_out_dac),
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.genlock_out_dac_clk (genlock_out_dac_clk),
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.sync_ttl_in1 (sync_ttl_in1),
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.sync_ttl_in2 (sync_ttl_in2),
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.sync_ttl_in3 (sync_ttl_in3),
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.sync_ttl_in4 (sync_ttl_in4),
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.sync_ttl_out1 (sync_ttl_out1),
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.sync_ttl_out2 (sync_ttl_out2),
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.sync_ttl_out3 (sync_ttl_out3),
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.sync_ttl_out4 (sync_ttl_out4),
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.timecode_headphone_in (timecode_headphone_in),
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.timecode_bnc_in (timecode_bnc_in),
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.timecode_out_bnc (timecode_out_bnc),
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.timecode_out_bnc_select (timecode_out_bnc_select),
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.timecode_out_headphone (timecode_out_headphone),
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.timecode_out_headphone_select(timecode_out_headphone_select),
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.stm32if_start_signal_out (stm32if_start_signal_out),
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.stm32if_camera_sync_out (stm32if_camera_sync_out),
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.stm32if_timecode_sync_out (stm32if_timecode_sync_out),
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.spi1_cs_pin (spi1_cs_pin),
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.spi1_clk_pin (spi1_clk_pin),
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.spi1_rx_pin (spi1_rx_pin),
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.spi1_tx_pin (spi1_tx_pin)
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);
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initial begin
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sys_clk = 0;
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sys_rst_n = 0;
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genlock_in_hsync = 0;
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genlock_in_vsync = 0;
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genlock_in_fsync = 0;
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sync_ttl_in1 = 0;
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sync_ttl_in2 = 0;
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sync_ttl_in3 = 0;
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sync_ttl_in4 = 0;
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timecode_headphone_in = 0;
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// timecode_bnc_in = 0;
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spi1_cs_pin = 0;
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spi1_clk_pin = 0;
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spi1_rx_pin = 0;
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#100;
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sys_rst_n = 1;
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#100;
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end
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assign timecode_bnc_in = timecode_out_bnc;
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always #5 sys_clk = ~sys_clk; // 50MHZ时钟
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endmodule
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