forked from p_lusterinc_xsync/xsync_fpge
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80 lines
3.1 KiB
80 lines
3.1 KiB
`include "config.v"
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module spi_reg_bus (
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input clk, //clock input
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input rst_n, //asynchronous reset input, low active
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//regbus interface
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output [31:0] addr,
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output [31:0] wr_data,
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output wr_en,
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//
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input wire spi_cs_pin, //
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input wire spi_clk_pin, //
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input wire spi_rx_pin, //
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output wire spi_tx_pin,
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input [31:0] rd_data_module_fpga_info,
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input [31:0] rd_data_module_ttlin,
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input [31:0] rd_data_module_timecode_in,
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input [31:0] rd_data_module_genlock_in,
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input [31:0] rd_data_module_internal_timecode,
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input [31:0] rd_data_module_internal_genlock,
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input [31:0] rd_data_module_internal_clock,
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input [31:0] rd_data_module_ttlout1,
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input [31:0] rd_data_module_ttlout2,
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input [31:0] rd_data_module_ttlout3,
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input [31:0] rd_data_module_ttlout4,
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input [31:0] rd_data_module_timecode_out,
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input [31:0] rd_data_module_genlock_out,
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input [31:0] rd_data_module_camera_sync_out,
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input [31:0] rd_data_module_sys_timecode,
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input [31:0] rd_data_module_sys_genlock,
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input [31:0] rd_data_module_sys_clock,
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input [31:0] rd_data_module_record_sig_generator
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);
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reg [31:0] rd_data;
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spi_reg_reader spi_reg_reader_inst (
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.clk (clk),
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.rst_n (rst_n),
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.addr (addr),
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.wr_data (wr_data),
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.wr_en (wr_en),
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.rd_data (rd_data),
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.spi_cs_pin (spi_cs_pin),
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.spi_clk_pin(spi_clk_pin),
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.spi_rx_pin (spi_rx_pin),
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.spi_tx_pin (spi_tx_pin)
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);
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// 数据路由
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wire [31:0] addr_group;
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assign addr_group = addr & 31'hFFFF_FFF0;
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always @(*) begin
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case (addr_group)
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`REGADDOFF__FPGA_INFO: rd_data <= rd_data_module_fpga_info;
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`REGADDOFF__TTLIN: rd_data <= rd_data_module_ttlin;
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`REGADDOFF__TIMECODE_IN: rd_data <= rd_data_module_timecode_in;
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`REGADDOFF__GENLOCK_IN: rd_data <= rd_data_module_genlock_in;
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`REGADDOFF__INTERNAL_TIMECODE: rd_data <= rd_data_module_internal_timecode;
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`REGADDOFF__INTERNAL_GENLOCK: rd_data <= rd_data_module_internal_genlock;
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`REGADDOFF__INTERNAL_CLOCK: rd_data <= rd_data_module_internal_clock;
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`REGADDOFF__TTLOUT1: rd_data <= rd_data_module_ttlout1;
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`REGADDOFF__TTLOUT2: rd_data <= rd_data_module_ttlout2;
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`REGADDOFF__TTLOUT3: rd_data <= rd_data_module_ttlout3;
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`REGADDOFF__TTLOUT4: rd_data <= rd_data_module_ttlout4;
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`REGADDOFF__TIMECODE_OUT: rd_data <= rd_data_module_timecode_out;
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`REGADDOFF__GENLOCK_OUT: rd_data <= rd_data_module_genlock_out;
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`REGADDOFF__CAMERA_SYNC_OUT: rd_data <= rd_data_module_camera_sync_out;
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`REGADDOFF__SYS_TIMECODE: rd_data <= rd_data_module_sys_timecode;
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`REGADDOFF__SYS_GENLOCK: rd_data <= rd_data_module_sys_genlock;
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`REGADDOFF__SYS_CLOCK: rd_data <= rd_data_module_sys_clock;
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`REGADDOFF__RECORD_SIG_GENERATOR: rd_data <= rd_data_module_record_sig_generator;
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default: rd_data <= 0;
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endcase
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end
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endmodule
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