xsync_stm32/usrc/service/reg_manager.c

#include "reg_manager.h"

#include "base_service/config_service.h"
#include "base_service/fpga_if.h"
#include "device_info.hpp"
#include "iflytop_xsync_protocol/iflytop_xsync_protocol.h"
#include "service/report_generator_service.h"

uint32_t m_action_val0;
uint32_t m_action_receipt;

void reg_manager_init() {}

/*******************************************************************************
 *                                   ACTION                                    *
 *******************************************************************************/
static uint32_t doaction(uint32_t action, uint32_t val) {
  if (action == xsync_stm32_action_generator_new_mac) {
    config_generate_random_mac();
    config_flush();
    return 0;
  } else if (action == xsync_stm32_action_factory_reset) {
    config_factory_reset();
    return 0;
  } else if (action == xsync_stm32_action_reboot) {
    NVIC_SystemReset();
    return 0;
  } else if (action == xsync_stm32_action_storage_cfg) {
    config_flush();
    return 0;
  }
  return 0;
}

uint32_t reg_manager_read_reg(uint32_t addr) {
  uint32_t    readbak = 0;
  static sn_t sncode;

  if (addr == kxsync_reg_software_version) {  // read only
    readbak = PC_VERSION;
  } else if (addr == kxsync_reg_manufacturer0) {  // read only
    readbak = PC_MANUFACTURER0;
  } else if (addr == kxsync_reg_manufacturer1) {  // read only
    readbak = PC_MANUFACTURER1;
  } else if (addr == kxsync_reg_product_type_id) {  // read only
    readbak = kxsync_device_type_xsync;
  } else if (addr == kxsync_reg_sn_id0) {  // read only
    device_info_get_sn(&sncode);
    readbak = sncode.sn0;
  } else if (addr == kxsync_reg_sn_id1) {  // read only
    device_info_get_sn(&sncode);
    readbak = sncode.sn1;
  } else if (addr == kxsync_reg_sn_id2) {  // read only
    device_info_get_sn(&sncode);
    readbak = sncode.sn2;
  } else if (addr == kxsync_reg_mac0) {  // read only
    memcpy(&readbak, config_get()->mac, 4);
  } else if (addr == kxsync_reg_mac1) {  // read only
    memcpy(&readbak, config_get()->mac + 4, 4);
  }
  /*******************************************************************************
   *                                   CONFIG                                    *
   *******************************************************************************/
  else if (addr == kxsync_reg_stm32_obtaining_ip_mode) {
    readbak = config_get()->obtaining_ip_mode;
  } else if (addr == kxsync_reg_stm32_ip) {
    readbak = config_get()->ip;
  } else if (addr == kxsync_reg_stm32_gw) {
    readbak = config_get()->gw;
  } else if (addr == kxsync_reg_stm32_netmask) {
    readbak = config_get()->netmask;
  } else if (addr == kxsync_reg_stm32_camera_sync_signal_count) {
    readbak = report_generator_service_xsync_get_count();
  } else if (addr == kxsync_reg_stm32_config0) {
    readbak = config_get()->config0;
  }
  /*******************************************************************************
   *                                   ACTION                                    *
   *******************************************************************************/
  else if (addr == kxsync_reg_stm32_action0) {
    readbak = m_action_receipt;
  } else if (addr == kxsync_reg_stm32_action_val0) {
    readbak = m_action_val0;
  }

  /*******************************************************************************
   *                             FPGAоƬ�Ĵ�����д                              *
   *******************************************************************************/
  else if (addr >= XYSNC_REG_FPGA_REG_START) {
    fpga_if_spi_read_data_02(addr, &readbak);
  }
  return readbak;
}
uint32_t reg_manager_write_reg(uint32_t addr, uint32_t value) {
  uint32_t readbak = 0;

  /*******************************************************************************
   *                                    INFO                                     *
   *******************************************************************************/
  if (addr == kxsync_reg_software_version) {  // read only
    readbak = reg_manager_read_reg(addr);
  } else if (addr == kxsync_reg_manufacturer0) {  // read only
    readbak = reg_manager_read_reg(addr);
  } else if (addr == kxsync_reg_manufacturer1) {  // read only
    readbak = reg_manager_read_reg(addr);
  } else if (addr == kxsync_reg_product_type_id) {  // read only
    readbak = reg_manager_read_reg(addr);
  }
  /*******************************************************************************
   *                                   CONFIG                                    *
   *******************************************************************************/
  else if (addr == kxsync_reg_stm32_obtaining_ip_mode) {
    config_get()->obtaining_ip_mode = value;
    readbak                         = config_get()->obtaining_ip_mode;
  } else if (addr == kxsync_reg_stm32_ip) {
    config_get()->ip = value;
    readbak          = config_get()->ip;
  } else if (addr == kxsync_reg_stm32_gw) {
    config_get()->gw = value;
    readbak          = config_get()->gw;
  } else if (addr == kxsync_reg_stm32_netmask) {
    config_get()->netmask = value;
    readbak               = config_get()->netmask;
  } else if (addr == kxsync_reg_stm32_camera_sync_signal_count) {
    report_generator_service_xsync_set_count(value);
    readbak = report_generator_service_xsync_get_count();
  } else if (addr == kxsync_reg_stm32_config0) {
    readbak = config_get()->config0;
  }

  /*******************************************************************************
   *                                   ACTION                                    *
   *******************************************************************************/
  else if (addr == kxsync_reg_stm32_action0) {
    readbak          = doaction(value, m_action_val0);
    m_action_receipt = readbak;
  } else if (addr == kxsync_reg_stm32_action_val0) {
    m_action_val0 = value;
    readbak       = value;
  }

  /*******************************************************************************
   *                             FPGAоƬ�Ĵ�����д                              *
   *******************************************************************************/
  else if (addr >= XYSNC_REG_FPGA_REG_START) {
    fpga_if_spi_write_data_02(addr, value, &readbak);
  }

  return readbak;
}

void reg_manager_read_regs(uint32_t start_addr, uint32_t nreg, uint32_t* datacache, uint32_t* len) {
  uint32_t _nreg = nreg;
  if (start_addr + nreg > MAX_REG_NUM) {
    _nreg = MAX_REG_NUM - start_addr;
  }

  if (*len < _nreg) {
    _nreg = *len;
  }

  for (size_t i = start_addr; i < _nreg; i++) {
    datacache[i] = reg_manager_read_reg(i);
  }
  *len = _nreg;
  return;
}